GB2347787A - Method of forming a tantalum oxide containing capacitor - Google Patents
Method of forming a tantalum oxide containing capacitor Download PDFInfo
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- GB2347787A GB2347787A GB9826790A GB9826790A GB2347787A GB 2347787 A GB2347787 A GB 2347787A GB 9826790 A GB9826790 A GB 9826790A GB 9826790 A GB9826790 A GB 9826790A GB 2347787 A GB2347787 A GB 2347787A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
- H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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Abstract
A method of forming a tantalum oxide containing capacitor which improves the Ta<SB>2</SB>O<SB>5</SB> film's properties, and includes providing a plasma silicon nitride film having a thickness of 20 100 angstroms, sufficient to prevent oxidation of a lower capacitor electrode, by a plasma nitridation process using a reactant gas during the step of preprocessing the surface of the lower capacitor electrode. The plasma silicon nitride film is formed by nitrifying a surface portion of the lower capacitor electrode by means of excitation of a reactant gas with a plasma. The plasma nitridation process is effective to form a sufficiently thick silicon nitride film on the lower capacitor electrode and anneal the resulting substrate in the same process chamber. Also, the method is applicable to a more simplified annealing mechanism, providing cost savings in the manufacture of DRAM devices, in the form of an ozone annealing process using thermal energy of more than about 400{C. In the ozone annealing process, the thermal energy is generated by heating a susceptor where wafers are placed.
Description
METHOD OF FORMING A TANTALUM OXIDE CONTAINING CAPACITOR
Field of the Invention
The present invention relates to a method of forming dynamic random access memory (DRAM) cell capacitor having high dielectric constant material, and more particularly to a method of forming a tantalum oxide (Ta205) containing capacitor.
Background of the Invention
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. one principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors. Such as trenched or stacked capacitors. Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell structure are important. The feature size of 256 Mb DRAMs will be on the order of 0.25 micron, and conventional dielectrics such as SiO2 and Si3N4 might not be suitable because of small dielectric constants.
Highly integrated memory devices, such as 256 Mbit DRAMs, are expected to require a very thin dielectric film for the 3-dimensional capacitor of cylindrically stacked or trench structures. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO2 equivalent thickness. Chemical vapor deposited (CVD) Ta205 films are considered to be very promising cell dielectric films for this purpose, as the dielectric constant of Ta2Os is approximately three times that of conventional Si3N4 capacitor dielectric films. However, one drawback associated with Ta205 dielectric films is undesired leakage current characteristics. Accordingly, although Ta205 material has inherently higher dielectric properties, as-deposited Ta2o5 typically produces unacceptable results due to leakage current.
One prior art technique disclosed includes exposing the polysilicon film to rapid thermal nitridation prior to subsequent deposition of the Ta2Os film. Such rapid thermal nitridation includes exposing the subjected polysilicon film to temperatures of from about 800 C. to 1100 C. for sixty seconds in an ammonia atmosphere at atmospheric pressure to form a silicon nitride film. The silicon nitride film formed thus acts as a barrier film to oxidation during Ta205 deposition and subsequent high temperature densification processes to prevent surface oxidation of the lower polysilicon electrode. Typical method of forming a Ta205 containing capacitor using the prior art process concepts is shown by a flow chart of Fig. 1.
Referring to Fig. 1, a lower capacitor electrode made from conductively doped polysilicon connects to a diffusion film which is formed in a silicon substrate. The polysilicon electrode is subjected to a rapid thermal processing step (in this case rapid thermal nitridation (RTN)) which converts a top surface of the polysilicon electrode into a silicon nitride film in step 10 of Fig. 1. Since the silicon nitride film formed thus is formed extremely thin, for example, about 5-10 angstroms thick due to inherent RTN process property, it can not prevent oxidation of the polysilicon electrode during subsequent oxidation annealing steps. In detail, oxygen atoms in a tantalum oxide film formed by subsequent step trend to be diffused penetrating the extremely thin silicon nitride film into the polysilicon electrode during subsequent oxidation annealing steps. Herein, if the silicon nitride film does not have a sufficient thickness, the oxygen atoms react with silicon of the polysilicon electrode to thereby form SiO2 film on the electrode. As a result, a SiO2 equivalent q is increased due to the RTN process and thereby capacitance of finally fabricated DRAM cell capacitor is lowered. Next, a capacitor cell dielectric material, tantalum oxide, is formed over the RTN film in step 12. The tantalum oxide film formed thus has the primary disadvantage as compared to insulators (for example, Si02 or Si3N4) with lower dielectric constants in that it has its fairly high conductivity with substantial current leakage due to deviation from stoichiometric composition of Ta: O, particularly, oxygen vacancies due to deficiency of oxygen in the tantalum oxide film. Therefore, the tantalum oxide film requires substantially a higher temperature annealing cycle to improve the film's electrical properties, particularly, to fill up the oxygen vacancies of the tantalum oxide film with oxygen atoms. One method is, as illustrated in step 14 of Fig. 1, an ozone (03) annealing process which generates oxygen atoms by exposing the resulting substrate to ultraviolet (UV) light under ozone ambient and fills up them into the oxygen vacancies.
However, the use of the ozone annealing process leads to increase in the production cost of
DRAM devices. This is because a UV light unit (shown by reference numeral 22 in Fig. 2) for exposing UV light through UV lamps 28 is very costly as compared with a heater unit (not shown in Fig. 2) for heating a susceptor 24 in a process chamber 20 where substrates 26 are placed. Next, an 2 annealing process is in step 16 carried out at a high temperature, for example, at about 750 C.-800 C. so as to eliminate carbon or hydrogen carbon compound containing in the tantalum oxide film. Finally, a titanium nitride (TiN) film is formed over the tantalum oxide film to form an upper capacitor electrode in step 18 of Fig.
I.
Furthermore, since in the prior art method the process steps of forming the Ta205 and Si3N4 films are performed separately in different process chambers, throughput of process steps is more longer.
Summary of the Invention
The present invention is intended to solve the problems, and it is an object of the invention to provide a method of forming a tantalum oxide containing capacitor in which a silicon nitride film serving as a barrier film has a thickness sufficient to prevent surface oxidation of a lower capacitor electrode during subsequent annealing process steps.
It is a further object of the present invention to provide a method of forming a tantalum oxide containing capacitor in which during an ozone annealing process for filling up oxygen vacancies in the tantalum oxide film with oxygen atoms generation of the oxygen atoms is accomplished by heating a wafer-placed susceptor.
It is another obj ect of the present invention to provide a method of forming a tantalum oxide containing capacitor in which process steps of forming the tantalum oxide and silicon nitride films are performed in the same process chamber.
According to one aspect of the present invention, a method of forming a capacitor on a substrate having a conductive diffusion film therein comprises the step of, after forming a lower capacitor electrode on the substrate to connect electrically to the conductive diffusion film, forming a plasma silicon nitride film on the lower capacitor electrode. With this method, the plasma silicon nitride film serves as a reaction prevention film having a thickness sufficient to prevent oxidation of the lower capacitor electrode during subsequent oxidation annealing processes. The method further comprises the steps of forming a high dielectric constant film of tantalum oxide on the plasma silicon nitride film, performing an ozone annealing process to fill up oxygen vacancies in the tantalum oxide film with oxygen atoms, performing an 2 annealing process to densify the tantalum oxide film, and forming an upper capacitor electrode on the plasma silicon nitride film, wherein the steps of forming the plasma silicon nitride film and performing the ozone annealing process are carried out in same process chamber.
In this method, the lower capacitor electrode is made of a conductively doped polysilicon.
In this method, the step of forming the plasma silicon nitride film comprises converting a surface portion of the lower capacitor electrode into a silicon nitride film by exciting a reactant gas with a plasma. The reactant gas is one selected from a group consisting of NH3, N2 and N20.
In this method, the thickness of the plasma silicon nitride film is in the range of 20-100 angstroms.
In this method, the oxygen atoms of the ozone annealing process are generated in the process chamber under ozone ambient by heating a susceptor where the substrate is placed.
In this method, the ozone annealing process is performed at a temperature of 300 C. to 600 C., preferably at 450 C., at a pressure of 1 mTorr to 50 Torr.
In this method, the plasma silicon nitride film after the 0 annealing process is converted into a silicon nitride composition which is composed of Si3N4 and SiO2 or SiON.
In this method, the 02 annealing process is performed at a temperature of 750 C.-800 C.
Brief Description of the Drawings
This invention may be understood and its objects will become apparent to those skilled in the art by reference to the accompanying drawings as follows:
Fig. 1 is a flow chart illustrating a prior art method of forming a tantalum oxide containing capacitor for DRAM applications;
Fig. 2 is a schematic view of an ozone annealing chamber used for generating oxygen atoms by exposing ultraviolet light under ozone ambient in accordance with the prior art method of Fig. 1;
Fig. 3 is a flow chart illustrating a novel method of forming a tantalum oxide containing capacitor for DRAM applications according to an embodiment of the present invention;
Figs. 4A through 4D are cross-sectional views showing the process steps ofthe novel method of forming a tantalum oxide containing capacitor for DRAM applications according to the embodiment of the present invention;
Fig. 5 is a schematic view of an ozone annealing chamber used for generating oxygen atoms by heating a wafer-placed susceptor under ozone ambient in accordance with the present invention; and
Fig. 6 is a graph depicting the measured results of the tantalum oxide containing capacitors fabricated according to the novel method of the present invention and the prior art method.
Detailed Descrintion of Preferred Embodiments The process of the present invention improves the Ta205 film's properties, providing a silicon nitride film having a thickness (for example, 20 ~ 100 angstroms) enough to prevent oxidation of the lower capacitor electrode, by a plasma nitridation process using a reactant gas (for example, NH3 gas) during the step of pre-processing the surface of the lower capacitor electrode. Herein, the plasma nitridation process means that a plasma silicon nitride film is formed by nitrifying a surface portion of the lower capacitor electrode by means of excitation of a reactant gas with a plasma. The plasma nitridation process is more effective not only to form the sufficiently thick silicon nitride film on the lower capacitor electrode but also to anneal the resulting substrate in the same process chamber.
Furthermore, the process of the present invention is applicable to the more simplified annealing mechanism, thereby providing cost saving of DRAM devices, by ozone annealing process using a susceptor-heating process for producing thermal energy of more than about 400 C. This is due to the more effective mechanism by the susceptor-heating ozone annealing as compared with regular UV ozone annealing. In the susceptor-heating ozone annealing process, the thermal energy is generated by heating a susceptor where wafers is placed. This makes the heater used ozone annealing process superior to UV ozone annealing in the light of cost saving of DRAM devices.
Fig. 3 is a flow chart illustrating processing steps according to a preferred embodiment of the invention, and Figs. 4A through 4D show by cross-sectional representation the process steps (substantially, corresponding to those of Fig. 3) according to the preferred embodiment of the invention.
Referring now to Fig. 3 and Fig. 4A, a supporting substrate 40 has been first prepared by prior fabrication steps of a conventional or non-conventional process. For example, the supporting substrate 40 may be comprised of a silicon wafer or simply a material that has been previously processed over a silicon (or germanium) substrate. Regardless of the nature of substrate, the general concept of the present invention will focus on the subsequent nitridation of capacitor plate electrode, particularly, lower capacitor electrode.
Referring again to Figs. 3, and 4A, a conductive diffusion film 41 has been formed
in the substrate 40. A lower capacitor electrode 42 is formed which connects to the diffusion film 41. The electrode 42 need not connect directly to the diffusion film 41 as there may also be a connecting conductor, such as a conductive plug (through not shown), formed between the diffusion film 41 and the electrode 42. Through not required, it is preferred that the electrode 42 is conductively doped polysilicon. Assuming the electrode 42 is polysilicon, it is now subjected to a pre-processing step shown in step 30 of Fig. 3, a plasma nitridation step using a reactant gas which converts a top surface of the polysilicon 42 into a plasma silicon nitride film (for example, Si3N4 film) 43 of about 20-100 angstroms in thickness.
The reactant gas is selected from a group consisting ofNH3, N2andN20. The plasma silicon nitride film 43 serves as a reaction prevention film to prevent surface oxidation of the electrode 42 during subsequent oxidation annealing steps. Herein, it is one of two key points of the present invention that the silicon nitride film 43 is formed having a thickness sufficient to prevent surface oxidation of the lower capacitor electrode 42 during subsequent oxidation annealing steps. If the comparatively thin silicon nitride film is formed on the top surface of the lower capacitor electrode 42 as in RTN (rapid thermal nitridation) of the prior art, it can not withstand against surface oxidation of the electrode 42 during subsequent oxidation annealing steps. This is because oxygen atoms trend to be diffuse penetrating the thin silicon nitride film into the electrode 42 during subsequent oxidation annealing steps.
Thus, if the silicon nitride film having a sufficient thickness is not formed on the lower capacitor electrode 42, the oxygen atoms in a tantalum oxide film to be formed by subsequent step react with silicon of the polysilicon electrode 42 to thereby form SiO2 film on the electrode 42. As a result, a SiO2 equivalent thickness Toxeq is increased and thereby capacitance of finally fabricated DRAM cell capacitor is lowered. However, with the present invention, since the plasma silicon nitride film 43 can be formed having a thickness sufficient to prevent surface oxidation of the electrode 42, formation of SiO2 film on the electrode can be suppressed, although subsequent oxidation annealing steps are carried out at high temperature.
Next, as shown in Fig. 4B and in step 32 of Fig. 3, a capacitor dielectric film 44 of preferably amorphous tantalum oxide (Ta205) is formed over the plasma silicon nitride film 43. The amorphous Ta2O5 film 44 is formed by, for an example, low pressure chemical vapor deposition (LPCVD) using Ta (OC2Hs) 5 with oxygen gas.
Subsequently, as shown in steps 34 and 36 of Fig. 3 and in Fig. 4C, the resulting substrate after formation of the capacitor dielectric film 44 is subjected to two continuous annealing process steps, ozone (03) annealing and 02 annealing. The ozone annealing process is carried out to fill up oxygen vacancies in the Ta20, film 44 with oxygen atoms in step 34 of Fig. 3. In this ozone annealing process, as shown in Fig. 5, oxygen atoms to be filled up into oxygen vacancies of the Ta205 film 44 are generated by heating by means of a heater 53 a susceptor 54 where wafers are placed. The ozone annealing process is performed at a temperature of 300 C. to 600 C., preferably at about 450 C., at a pressure of 1 mTorr to 50 Torr. Herein, it is the other key point of the present invention that for the ozone annealing process generation of oxygen atoms for filling up oxygen vacancies of the Ta205 film 44 can be accomplished by heating the wafer-placed susceptor 54 preferably to about 450 C. Use of susceptor heating process to generate oxygen atoms is more effective in simplification of ozone annealing mechanism as compared with regular UV ozone annealing process of the prior art. Also, during the ozone annealing process the silicon nitride film 43 may be converted into a film 43A which is composed of a composition of
Si3N4 and SiO2 or SiON. If the silicon nitride film 43 is formed having a very sufficient thickness, an extremely thin SiO2 (or SiON) film (not shown) enough to exert no influence on the DRAM cell capacitor may be formed on the silicon nitride film 43.
Of the two continuous annealing processes, th ou annealing process is in step 36 carried out at a high temperature, for example, at about 750 C. ~ 800 C. to eliminate carbon or hydrogen carbon compound (CXHy) containing in the amorphous Ta20, film 44 and to allow densification of the amorphous Ta205 film 44. Since such carbon and/or hydrogen carbon compound containing in the Ta2o5 film 44 serves as leakage current sources in
DRAM cell capacitors, those sources must be eliminated to improve undesired leakage characteristics of the Ta205 film 44. The dielectric constant of the amorphous Ta2Os film 44 is less than approximately twenty, but that ofthe Ta2Os film 44 densified by the 2 annealing process is changed to twenty four. Thus, the dielectric constant of the Ta205 film 44 densified thus is approximately six times that of SiO2. Furthermore, the initial thickness of the silicon nitride film 43 formed by the plasma nitrization was about 20-100 angstroms, and the resulting thickness after the 2 annealing process was about 25-105 angstroms. In addition to prevention of oxidation of the lower capacitor electrode, the resulting silicon nitride film 43A may serve as a leakage prevention barrier film so as to improve leakage of the Ta205 film 44. This is because the Ta20, film 44 has inherently high leakage current characteristics.
Next, as shown in step S38 of Fig. 3 and in Fig. 4D, a double-film structure electrode of low resistance which is comprised of a chemical vapor deposited TiN and conductively doped polysilicon is formed to thereby form an upper capacitor electrode 45. The process then continues by conventional methods to complete the DRAM device.
Fig. 6 shows the measured results of the tantalum oxide containing capacitors fabricated according to the novel method of the present invention and the prior art method, using MOS I-V measurement. As can be seen, since the silicon nitride film of the tantalum oxide containing capacitor which is fabricated by RTN process of the prior art is very extremely thin, the leakage was much worse, as shown by a curve line 60 of Fig. 6. This is because the silicon nitride film formed by RTN process does not have a thickness enough to prevent surface oxidation of the lower capacitor electrode, thus degrading the dielectric properties. But, as shown by a curve line 62 of Fig. 6, it can be seen that the dielectric properties of the tantalum oxide containing capacitor formed according to the present invention is improved.
While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the sprit and scope of this invention.
Claims (9)
- WHAT IS CLAIMED IS: 1. A method of forming a capacitor on a substrate having a conductive diffusion film therein, comprising the steps of : forming a lower capacitor electrode on the substrate to connect electrically to the conductive diffusion film; forming a plasma silicon nitride film on the lower capacitor electrode, the plasma silicon nitride film serving as a reaction prevention film having a thickness sufficient to prevent oxidation of the lower capacitor electrode during subsequent oxidation annealing processes; forming a high dielectric constant film of tantalum oxide on the plasma silicon nitride film; performing an ozone annealing process to fill up oxygen vacancies in the tantalum oxide film with oxygen atoms; performing an 02 annealing process to densify the tantalum oxide film; and forming an upper capacitor electrode on the plasma silicon nitride film, wherein the steps of forming the plasma silicon nitride film and performing the ozone annealing process are carried out in same process chamber.
- 2. The method according to claim 1, wherein the lower capacitor electrode is made of a conductively doped polysilicon.
- 3. The method according to claim 1, wherein the step of forming the plasma silicon nitride film comprises converting a surface portion of the lower capacitor electrode into a silicon nitride film by exciting a reactant gas with a plasma.
- 4. The method according to claim 3, wherein the reactant gas is one selected from a group consisting of NH3, N2 and N20.
- 5. The method according to claim 1, wherein the thickness of the plasma silicon nitride film is in the range of 20-100 angstroms.
- 6. The method according to claim 1, wherein the oxygen atoms of the ozone annealing process are generated in the process chamber under ozone ambient by heating a susceptor where the substrate is placed.
- 7. The method according to claim 1, wherein the ozone annealing process is performed at a temperature of300 C. to 600 C., preferably at 450 C., at a pressure of 1 mTorr to 50 Torr.
- 8. The method according to claim 1, wherein the plasma silicon nitride film after the 02 annealing process is converted into a silicon nitride composition which is composed of Si3N4 and SiO2 or SiON.
- 9. The method according to claim 1, wherein the 2 annealing process is performed at a temperature of 750 C.-800 C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9826790A GB2347787A (en) | 1998-12-04 | 1998-12-04 | Method of forming a tantalum oxide containing capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9826790A GB2347787A (en) | 1998-12-04 | 1998-12-04 | Method of forming a tantalum oxide containing capacitor |
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| Publication Number | Publication Date |
|---|---|
| GB9826790D0 GB9826790D0 (en) | 1999-01-27 |
| GB2347787A true GB2347787A (en) | 2000-09-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9826790A Withdrawn GB2347787A (en) | 1998-12-04 | 1998-12-04 | Method of forming a tantalum oxide containing capacitor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2358284A (en) * | 1999-07-02 | 2001-07-18 | Hyundai Electronics Ind | Capacitor with tantalum oxide Ta2O5 dielectric layer and silicon nitride layer formed on lower electrode surface |
| SG160198A1 (en) * | 2001-08-29 | 2010-04-29 | Tokyo Electron Ltd | Forming method and forming system of insulation film |
| CN102683583A (en) * | 2011-03-15 | 2012-09-19 | 北京大学 | Unipolar resistive random access memory and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0046868A2 (en) * | 1980-08-29 | 1982-03-10 | International Business Machines Corporation | Capacitor structure with dual dielectrics |
| JPS5984570A (en) * | 1982-11-08 | 1984-05-16 | Nec Corp | Manufacture of capacitor for semiconductor device |
| JPH07211791A (en) * | 1994-01-17 | 1995-08-11 | Hitachi Ltd | Semiconductor integrated circuit device and its manufacture |
| US5468687A (en) * | 1994-07-27 | 1995-11-21 | International Business Machines Corporation | Method of making TA2 O5 thin film by low temperature ozone plasma annealing (oxidation) |
-
1998
- 1998-12-04 GB GB9826790A patent/GB2347787A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0046868A2 (en) * | 1980-08-29 | 1982-03-10 | International Business Machines Corporation | Capacitor structure with dual dielectrics |
| JPS5984570A (en) * | 1982-11-08 | 1984-05-16 | Nec Corp | Manufacture of capacitor for semiconductor device |
| JPH07211791A (en) * | 1994-01-17 | 1995-08-11 | Hitachi Ltd | Semiconductor integrated circuit device and its manufacture |
| US5468687A (en) * | 1994-07-27 | 1995-11-21 | International Business Machines Corporation | Method of making TA2 O5 thin film by low temperature ozone plasma annealing (oxidation) |
Non-Patent Citations (2)
| Title |
|---|
| Patent Abstracts of Japan & JP 07 211 791 A * |
| Patent Abstracts of Japan & JP 59 084 570 A * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2358284A (en) * | 1999-07-02 | 2001-07-18 | Hyundai Electronics Ind | Capacitor with tantalum oxide Ta2O5 dielectric layer and silicon nitride layer formed on lower electrode surface |
| US6376299B1 (en) | 1999-07-02 | 2002-04-23 | Hyundai Electronics Industries, Co., Ltd. | Capacitor for semiconductor memory device and method of manufacturing the same |
| GB2358284B (en) * | 1999-07-02 | 2004-07-14 | Hyundai Electronics Ind | Method of manufacturing capacitor for semiconductor memory device |
| SG160198A1 (en) * | 2001-08-29 | 2010-04-29 | Tokyo Electron Ltd | Forming method and forming system of insulation film |
| CN102683583A (en) * | 2011-03-15 | 2012-09-19 | 北京大学 | Unipolar resistive random access memory and manufacturing method thereof |
| CN102683583B (en) * | 2011-03-15 | 2014-04-09 | 北京大学 | Unipolar resistive random access memory and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9826790D0 (en) | 1999-01-27 |
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| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |