CN1146961C - 形成电介质层的方法 - Google Patents

形成电介质层的方法 Download PDF

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CN1146961C
CN1146961C CNB991110935A CN99111093A CN1146961C CN 1146961 C CN1146961 C CN 1146961C CN B991110935 A CNB991110935 A CN B991110935A CN 99111093 A CN99111093 A CN 99111093A CN 1146961 C CN1146961 C CN 1146961C
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金注完
金成镇
赵昶贤
黄秉槿
李宰求
高宽协
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Samsung Electronics Co Ltd
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Abstract

一种形成电介质层的新方法。当图形之间形成的凹槽区域的纵横比大时，该方法包括淀积第一电介质层、腐蚀第一电介质层和淀积第二电介质层的步骤，从而可以形成无空隙的电介质层。

Description

形成电介质层的方法
技术领域
本发明涉及制造半导体器件的方法，特别涉及形成集成电路中的电介质层的方法。
背景技术
随着半导体器件集成度的增加，其图形尺寸也不断缩小。例如，甚至小于0.18微米的设计规则显然也将用于千兆位DRAM。当把存储器单元阵列的最小设计规则按比例缩小时，在单元阵列内结构的纵横比将增加。这种按比例缩小还会导致结构之间的凹槽区域的纵横比增加。由于要用填充材料例如电介质填充凹槽区域，但因凹槽区域尺寸小而使凹槽区域不能被电介质充分填充。结果，会出现如在SiliconProcessing for the VLSI Era，Vol.II，pp.194-199和U.S.P No.5494854中披露的空隙。在随后的工艺中这种空隙使导电图形之间形成桥接。
电介质层主要选自由USG(非掺杂的硅酸盐玻璃)、BPSG(硼磷硅酸盐玻璃)和HDP(高密度等离子体)氧化物构成的组中。
BPSG层完全填充凹槽区域而不会形成空隙。但是，在淀积BPSG层后，需要立即进行BPSG层的高温(大于800℃)回流工艺。这种高温回流不希望有地造成接合处周围杂质离子的扩散，因而难以制造具有短沟道长度的高集成化的器件。此外，在湿式化学腐蚀中BPSG层被速腐蚀(相对于湿式化学腐蚀有相当高的腐蚀率)，从而引起不良的垂直接触孔形貌。结果，难以按小尺寸形成期望的小接触孔。再有，由于不良的接触形貌，所以随后淀积在其上的导电层的均匀性差。
尽管不需要上述高温回流工艺，但由化学汽相淀积(CVD)形成的USG层不能完全填充凹槽区域，因而造成空隙(void)。这种USG凹槽区域填充特性不适合高集成化的器件。
但是，HDP氧化物有BPSG和USG二者的优点。就是说，由于HDP的低温工艺和较好的凹槽区域填充特性，因而HDP有利于以较小的热积聚填充凹槽区域。尽管HDP氧化物被用作电介质层，但当其纵横比大时，它也不可能完全填充凹槽区域。特别是对于纵横比为3∶1或更大的凹槽区域，HDP氧化物填充凹槽区域的能力是有限的。
图1a至图1c是在现有技术的形成电介质层工艺的所选各阶段半导体衬底的剖面图。
参照图1a，形成器件隔离层4，以在半导体衬底1内和半导体衬底1上限定有源区2和无源区。其中，由浅沟槽隔离技术制成器件隔离层4。在有源区2上顺序形成栅隔离层6、栅电极8和栅腐蚀掩模9。顺序淀积多晶硅层和硅化物层形成栅电极8。由厚度范围1000至2000的氮化硅层构成栅腐蚀掩模9。接着，将低浓度的杂质离子注入有源区2中，形成低浓度源/漏区。
在栅电极8和栅腐蚀掩模9两者的侧壁上形成栅间隔层10，从而完全形成栅结构。在淀积厚度范围为300至1500的氮化硅后，通过腐蚀工艺例如深腐蚀工艺形成栅间隔层10。
如图1b所示，在衬底1上淀积作为电介质层16的氧化硅。
最后，如图1c所示，通过CMP(化学机械研磨)工艺使层间电介质层16的上表面平面化。
但是，形成电介质层的上述方法有如图1b所示的在电介质层内形成空隙18的缺点。因此，当在衬底1上淀积例如用于形成基层(pad)电极的多晶硅层时，多晶硅层也渗入通过CMP工艺露出的空隙18中。结果，产生在基层电极之间的桥接。
此外，当在例如浅沟槽隔离的器件隔离区中出现这种空隙时，可发生栅电极之间的桥接。
因此，强烈要求淀积无空隙电介质层的工艺或去除已经形成于电介质层中的空隙的工艺。
发明内容
鉴于上述问题提供出本发明，因此本发明的目的在于提供形成无空隙电介质层的高集成化器件的方法。
按照本发明的一个方面，提供了一种在间隔开的栅位线之间的间隔中形成绝缘层的方法，上述栅位线在其上具有侧壁间隔层和硬掩模层，上述栅位线形成在半导体衬底上，该方法包括以下步骤：在具有多个栅位线的衬底上淀积高密度等离子体氧化物层；湿腐蚀高密度等离子体氧化物层，以在间隔中剩下部分高密度等离子体氧化物层，其中，仅仅在栅位线之间的间隔的下部存在高密度等离子体氧化物层的剩余部分；在具有高密度等离子体氧化物层的剩余部分的衬底上淀积用于填充间隔上部的电介质层。
附图说明
下面，通过参照附图，本领域的技术人员可以理解本发明，并且本发明的目的将是显而易见的，其中：
图1a至图1c是在按照现有技术形成电介质层的工艺的所选各阶段半导体衬底的剖面图；
图2a至图2d是在按照本发明第一实施例的形成电介质层工艺的所选各阶段半导体衬底的剖面图；
图3是按照本发明第二实施例的形成电介质层的新方法制造的半导体衬底的剖面图。
具体实施方式
下面，参照附图说明本发明的优选实施例。
参照图2和图3，按照本发明形成电介质层的新方法提供足以防止导电图形之间的桥接的无空隙电介质层。根据该方法，在包括其中形成的凹槽区域的底层区(即半导体衬底或形成于半导体衬底上的层)上淀积第一电介质层。接着，腐蚀第一电介质层，以便在凹槽区域的各底部留下一部分第一电介质层。在包括第一电介质层的底层区上淀积第二电介质层，以填充凹槽区域。
第一实施例
下面，参照附图2a至2d说明本发明第一实施例，图2a至图2d是在形成电介质层工艺的所选各阶段半导体衬底的剖面图。
参照图2a，形成器件隔离层102，以限定半导体衬底100上的有源区101和无源区。通过例如LOCOS(硅的局部氧化)方法或沟槽隔离方法形成器件隔离层102。在本实施例中，使用沟槽隔离方法形成器件隔离层102。在有源区101上形成栅绝缘层104后，在栅绝缘层104上形成栅结构110。结果，在两个相邻的栅结构之间形成凹槽区域。
例如，对于0.18微米器件来说，凹槽区域的上宽度和下宽度分别是0.08微米和0.1微米，而凹槽区域的高度为0.4微米。
栅结构110的形成包括在栅绝缘层104上淀积用于栅电极的导电层。把用于栅电极的导电层淀积至厚度约2000。在本实施例中，用于栅电极的导电层由多层结构构成，其中按顺序在栅绝缘层104上形成厚度为1000的多晶硅层106a和厚度1500的硅化物层106b。在用于栅电极的导电层上淀积用于栅腐蚀掩模的电介质层。用于栅腐蚀掩模的电介质层对随后的层间电介质114、116有腐蚀选择性。例如，可以由选自氮化硅、氧化硅、氧化氮硅和其化合物构成的组中的一个制成用于栅腐蚀掩模的电介质层。当把电介质层淀积至约1000至3600范围(最好约2600)的厚度时，可以形成厚度1000至2000(最好约1500)的氮化硅层、厚度200至800(最好约500 )的氧化硅层、厚度400至800(最好约600)的氧化氮硅层。氧化氮硅层用作为防反射层。
利用栅形成掩模顺序腐蚀用于栅腐蚀掩模的电介质层和用于栅电极的导电层，形成栅腐蚀掩模107和栅电极106。接着，把低浓度的杂质离子注入在栅电极106两侧的有源区101中，以形成低浓度的源/漏区。
另一方面，可以通过腐蚀电介质层形成栅电极106，形成图形层，随后利用图形层作为栅形成掩模腐蚀导电层。
接着，在衬底100上淀积用于栅间隔层的电介质层。正如栅腐蚀掩模107那样，由氮化硅、氧化硅和氧化氮硅构成用于栅间隔层的电介质层，并达到约300至1500范围的厚度。通过深腐蚀工艺，腐蚀用于栅间隔层的电介质层，在包括栅电极106和栅腐蚀掩模107的叠置层的侧壁上形成栅间隔层108。
如图1所示，如果需要升高，那么在所获得的半导体衬底上可以把氮化硅112淀积至50至200范围的厚度。把氮化硅112用作为腐蚀中止层，以防止器件隔离层102在形成存储电极接触孔或位线接触孔的腐蚀步骤期间被腐蚀。
在氮化硅112上淀积第一层间电介质114，几乎填充相邻栅结构110之间的凹槽区域。由氧化硅例如BPSG、USG、PE-TEOS、HDP氧化物或其组合物构成第一层间电介质114。把第一层间电介质114淀积至300至3000范围的厚度，最好为2000。在用CVD方法形成HDP氧化物的情况下，在本实施例中，利用惰性气体例如氩(Ar)或氦(He)作为溅射气体完成淀积第一层间电介质114的工艺。
当用He气作为溅射气体形成第一层间电介质114时，在以下条件下，例如在2000W至4000W范围的低频功率(400kHz)、500W至3000W范围的高频功率(13.56MHz)、利用包括流率范围为40sccm至120sccm的硅烷(SiH4)气体和流率范围为40sccm至300sccm的O2气体的工作气体的条件下，淀积第一层间电介质。最好低频功率为3000W，高频功率为1300W，SiH4气体的流率为80sccm，而O2气体的流率为120sccm。再有，当把流率范围为20sccm至600sccm的He气体用作为溅射气体时，如图2a中序号115所示，第一层间电介质114有被改善的淀积形貌。这是第一层间电介质114的反溅射(re-sputtering)量因原子质量为40的氩而较低的缘故。
接着，如图2b所示，腐蚀层间电介质114，在栅结构110之间的凹槽区域底部上留下一部分层间电介质114。作为腐蚀工艺，最好采用湿式腐蚀。这是由于相邻凹槽区域之间的空间不仅在垂直方向上可以进一步扩大，而且在水平方向上也可以进一步扩大的缘故。利用一般的氧化物腐蚀剂例如200∶1 HF、LAL(NH4F和HF的混合物)和BOE(缓冲氧化物腐蚀剂)完成湿式腐蚀工艺。
或者，还可以实施干式腐蚀工艺，或可以在原地(in-situe)实施湿式腐蚀和干式腐蚀工艺。利用从由Ar、CF4、CHF3、He、CH2F2和O2组成的组中至少选择一个作为腐蚀气体，完成干式腐蚀工艺。
图2b和图2c详细地表示利用干式和湿式腐蚀工艺的组合腐蚀第一层间电介质114的工艺。
参照图2b，首先腐蚀层间电介质114，在栅结构110之间的凹槽区域底部上留下一部分层间电介质。通过干式或湿式腐蚀完成第一层间电介质114的腐蚀。或者，通过干式和湿式腐蚀工艺的组合可以完成第一层间电介质114的腐蚀。
例如，利用干式腐蚀除去第一层间电介质114的一部分。第一层间电介质114的腐蚀量在深度上为150至500的范围内，最好深度为300。按以下条件完成干式腐蚀工艺。就是说，低频功率(400kHz)和高频功率(13.56MHz)两者有2000W至4500W的范围。用从氦气、O2气和其混合气体组成的组中至少选出的一种作为腐蚀气体，最好选择其混合气体作为腐蚀气体。当用氦气时，其流率为390sccm。当采用O2气时，其流率为30sccm。
如图2b所示，在干式腐蚀工艺后，第一层间电介质114的形貌被进一步改善。因此，可以立即完成第二层间电介质116的淀积而不进行湿式腐蚀工艺。
但是，为了增加无空隙层间电介质的裕量，期望在干式腐蚀工艺后立即实施湿式腐蚀工艺。在干式腐蚀工艺后按以下条件实施要立即进行的湿式腐蚀工艺。具体地说，在深度上，第一层间电介质114在100至400的范围内腐蚀，最好腐蚀200。接着，利用通常的氧化物腐蚀剂例如200∶1 HF、LAL或BOE完成湿式腐蚀工艺。作为这种湿式腐蚀工艺的结果，如图2C所示，使衬底100的上表面光滑。
随后，如图2d所示，在包括第一层间电介质114的衬底100上淀积第二层间电介质116，填充凹槽区域。结果，如图2d所示，形成无空隙层间电介质118，即第一和第二层间电介质114和116的组合。由与第一层间电介质114相同的材料例如HDP氧化物构成第二层间电介质116。或者，由与第一层间电介质114不同的材料例如USG或PE-TEOS构成第二层间电介质116。
把第二层间电介质116淀积至300到3000范围内的厚度，最好为2800。在下列条件下完成第二层间电介质116的淀积。就是说，低频功率在2000W至4000W的范围内，高频功率在500W至4000W的范围内。作为工作气体，硅烷(SiH4)气体的流率在40sccm至120sccm的范围内，而O2气的流率在40sccm至300sccm的范围内。再有，作为溅射气体，使用氦气体。最好低频功率为3000W，高频功率为2000W，硅烷的流率为120sccm，而氦的流率为390sccm。
按照本发明的第一实施例，由于在凹槽区域中留下一部分第一层间电介质114，所以可以降低凹槽区域的纵横比。因此，在淀积第二层间电介质116期间不产生空隙。
随后，利用深腐蚀工艺或CMP使第二层间电介质116的上表面平面化。
第二实施例
图3是说明本发明第二实施例的形成电介质层方法的剖面图。
参照图3，在半导体衬底200上顺序淀积基层氧化物202、基层氮化物204a和HTO氧化物204b，接着利用本领域中众所周知的光刻技术进行构图。结果，形成沟槽腐蚀掩模204，该腐蚀掩模包括基层氮化物204a，并形成HTO氧化物204b。利用沟槽腐蚀掩模204腐蚀衬底200，以在其上形成沟槽206，接着，进行热氧化，以在沟槽206的两侧壁和底部形成氧化膜。
在包括沟槽206的衬底200上淀积第一沟槽隔离层208。从USG和HDP氧化物组成的组中选择一个构成第一沟槽隔离层208。
接着，腐蚀第一沟槽隔离层208，以在沟槽206的底部上留下一部分第一沟槽隔离层。因此，可以除去在淀积第一沟槽隔离层208期间和淀积之后形成的空隙。由干式腐蚀、湿式腐蚀或干式和湿式腐蚀工艺的组合完成腐蚀第一沟槽隔离层208。
淀积第二沟槽隔离层210，填充沟槽206。由与第一沟槽隔离层208相同的材料构成第二沟槽隔离层210。或者，可以用与第一沟槽隔离层208不同的材料例如PE-TEOS构成第二沟槽隔离层210。作为淀积第二沟槽隔离层210的结果，完全形成无空隙的沟槽隔离层212。
利用溅射气体例如氩气或氦气完成淀积第一沟槽隔离层208和第二沟槽隔离层210的工艺。
本发明并不限于上述特定实例，这些实例仅是说明性的，而不是限定性的。本发明欲覆盖不脱离本发明的精神和范围的所有工艺和结构。例如，本发明可用于利用材料层例如导电层和电介质层填充凹槽区域或窄空间或凹槽部分的所有工艺。

Claims (7)

1.一种在间隔开的栅位线之间的间隔中形成绝缘层的方法，上述栅位线在其上具有侧壁间隔层和硬掩模层，上述栅位线形成在半导体衬底上，该方法包括以下步骤：
在具有多个栅位线的衬底上淀积高密度等离子体氧化物层；
湿腐蚀高密度等离子体氧化物层，以在间隔中剩下部分高密度等离子体氧化物层，其中，仅仅在栅位线之间的间隔的下部存在高密度等离子体氧化物层的剩余部分；
在具有高密度等离子体氧化物层的剩余部分的衬底上淀积用于填充间隔上部的电介质层。
2.如权利要求1的方法，其中，淀积高密度等离子体氧化物层是利用选自包括氩气和氦气的惰性气体组的第一溅射气体来完成的，并且淀积电介质层是利用包括氩气和氦气的惰性气体组的第二溅射气体来完成的。
3.如权利要求1的方法，还包括在湿腐蚀高密度等离子体氧化物层之前干腐蚀高密度等离子体氧化物层。
4.如权利要求1的方法，还包括在湿腐蚀高密度等离子体氧化物层之后干腐蚀高密度等离子体氧化物层。
5.如权利要求3的方法，其中，干腐蚀是利用选自包括氩气和氦气的组的溅射气体和为氧气的处理气体进行的。
6.如权利要求4的方法，其中，干腐蚀是利用选自包括氩气和氦气的组的溅射气体和为氧气的处理气体进行的。
7.如权利要求1的方法，还包括在淀积高密度等离子体氧化物层之前淀积腐蚀停止层，其中，腐蚀停止层具有相对于高密度等离子体氧化物层和电介质层的腐蚀选择率。
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US20010046777A1 (en) 2001-11-29
JP4726273B2 (ja) 2011-07-20
DE19935946A1 (de) 2000-02-10
JP2000077404A (ja) 2000-03-14
DE19935946B4 (de) 2007-08-16
CN1244032A (zh) 2000-02-09
KR100319185B1 (ko) 2002-01-04
US6337282B2 (en) 2002-01-08

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