KR100645458B1 - 습식 세정에 의한 어택을 방지할 수 있는 반도체 장치제조 방법 - Google Patents
습식 세정에 의한 어택을 방지할 수 있는 반도체 장치제조 방법 Download PDFInfo
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- KR100645458B1 KR100645458B1 KR1020030068702A KR20030068702A KR100645458B1 KR 100645458 B1 KR100645458 B1 KR 100645458B1 KR 1020030068702 A KR1020030068702 A KR 1020030068702A KR 20030068702 A KR20030068702 A KR 20030068702A KR 100645458 B1 KR100645458 B1 KR 100645458B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Abstract
Description
Claims (12)
- 기판 상에 이웃하는 복수의 도전패턴을 형성하는 단계;상기 도전패턴이 형성된 프로파일을 따라 식각정지막을 형성하는 단계;상기 식각정지막이 형성된 기판 전면에 유동성 절연막을 형성하는 단계;상기 유동성 절연막 상에 포토레지스트 패턴을 형성하는 단계;상기 포토레지스트 패턴을 식각마스크로 상기 이웃하는 도전패턴 사이의 상기 유동성 절연막을 식각하여 상기 식각정지막을 노출시키는 콘택홀을 형성하는 단계;상기 콘택홀이 형성된 전체 구조 상부에 어택방지막을 형성하는 단계;상기 콘택홀 저면에서의 상기 식각정지막을 제거하여 상기 기판을 노출시키는 단계; 및상기 콘택홀 내부를 세정하는 단계를 포함하는 반도체 장치 제조 방법.
- 제 1 항에 있어서,상기 어택방지막을 형성하는 단계는,상기 콘택홀이 형성된 전면에 질화막 계열의 제1 어택방지막을 형성하는 단계와, 상기 제1 어택방지막 상에 제2 어택방지막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제 2 항에 있어서,상기 제1 및 제2 어택방지막을 형성하는 단계에서, 플라즈마 화학기상증착 방식을 이용하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제 2 항에 있어서,상기 제1 어택방지막을 20Å 내지 150Å의 두께로 형성하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제 1 항에 있어서,상기 유동성 절연막은, SOG(Spin On Glass)막 또는 APL(Advanced Planarization Layer)를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제 5 항에 있어서,상기 유동성 절연막이 SOG막인 경우, 상기 유동성 절연막을 형성하는 단계 는,상기 SOG막을 도포하는 단계와, 상기 SOG막 큐어링하는 단계를 포함하며,상기 큐어링하는 단계는,H2O, O2, N2, H2 및 N2O으로 이루어진 그룹에서 선택된 적어도 하나의 가스 분위기 및 600℃ 내지 700℃의 온도 하에서, 10분 내지 60분 동안 실시하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제 1 항에 있어서,상기 세정하는 단계 후,상기 노출된 기판에 전기적으로 도통된 플러그를 형성하는 단계를 더 포함하며,상기 플러그를 형성하는 단계는,상기 노출된 기판에 도통되도록 플러그 형성용 물질을 형성하는 단계;상기 셀영역과 상기 주변회로영역의 단차를 줄이기 위해 증착된 상기 플러그 형성용 물질의 일부를 에치백하여 제거하는 단계; 및상기 도전패턴 상부가 노출되는 타겟으로 상기 플러그 형성용 물질을 연마하여 격리된 플러그를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제 7 항에 있어서,상기 플러그 형성용 물질을 형성하는 단계는,상기 기판 전면에 상기 플러그 형성용 물질을 증착하는 방식 또는 선택적 에피택셜 성장을 통해 상기 노출된 기판으로부터 성장시키는 방식을 이용하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제 1 항에 있어서,상기 포토레지스트 패턴은, T 타입, 라인 타입 또는 홀 타입 중 어느 하나의 형상을 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제 1 항에 있어서,상기 도전패턴은 게이트전극 패턴, 비트라인 또는 금속배선 중 어느 하나를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제 1 항에 있어서,상기 콘택홀을 형성하는 단계에서, 자기정렬콘택 식각 공정을 이용하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제 1 항에 있어서,상기 식각정지막을 제거하는 단계에서, 블랭킷 식각을 이용하는 것을 특징으로 하는 반도체 장치 제조 방법.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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KR1020030068702A KR100645458B1 (ko) | 2003-10-02 | 2003-10-02 | 습식 세정에 의한 어택을 방지할 수 있는 반도체 장치제조 방법 |
TW093117123A TWI251296B (en) | 2003-10-02 | 2004-06-15 | Method for fabricating semiconductor device capable of preventing damage by wet cleaning process |
US10/880,953 US6995056B2 (en) | 2003-10-02 | 2004-06-29 | Method for fabricating semiconductor device capable of preventing damage by wet cleaning process |
JP2004194518A JP4538272B2 (ja) | 2003-10-02 | 2004-06-30 | 湿式洗浄によるアタックを防止できる半導体装置の製造方法 |
CNB200410078265XA CN100565818C (zh) | 2003-10-02 | 2004-09-21 | 能防止湿式清洁过程导致之损坏的半导体装置的制造方法 |
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KR1020030068702A KR100645458B1 (ko) | 2003-10-02 | 2003-10-02 | 습식 세정에 의한 어택을 방지할 수 있는 반도체 장치제조 방법 |
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KR20050032750A KR20050032750A (ko) | 2005-04-08 |
KR100645458B1 true KR100645458B1 (ko) | 2006-11-13 |
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KR1020030068702A KR100645458B1 (ko) | 2003-10-02 | 2003-10-02 | 습식 세정에 의한 어택을 방지할 수 있는 반도체 장치제조 방법 |
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US (1) | US6995056B2 (ko) |
JP (1) | JP4538272B2 (ko) |
KR (1) | KR100645458B1 (ko) |
CN (1) | CN100565818C (ko) |
TW (1) | TWI251296B (ko) |
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US7524735B1 (en) | 2004-03-25 | 2009-04-28 | Novellus Systems, Inc | Flowable film dielectric gap fill process |
US9257302B1 (en) | 2004-03-25 | 2016-02-09 | Novellus Systems, Inc. | CVD flowable gap fill |
US8164141B2 (en) | 2005-10-06 | 2012-04-24 | United Microelectronics Corp. | Opening structure with sidewall of an opening covered with a dielectric thin film |
US8236702B2 (en) * | 2005-10-06 | 2012-08-07 | United Microelectronics Corp. | Method of fabricating openings and contact holes |
US7825034B2 (en) * | 2005-10-06 | 2010-11-02 | United Microelectronics Corp. | Method of fabricating openings and contact holes |
KR100818708B1 (ko) * | 2006-08-18 | 2008-04-01 | 주식회사 하이닉스반도체 | 표면 세정을 포함하는 반도체소자 제조방법 |
US9245739B2 (en) | 2006-11-01 | 2016-01-26 | Lam Research Corporation | Low-K oxide deposition by hydrolysis and condensation |
KR100909757B1 (ko) * | 2007-10-31 | 2009-07-29 | 주식회사 하이닉스반도체 | 반도체 소자의 층간절연막 형성 방법 |
TWI452419B (zh) * | 2008-01-28 | 2014-09-11 | Az Electronic Mat Ip Japan Kk | 細微圖案光罩及其製造方法、及使用其之細微圖案形成方法 |
US20090253080A1 (en) * | 2008-04-02 | 2009-10-08 | Dammel Ralph R | Photoresist Image-Forming Process Using Double Patterning |
US20090253081A1 (en) * | 2008-04-02 | 2009-10-08 | David Abdallah | Process for Shrinking Dimensions Between Photoresist Pattern Comprising a Pattern Hardening Step |
US20100040838A1 (en) * | 2008-08-15 | 2010-02-18 | Abdallah David J | Hardmask Process for Forming a Reverse Tone Image |
US8455176B2 (en) | 2008-11-12 | 2013-06-04 | Az Electronic Materials Usa Corp. | Coating composition |
JP4886021B2 (ja) * | 2008-12-16 | 2012-02-29 | エルピーダメモリ株式会社 | 半導体装置及びその製造方法 |
US20100183851A1 (en) * | 2009-01-21 | 2010-07-22 | Yi Cao | Photoresist Image-forming Process Using Double Patterning |
US8084186B2 (en) * | 2009-02-10 | 2011-12-27 | Az Electronic Materials Usa Corp. | Hardmask process for forming a reverse tone image using polysilazane |
KR101078732B1 (ko) * | 2009-06-24 | 2011-11-01 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
CN102005412B (zh) * | 2009-09-03 | 2012-12-12 | 中芯国际集成电路制造(上海)有限公司 | 接触孔的形成方法和接触插塞的形成方法 |
US8278224B1 (en) | 2009-09-24 | 2012-10-02 | Novellus Systems, Inc. | Flowable oxide deposition using rapid delivery of process gases |
US8685867B1 (en) * | 2010-12-09 | 2014-04-01 | Novellus Systems, Inc. | Premetal dielectric integration process |
US9719169B2 (en) | 2010-12-20 | 2017-08-01 | Novellus Systems, Inc. | System and apparatus for flowable deposition in semiconductor fabrication |
US8846536B2 (en) | 2012-03-05 | 2014-09-30 | Novellus Systems, Inc. | Flowable oxide film with tunable wet etch rate |
TWI473206B (zh) * | 2012-07-03 | 2015-02-11 | Powerchip Technology Corp | 接觸窗的形成方法 |
US9847222B2 (en) | 2013-10-25 | 2017-12-19 | Lam Research Corporation | Treatment for flowable dielectric deposition on substrate surfaces |
US9349939B2 (en) * | 2014-05-23 | 2016-05-24 | Qualcomm Incorporated | Etch-resistant protective coating for a magnetic tunnel junction device |
US10049921B2 (en) | 2014-08-20 | 2018-08-14 | Lam Research Corporation | Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor |
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US10388546B2 (en) | 2015-11-16 | 2019-08-20 | Lam Research Corporation | Apparatus for UV flowable dielectric |
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KR100426811B1 (ko) * | 2001-07-12 | 2004-04-08 | 삼성전자주식회사 | 셀프얼라인 콘택을 갖는 반도체 소자 및 그의 제조방법 |
US6436841B1 (en) | 2001-09-10 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Selectivity oxide-to-oxynitride etch process using a fluorine containing gas, an inert gas and a weak oxidant |
US6861751B2 (en) * | 2002-12-09 | 2005-03-01 | Integrated Device Technology, Inc. | Etch stop layer for use in a self-aligned contact etch |
US6841396B2 (en) * | 2003-05-19 | 2005-01-11 | Texas Instruments Incorporated | VIA0 etch process for FRAM integration |
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2003
- 2003-10-02 KR KR1020030068702A patent/KR100645458B1/ko active IP Right Grant
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2004
- 2004-06-15 TW TW093117123A patent/TWI251296B/zh not_active IP Right Cessation
- 2004-06-29 US US10/880,953 patent/US6995056B2/en active Active
- 2004-06-30 JP JP2004194518A patent/JP4538272B2/ja not_active Expired - Fee Related
- 2004-09-21 CN CNB200410078265XA patent/CN100565818C/zh active Active
Also Published As
Publication number | Publication date |
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KR20050032750A (ko) | 2005-04-08 |
CN1606138A (zh) | 2005-04-13 |
JP4538272B2 (ja) | 2010-09-08 |
TW200534389A (en) | 2005-10-16 |
CN100565818C (zh) | 2009-12-02 |
JP2005117016A (ja) | 2005-04-28 |
TWI251296B (en) | 2006-03-11 |
US6995056B2 (en) | 2006-02-07 |
US20050074965A1 (en) | 2005-04-07 |
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