CN1290176C - 形成半导体器件接触的方法 - Google Patents

形成半导体器件接触的方法 Download PDF

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CN1290176C
CN1290176C CNB2004100619499A CN200410061949A CN1290176C CN 1290176 C CN1290176 C CN 1290176C CN B2004100619499 A CNB2004100619499 A CN B2004100619499A CN 200410061949 A CN200410061949 A CN 200410061949A CN 1290176 C CN1290176 C CN 1290176C
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金亨涣
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Abstract

本发明公开了一种形成半导体器件接触的方法。特别是在形成半导体器件接触的方法中，为了形成线型存储节点接触，在浅沟槽隔离蚀刻工艺中使用对氧化膜具有高选择性的化学机械抛光浆料研磨层间介质层，在半导体衬底上再次形成具有预定厚度的层间介质层，以确保足够的蚀刻裕度用于随后的蚀刻工艺，由此防止位线硬掩模氮化物膜的损耗并降低存储节点和位线之间的自对准接触失败。

Description

形成半导体器件接触的方法
技术领域
本发明一般涉及形成半导体器件接触的方法，尤其涉及这样一种形成半导体器件接触的方法，在该方法中，为了形成线型存储节点接触(aline-type storage node contact)(以下称为“SNC”)，在STI(浅沟槽隔离)(shallow trench isolation)蚀刻工艺中使用对氧化膜具有高选择性的化学机械抛光(CMP)浆料研磨层间介质(interlayer dielectric)(以下称为“ILD”)层，并且在半导体衬底上再次形成具有预定厚度的ILD层以确保足够的蚀刻裕度(etching margin)用于随后的蚀刻工艺，由此防止位线硬掩模氮化物膜的损耗并降低存储节点和位线之间的自对准接触(以下称为“SAC”)失败。
背景技术
精细图案形成技术的发展影响半导体器件的高集成趋势，半导体存储器单元尺寸的减小取决于半导体存储器的高集成度和高容量。
特别是在引领集成度增加的DRAM(动态随机存取存储器)情况中，按照存储单元尺寸的减小垂直结构变得复杂。结果，为了增加电容器的有效面积，在形成位线之后形成电容器。
此外，当形成位线时，形成用于在晶体管和电容之间进行电操作的SNC是重要的。
通过线型SAC工艺形成SNC。在线型SAC工艺中，构图位线，形成ILD层并蚀刻除用于隔离接触的部分ILD层之外的半导体衬底。
这里，为了确保用于蚀刻工艺的蚀刻裕度，在对ILD层的平坦化工艺中需要在位线上保留具有预定厚度的ILD层。但是，随着半导体器件变得微细，难于在位线上对ILD层进行平坦化工艺，由此形成不均匀的ILD层。
图1A到1F是说明形成半导体器件接触的传统方法的示图。
参照图1A，使用氧化物膜的第一ILD层5形成在具有单元晶体管(未示出)和下部多晶硅(lower polysilicon plug)塞3的半导体衬底1上。
如图1B所示，在图1A的第一ILD层5上形成用于位线的阻挡层(未示出)材料、用于位线的导电层(未示出)和硬掩模氮化物膜(未示出)的层叠结构，选择性地蚀刻该层叠结构，形成包括用于位线的阻挡层图案7、用于位线的导电层图案9和硬掩模氮化物膜图案11的位线13。
如图1C所示，在图1B的位线侧壁形成位线隔离物15。
如图1D所示，在包括图1C的位线的半导体衬底上形成第二ILD层17。
使用常见化学机械抛光浆料研磨图1D的第二ILD层17。由于采用了该研磨工艺，在位线13上保留具有预定厚度的ILD层。
包括胶体或雾化SiO2研磨剂和诸如KOH/NH4OH之类添加剂的常见化学机械抛光浆料具有从10到11变化的pH，并具有氮化物膜对氧化物膜的选择比为1∶4范围的研磨选择性。
如图1F所示，对图1E所示的平坦化的第二ILD层17进行SNC蚀刻直到露出多晶硅塞3，形成SNC开口19。
当使用常见浆料研磨ILD层以在位线上保留具有预定厚度的ILD层时，位线上的ILD层厚度具有很大的差异，由此引起在随后的SNC蚀刻工艺中硬掩模氮化物膜的损耗。
例如，如果在位线上形成的具有很厚厚度的ILD层中确定形成SNC开口的蚀刻目标之后进行蚀刻工艺，如图2A所示在具有很厚厚度的ILD层17上硬掩模氮化物11严重地损耗。这样，因为通过SNC化学机械抛光工艺硬掩模氮化物膜的厚度变得更薄，在形成随后存储节点(SN)的蚀刻工艺中产生位线和SAC的误差。
另一方面，如果在位线上形成的具有薄厚度的ILD层中确定蚀刻目标之后进行蚀刻工艺，如图2B所示具有很薄厚度的ILD层17的上部不研磨，而是保留在位线上。结果，SNC没有开口。
该缺点在蚀刻工艺中在SNC区的面积差和底区的尺寸差之间产生。结果，难于在整个晶片的表面上体现均匀的器件特性。
发明内容
本发明的目的是提供一种形成半导体器件接触的方法，其中使用对氧化物膜比对氮化物膜有更优良研磨选择性的化学机械抛光浆料研磨ILD层，并且再次淀积具有预定厚度的ILD层，以在位线上形成均匀的ILD层，由此确保用于进行随后SNC蚀刻工艺的足够的蚀刻裕度。
在实施例中，形成半导体器件的方法包括如下步骤：
在具有单元晶体管(cell transister)和下多晶硅塞的半导体衬底上形成第一层间介质(ILD)层；
在第一ILD层上形成由阻挡层、导电层和硬掩模氮化物膜构成的层叠结构，并选择性地蚀刻该层叠结构，以形成位线；
在位线侧壁形成氧化物膜隔离物；
在包括位线的半导体衬底上形成第二ILD层；
使用对氧化物膜具有高选择性的化学机械抛光浆料研磨第二ILD层，以露出硬掩模氮化物膜；
在研磨后的第二层间介质层和该硬掩模氮化物膜上形成第三ILD层；和
进行蚀刻工艺，以形成存储节点接触的开口，暴露出下部多晶硅塞。
附图说明
图1A至1F是说明形成半导体器件传统方法的示图。
图2A至2B是说明在按照传统方法形成的位线上ILD层厚度的剖面图。
图3A至3G是说明按照本发明的实施例形成半导体器件接触的方法的示图。
具体实施方式
将参照附图详细介绍本发明。
参照图3A，在具有单元晶体管(未示出)和下多晶硅塞23的半导体衬底21上通过淀积氧化物膜形成第一ILD层25。
如图3B所示，在图3A的第一ILD层25上形成由用于位线的阻挡层(未示出)材料、用于位线的导电层(未示出)和硬掩模氮化物膜(未示出)构成的层叠结构，选择性地蚀刻该层叠结构，形成包括用于位线的阻挡层图案27、用于位线的导电层图案29和硬掩模氮化物膜图案31的位线33。
用于位线的阻挡层材料由Ti/TiN构成，导电层是钨。
如图3C所示，在图3B的位线33的侧壁形成位线隔离物35。
如图3D所示，在图3C的半导体衬底上形成第二ILD层37。这里，优选使用常见的氧化物膜形成第一ILD层和第二ILD层。
如图3E所示，通过使用对氧化物膜具有选择性的化学机械抛光浆料在图3D的第二ILD层37上进行化学机械抛光工艺，以暴露出硬掩模氮化物膜31作为研磨阻挡膜。
用于氧化物膜的化学机械抛光浆料包括作为研磨剂的二氧化铈(CeO2)并具有分布范围从4到10的pH，优选浆料具有从6到8的pH，如同用于STI的化学机械抛光浆料组分所具有的pH那样。使用蒸馏水或超高纯水作为溶剂。
而且，用于氧化物膜的化学机械抛光浆料包括有机聚合物作为添加剂，优选为聚丙烯酸盐。
研磨剂的量的分布范围从0.5到10wt％，优选从1到5wt％，添加剂的量的分布范围从0.5到10wt％，优选从1到5wt％。
根据本发明的一个实施例的浆料组分的氮化物膜对氧化物膜的选择比的范围为1∶10～200，优选1∶30～200。
使用氮化物膜对氧化物膜选择比为1∶10～200的高选择比的氧化物膜化学机械抛光浆料研磨第二ILD层37，以露出硬掩模氮化物膜。
如图3F所示，在通过图3E的研磨工艺平坦化的第二ILD层37上均匀地形成第三ILD层38。
这里，选自包括HDP PSG(高密度等离子体磷硅酸盐玻璃)、BPSG(硼磷硅酸盐玻璃)、PSG(磷硅酸盐玻璃)、HDP USG(高密度等离子体未掺杂硅酸盐玻璃)、FSG(氟硅酸盐玻璃)、PE-SiH4(等离子体增强硅烷)、LP-TEOS(低压四乙氧基硅酸盐玻璃)和PE-TEOS(等离子体增强四乙氧基硅酸盐玻璃)的组的原料构成第三ILD层38。
这里，第三ILD层的厚度范围从500到5000，优选从500到2000。
对图3F的半导体衬底进行SNC蚀刻工艺，以形成露出下部的多晶硅塞的SNC的开口39，如图3G所示那样。
这样，在硬掩模氮化物膜被暴露出并且具有预定厚度的第三ILD层在硬掩模氮化物膜上再次淀积之后，具有均匀厚度的ILD层形成在位线上。结果，在随后形成SNC的蚀刻工艺中防止了硬掩模氮化物膜的损耗，由此确保了足够的蚀刻裕度并降低了SN和位线之间的误差。
如前所述，在本发明的实施例中，在研磨第二ILD层被研磨之后，在第二ILD层上形成具有预定厚度的第三ILD层。结果，在随后形成SNC的蚀刻工艺中防止了位线硬掩模氮化物膜的损耗，由此确保了足够的蚀刻裕度并降低了SN和位线之间的误差。由此，能够制造稳定的器件。

Claims (16)

1.一种形成半导体器件接触的方法，包括如下步骤：
在具有单元晶体管和下部多晶硅塞的半导体衬底上形成第一层间介质层；
在所述第一层间介质层上形成由阻挡层、导电层和硬掩模氮化物膜构成的层叠结构，并选择性地蚀刻所述层叠结构，以形成位线；
在所述位线的侧壁上形成氧化物膜隔离物；
在包括所述位线的所述半导体衬底上形成第二层间介质层；
使用具有对氧化物膜的高选择性的化学机械抛光浆料研磨第二层间介质层，以暴露出所述硬掩模氮化物膜；
在研磨后的第二层间介质层和该硬掩模氮化物膜上形成第三层间介质层；和
进行蚀刻工艺，以形成存储节点接触的开口，暴露出下部多晶硅塞。
2.按照权利要求1所述的方法，其中所述化学机械抛光浆料具有分布范围从4到10的pH。
3.按照权利要求1所述的方法，其中所述化学机械抛光浆料具有分布范围从6到8的pH。
4.按照权利要求1所述的方法，其中所述化学机械抛光浆料包括作为溶剂的蒸馏水或超高纯水。
5.按照权利要求1所述的方法，其中所述化学机械抛光浆料包括作为研磨剂的二氧化铈。
6.按照权利要求5所述的方法，其中所述研磨剂的数量的分布范围为所述化学机械抛光浆料的0.5到10wt％。
7.按照权利要求1所述的方法，其中所述化学机械抛光浆料包括作为添加剂的有机聚合物。
8.按照权利要求7所述的方法，其中所述有机聚合物是聚丙烯酸盐。
9.按照权利要求7所述的方法，其中所述化学机械抛光浆料添加剂的数量的分布范围为所述化学机械抛光浆料的0.5到10wt％。
10.按照权利要求1所述的方法，其中所述化学机械抛光浆料的氮化物膜对氧化物膜的选择比的范围为1∶10～200。
11.按照权利要求1所述的方法，其中所述化学机械抛光浆料的氮化物膜对氧化物膜的选择比的范围为1∶30～200。
12.按照权利要求1所述的方法，其中所述阻挡层由Ti/TiN形成。
13.按照权利要求1所述的方法，其中所述导电层是钨。
14.按照权利要求1所述的方法，其中所述第三层间介质层是由选自包括高密度等离子体磷硅酸盐玻璃、硼磷硅酸盐玻璃、磷硅酸盐玻璃、高密度等离子体未掺杂硅酸盐玻璃、氟硅酸盐玻璃、等离子体增强硅烷、低压四乙氧基硅酸盐玻璃和等离子体增强四乙氧基硅酸盐玻璃的组的原料构成。
15.按照权利要求1所述的方法，其中所述第三层间介质层的厚度范围从500到5000。
16.按照权利要求1所述的方法，其中所述第三层间介质层的厚度范围从500到2000。
CNB2004100619499A 2003-10-22 2004-06-29 形成半导体器件接触的方法 Expired - Fee Related CN1290176C (zh)

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