CN107017154A - 使用多重光刻多重蚀刻的通孔图案化 - Google Patents
使用多重光刻多重蚀刻的通孔图案化 Download PDFInfo
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- CN107017154A CN107017154A CN201710015006.XA CN201710015006A CN107017154A CN 107017154 A CN107017154 A CN 107017154A CN 201710015006 A CN201710015006 A CN 201710015006A CN 107017154 A CN107017154 A CN 107017154A
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- mask layer
- layer
- dielectric
- photoresist
- etching
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Classifications
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Abstract
一种方法包括形成介电层,在介电层上方形成光刻胶,在光刻胶上方形成第一掩模层,以及在第一掩模层上方形成第二掩模层。执行第一光刻第一蚀刻以在第二掩模层中形成第一通孔图案,其中,第一光刻第一蚀刻停止在第一掩模层的顶面上。执行第二光刻第二蚀刻以在第二掩模层中形成第二通孔图案,其中,第二光刻第二蚀刻停止在第一掩模层的顶面上。使用第二掩模层作为蚀刻掩模以蚀刻第一掩模层。蚀刻光刻胶和介电层以同时将第一通孔图案和第二通孔图案转印至介电层内。本发明实施例涉及使用多重光刻多重蚀刻的通孔图案化的方法。
Description
技术领域
本发明实施例涉及使用多重光刻多重蚀刻的通孔图案化的方法。
背景技术
为了在晶圆上形成集成电路的部件,使用光刻工艺。典型的光刻工艺涉及施加光刻胶和在光刻胶上限定图案。在光刻掩模中限定图案化的光刻胶中的图案,并且通过光刻掩模中的透明部分或不透明部分限定。然后,将图案化的光刻胶中的图案通过蚀刻步骤转印至下面的部件,其中,图案化的光刻胶用作蚀刻掩模。在蚀刻步骤之后,去除图案化的光刻胶。
通过集成电路日渐按比例缩小,光学邻近效应对从光刻胶转印图案至晶圆带来越来越大的问题。当两个分隔开的部件彼此太接近时,光学邻近效应可能引起形成的部件彼此之间的短路。为了解决这样的问题,双重图案化技术被引入以增加部件密度而不引起光学邻近效应。双重图案化技术中的一种使用双重图案化双重蚀刻(2P2E)。靠近的部件被分成两个光刻掩模,两个光刻掩模用于暴露出同一光刻胶或两个光刻胶,以使靠近的图案可以被转印至诸如低k介电层的同一层。在双重图案化光刻掩模的每个中,部件之间的距离增加超过单一图案化掩模中的部件之间的距离,且当需要时可以部分地加倍。双重图案化光刻掩模中的距离大于光学邻近效应的阈值距离,并且因此阈值距离至少被减小或基本上消除。
发明内容
根据本发明的一个实施例,提供了一种使用多重光刻多重蚀刻的通孔图案化的方法,包括:形成介电层;在所述介电层上方形成光刻胶;在所述光刻胶上方形成第一掩模层;在所述第一掩模层上方形成第二掩模层;执行第一光刻第一蚀刻以在所述第二掩模层中形成第一通孔图案,其中,所述第一光刻第一蚀刻停止在所述第一掩模层的顶面上;执行第二光刻第二蚀刻以在所述第二掩模层中形成第二通孔图案,其中,所述第二光刻第二蚀刻停止在所述第一掩模层的所述顶面上;使用所述第二掩模层作为蚀刻掩模蚀刻所述第一掩模层;以及蚀刻所述光刻胶和所述介电层以同时将所述第一通孔图案和所述第二通孔图案转印至所述介电层内。
根据本发明的另一实施例,还提供了一种使用多重光刻多重蚀刻的通孔图案化的方法,包括:在衬底上方形成低k介电层;蚀刻所述低k介电层以形成沟槽;在所述低k介电层上方形成第一掩模层;在所述第一掩模层上方形成第二掩模层;在第一图案化步骤中,在所述第二掩模层中形成第一通孔图案;在第二图案化步骤中,在所述第二掩模层中形成第二通孔图案;使用第二掩模层作为蚀刻掩模蚀刻所述第一掩模层以同时将所述第一通孔图案和所述第二通孔图案转印至所述第一掩模层内;以及使用所述第一掩模层作为蚀刻掩模蚀刻所述低k介电层以在所述低k介电层中形成第一通孔开口和第二通孔开口。
根据本发明的又一实施例,还提供了一种使用多重光刻多重蚀刻的通孔图案化的方法,包括:在半导体衬底上方形成低k介电层;蚀刻所述低k介电层以形成第一沟槽和第二沟槽;施加具有填充所述第一沟槽的第一部分和填充所述第二沟槽的第二部分的光刻胶;形成覆盖所述光刻胶的第一掩模层,其中,所述第一掩模层是平坦的毯式层;在所述第一掩模层上面形成第二掩模层;使用分开的工艺步骤在所述第二掩模层中形成第一通孔开口和第二通孔开口,其中,当形成所述第一通孔开口和所述第二通孔开口时,所述光刻胶被所述第一掩模层完全地覆盖;蚀刻所述第一掩模层以将所述第一通孔开口和所述第二通孔开口延伸至所述第一掩模层内;所述第一通孔开口和所述第二通孔开口分别地延伸至所述光刻胶的所述第一部分和所述第二部分内;以及使用所述光刻胶作为蚀刻掩模蚀刻所述低k介电层以在所述低k介电层中分别形成第一通孔开口和第二通孔开口。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是,根据工业中的标准实践,对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或缩小。
图1至图13示出了根据一些实施例的金属线和下面的通孔的形成中的中间阶段的截面图。
图14示出了根据一些实施例的包括下面的且连接至同一金属线的两个通孔的集成电路结构的截面图。
图15示出了根据一些实施例的用于形成包括下面的且连接至上面对应的金属线的两个通孔的集成电路结构的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语,以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而在此使用的空间相对描述符可以同样地作相应的解释。
根据各个示例性实施例提供了用于在集成电路的互连结构中形成靠近设置的通孔的多重图案化方法。示出了形成通孔的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和说明性实施例,相同的参考标号用于指定相同的元件。
图1至图13示出了根据一些实施例的通孔形成的中间阶段的截面图。图1至图13中示出的步骤也在图15中示出的工艺流程200中示意性地示出。在随后的讨论中,参照图15中的工艺步骤讨论了图1至图13中示出的工艺步骤。
图1示出了晶圆10的截面图,其中示出的部分是器件管芯的一部分。根据本发明的一些实施例,晶圆10是包括诸如晶体管和/或二极管的有源器件以及诸如电容器、电感器、电阻器等的可能的无源器件的器件晶圆。
根据本发明的一些实施例,晶圆10包括半导体衬底12和在半导体衬底12的顶面处形成的部件。半导体衬底12可以包括晶体硅,晶体锗,硅锗和/或诸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等的III-V族化合物半导体。半导体衬底12还可以是块状硅衬底或绝缘体上硅(SOI)衬底。在半导体衬底12中可以形成浅沟槽隔离(STI)区域(未示出)以隔离半导体衬底12中的有源区域。尽管未示出,可以形成贯通孔以延伸至半导体衬底12内,其中,使用贯通孔以电互连位于晶圆10的相对两侧上的部件。其中可以包括晶体管的有源器件14形成在衬底12的顶面处。
图1中还示出了介电层16,其在下文中可选地称为金属间介电(IMD)层16。根据本发明的一些实施例,IMD层16由介电常数(k值)低于约3.0、低于约2.5或甚至更低的低k介电材料形成。IMD层16可以是由Black Diamond(应用材料公司的注册商标)、含碳低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等形成的。根据本发明的一些实施例,IMD层16的形成包括沉积含致孔剂的介电材料以及然后实施固化工艺以驱除致孔剂,并且因此剩余的IMD层16是多孔的。
在IMD 16中形成导电部件22。根据一些实施例,导电部件22是包括扩散阻挡层18和位于扩散阻挡层18上方的含铜材料20的金属线。扩散阻挡层18可以包括钛、氮化钛、钽、氮化钽等,并且具有防止含铜材料20中的铜扩散到IMD 16内的功能。导电线22在下文中称为金属线22。导电部件22可具有单镶嵌结构、双镶嵌结构,且在一些实施例中可以是接触插塞。
在介电层16和导电线22上方形成介电层24。介电层24可用作蚀刻停止层(ESL),并且因此贯穿说明书称为ESL 24。ESL 24可包括氮化物、基于硅碳的材料、碳掺杂的氧化物和/或它们的组合。形成方法包括等离子体增强化学汽相沉积(PECVD)或诸如高密度等离子体CVD(HDPCVD)、原子层CVD(ALCVD)等的其它方法。在一些实施例中,介电层24还用作用于防止诸如铜的不期望的元素扩散至随后形成的低k介电层的扩散阻挡层。ESL 24可包括碳掺杂的氧化物(CDO)、结合有碳的氧化硅(SiOC)或鸟氨酸脱羧酶(ODC)。ESL 24还可以是由氮掺杂的碳化硅(NDC)。ESL 24可以是单层或可以包括一个以上的层。
在ESL 24上方形成介电层26。根据本发明的一些示例性实施例,介电层26是由低k介电材料形成的,并且在本文中称为低k介电层26。可以使用选自用于形成介电层16的相同的候选材料的材料形成低k介电层26。当从相同的候选材料选择时,介电层16和26的材料可以彼此相同或不同。
根据一些实施例,在低k介电层26上方形成层28、30和32。相应的步骤示出为图15中示出的工艺流程中的步骤202。在低k介电层26上方形成抗反射涂层(ARL)28。根据一些示例性实施例,ARL 28可以是由氧化物形成的无氮ARL(NFARL)。例如,NFARL可包括使用等离子体增强化学汽相沉积(PECVD)形成的氧化硅。
在ARL 28上方形成掩模层30。掩模层30在下文中还称为硬掩模层30。根据一些实施例,硬掩模层30包括可以是以金属氮化物形式的金属。硬掩模层30还可以由诸如氮化硅的非金属氮化物、诸如氮氧化硅的氮氧化物等形成。在硬掩模层30上方还可形成ARL 32。ARL 32还可以是可以由使用PECVD形成的诸如氧化硅的氧化物形成的NFARL。
图案化ARL 32和掩模层30以形成沟槽34。根据一些实施例,使用双重图案化双重蚀刻(2P2E)工艺形成沟槽34,其中,使用不同光刻工艺形成两个相邻的沟槽34,以使相邻的沟槽34可以接近彼此定位而不招致光学邻近效应。
参照图2,图案化的ARL 32和掩模层30用作蚀刻掩模以蚀刻ARL 28和低k介电层26。因此,沟槽34延伸至低k介电层26内。相应的步骤示出为图15中示出的工艺流程中的步骤204。当沟槽34的底面在低k介电层26的顶面和底面之间的中间水平处时,蚀刻完成。在蚀刻期间,可以消耗ARL 32(图1),留下掩模层30作为顶层。
参照图3,在掩模层30上方形成光刻胶36,且光刻胶具有填充至沟槽34内的一些部分(图2)。相应的步骤示出为图15中示出的工艺流程中的步骤206。光刻胶36具有平坦的顶面,以使光刻胶36上面的随后形成的层可以是平坦的层,并且可以非常薄(例如,具有几百埃的厚度)同时仍然是共形的。
接下来,形成又称为掩模层38的高蚀刻选择性层38。相应的步骤示出为图15中示出的工艺流程中的步骤208。高蚀刻选择性层38包括具有不同特征的至少两个层,且因此当使用适当蚀刻剂时具有高蚀刻选择性。根据本发明的一些实施例,层38包括层40、层40上方的层42以及层42上方的层44。例如,层38包括低温(LT)氧化物层40、LT氧化物层40上方的含金属和/或氮化物的层(诸如,TiN、AlN或Al2O3)42以及层42上方的LT氧化物层44。层42可以用作硬掩模,且在掩模层42的图案化中和/或低k介电层26的蚀刻中,LT氧化物层40可用作蚀刻停止层。
根据可选的实施例,层38包括层40和层42,但是不包括层44。根据又可选实施例,层38包括层42和层44,但是不包括层40。,当选择适当的蚀刻剂时,金属氮化物层42由于含有金属可具有相对于LT氧化物层40和44的较高的蚀刻选择性,以使蚀刻可导致层38中上面的层被图案化,同时层38中的下面的层用作蚀刻停止层。由于光刻胶36的存在,层40、42、和44在低温下形成以防止光刻胶36的破坏。层40、42和44的形成温度可以低于约200℃,且可以在约75℃和约170℃之间的范围内。形成在光刻胶36上的层40可使用原子层沉积(ALD)形成以通过等离子体最小化对光刻胶36的损坏,同时也可使用诸如化学汽相沉积(CVD)、物理汽相沉积(PVD)等的其它方法。可使用PVD形成层42(诸如TiN)。层40、42和44的厚度可以介于约和约的范围内。
层40、42、和44的材料可以选自各个组合。例如,下文列举了多个蚀刻剂组,其中,每组包括适合用于蚀刻一些可蚀刻材料的蚀刻剂,同时也列举了一些不可蚀刻的材料。因此,可蚀刻材料可用于形成层38中上面的层,且不可蚀刻材料可用于形成层38中正下面的层。例如,H3PO4或HNO3适合用于蚀刻金属(诸如铝)或SiN,且不适合用于蚀刻SiO2、Si、和光刻胶中的任意一种。NH4OH或H2O2适合用于蚀刻铝或聚合物,且不适合用于蚀刻SiO2、Si、和SiN中的任意一种。也可使用干蚀刻实施蚀刻。例如,可使用Cl2蚀刻金属,且可使用CxFy蚀刻介电材料,其中,工艺气体的流速可以被调节以提高蚀刻中的选择性。
图3至图8示出了用于形成通孔图案的二光刻二蚀刻工艺。图3至图5示出了用于形成第一通孔图案的第一光刻胶第一蚀刻工艺中的中间阶段。根据本发明的一些实施例,在层38上方形成三层,其中,三层包括底层(又名下层)46、底层46上方的中间层48以及中间层48上方的上层50。相应的步骤示出为图15中示出的工艺流程中的步骤210。根据一些实施例,底层46和上层50是由光刻胶形成的。中间层48可以是由无机材料形成的,无机材料可以是氮化物(诸如氮化硅)、氮氧化物(诸如氮氧化硅)、氧化物(诸如氧化硅)等。相对于上层50和底层46,中间层48具有较高的蚀刻选择性,并且因此,上层50可用作用于图案化中间层48的蚀刻掩模,并且中间层48可用作用于图案化底层46的蚀刻掩模。上层50被图案化以形成开口52,开口52具有将在低k介电层26中形成的通孔70A中的图案(图13)。
接下来,使用图案化的上层50作为蚀刻掩模蚀刻中间层48,以使上层50的图案被转印至中间层48。图4中示出生成的结构。在中间层48的图案化期间,上层50被至少部分地或完全地消耗。在蚀刻穿过中间层48之后,图案化底层46,其中,中间层48用作蚀刻掩模。如果在中间层48的图案化期间上层50尚未被完全地消耗,在底层46的图案化期间,上层50也将被完全地消耗。
然后,底层46和上面的中间层48用作蚀刻掩模以蚀刻下面的层44,其中,蚀刻工艺称为第一蚀刻工艺。相应的步骤示出为图15中示出的工艺流程中的步骤212。因此,开口52延伸至层44内,层42暴露于开口52。由于中间层48和层44均由无机材料形成,且相对于彼此可具有较低的蚀刻选择性,中间层48可以被消耗,且在层44的随后的蚀刻中,底层46用作蚀刻掩模。尽管以比中间层48和层44低的蚀刻速率,在层44的图案化期间,还可消耗底层46。因此,在完成层44的图案化的时候,底层46的厚度减小。
蚀刻之后,包括光刻胶的剩余底层46在灰化工艺中被去除,其中,氧气用于去除底层46。图5中示出生成的结构。如图4和图5所示,由于层40和层42提供保护,在灰化工艺中,低k介电层26和光刻胶36未被损坏。
图6至图8示出了层44的图案化中的第二光刻第二蚀刻工艺。根据本发明的一些实施例,如图6所示,在层44上方形成第二三层。相应的步骤示出为图15中示出的工艺流程中的步骤214。第二三层包括底层54、底层54上方的中间层56以及中间层56上方的上层58。根据一些实施例,底层54和上层58是由光刻胶形成的。中间层56可以是由无机材料形成的,无机材料可以是氮化物(诸如氮化硅)、氮氧化物(诸如氮氧化硅)、氧化物(诸如氧化硅)等。相对于上层58和底层54,中间层56具有较高的蚀刻选择性,并且因此,上层58可用作用于图案化中间层56的蚀刻掩模,并且中间层56可用作用于图案化底层54的蚀刻掩模。上层58被图案化以形成开口60,开口60还具有将在低k介电层26中形成的通孔70B(图13)的图案。
使用图案化的上层58作为蚀刻掩模蚀刻中间层56,以使上层58的图案被转印至中间层56。图7中示出生成的结构。在中间层56的图案化期间,上层58也可被消耗。在蚀刻穿过中间层56之后,图案化底层54,接下来蚀刻层44。因此,开口60延伸至层44内,层42暴露于开口60。相应的步骤示出为图15中示出的工艺流程中的步骤216。蚀刻之后,包括光刻胶的剩余底层54(图7)在灰化工艺中被去除,其中,氧气用于去除底层54。图8中示出生成的结构。如图7和图8所示,由于层40和层42提供保护,在灰化工艺中,低k介电层26和光刻胶36未被损坏。
图9和图10示出了至低k介电层26内的通孔图案的转印。相应的步骤示出为图15中示出的工艺流程中的步骤218。参照图9,使用层42(图8)用作蚀刻掩模以蚀刻下面的层40。如图9所示,根据本发明的一些实施例,在蚀刻之后去除硬掩模层42,留下图案化的层40。根据可选的实施例,在层40的图案化之后,留下硬掩模层42(图8)未被去除,如通过图9中虚线示出。
在随后的步骤中,如图10所示,蚀刻光刻胶36,其中,层40(或层42,如果层42未去除)用作蚀刻掩模。光刻胶36的蚀刻停止在低k介电层26的顶面上。然后,光刻胶36用作蚀刻掩模以蚀刻低k介电层26,以使在低k介电层26的下部中形成通孔开口64和66。执行蚀刻直至暴露出ESL 24。当ESL 24包括一个以上的层,ESL 24的顶层也可被蚀刻穿过且蚀刻停止在ESL 24的底层上。
在通孔开口64和66的形成之后,通过使用氧气(O2)作为工艺气体,在灰化工艺中去除剩余的光刻胶36。然后蚀刻掩模层30,产生图11中的结构。
根据一些实施例,如图3至图8所示,在第一光刻胶第一蚀刻中和第二光刻胶第二蚀刻中形成的图案保存在光刻胶36上方的层(层44,图8)中,而不是直接地形成在低k介电层26中。因此,在低k介电层26中的通孔开口64和66的形成仅涉及光刻胶36的单一灰化工艺。这不同于常规的2P2E工艺,常规的2P2E工艺中每个2P2E工艺中的通孔开口的形成涉及直接蚀刻至低k介电层26内并且因此需要形成光刻胶以用于每个2P2E工艺。结果,常规的2P2E工艺需要两个光刻胶的灰化,且将低k介电层26暴露于两次灰化工艺。根据本发明的实施例,由于灰化工艺造成低k介电层26的损坏,通过单一灰化工艺,低k介电层26的损坏可以被最小化。
参照图12,蚀刻穿过蚀刻停止层24,露出下面的导电线22。图13分别示出了在通孔开口64和66(图12)中的导电通孔70(包括70A和70B)的形成。导电线68(包括68A和68B)还形成在沟槽34中(图12)。相应的步骤示出为图15中示出的工艺流程中的步骤220。通孔70和导电线68可以包括诸如扩散阻挡层、粘合层等的衬垫72。衬垫72可以由钛、氮化钛、钽、氮化钽或其他替代物形成。导电线68的内部材料74包括诸如铜、铜合金、银、金、钨、铝等的导电材料。在根据一些实施例,通孔70和导电线68的形成包括实施毯式沉积以形成衬垫72,沉积铜或铜合金的薄晶种层,以及例如通过电镀、化学镀、沉积等用金属74填充剩余的通孔开口64/66和沟槽34。可执行诸如化学机械平坦化(CMP)的平坦化以使导电线68的表面平坦,且从介电层26的顶面去除多余的导电材料。在随后的步骤中,形成介电ESL层76,且可形成更多的低k介电层和金属线和通孔(未示出)。
根据一些实施例,如所论述的工艺步骤可用于三光刻三蚀刻工艺。在这些实施例中,可以执行第三光刻第三蚀刻以在层44中形成第三通孔的图案,其中,第三图案同时向下转印至低k介电层26作为开口52和60(图8)。第三光刻第三蚀刻可以插入在图8中示出的步骤和图9中示出的步骤之间。第三光刻第三蚀刻的工艺步骤类似于图6至图8中示出的步骤,并且因此在此不再赘述。
图1至图13中示出的工艺步骤示出了两个通孔的形成,每个通孔连接至其自身上面的金属线。相同的工艺步骤还可用于形成向下面的通孔且连接至上面相同的金属线。同时执行工艺步骤,且共享图1至图13中示出的工艺步骤,没有添加额外的工艺步骤。例如,图14示出了使用2P2E工艺形成的包括通孔174和274的结构。通孔174和274在下面且连接至上面的相同的导电线168。此外,通过如图13中限定通孔70A的图案的相同的工艺步骤3至步骤5同时限定通孔174的图案,以及通过如图13中限定通孔70B的图案的相同工艺步骤6至步骤8同时限定通孔274的图案。
本发明的实施例具有一些有利的特征。根据本发明的一些实施例,掩模层用于保存2P2E(或3P3E)工艺中形成的图案。然后,图案被同时转印至低k介电层内。因此,无论使用了多少次光刻和蚀刻步骤,通孔和金属线的形成仅涉及其灰化可能造成低k介电层的损坏的单一光刻胶层。2P2E工艺中的光刻胶的灰化不导致低k介电层的损坏,因为低k介电层受到上面的光刻胶和掩模层的保护。此外,通过2P2E工艺,通孔连接上面的金属线的拐角具有尖锐轮廓,而不是不利的圆形。
根据本发明的一些实施例,一种方法包括形成介电层,在介电层上方形成光刻胶,在光刻胶上方形成第一掩模层,以及在第一掩模层上方形成第二掩模层。执行第一光刻第一蚀刻以在第二掩模层中形成第一通孔图案,其中,第一光刻第一蚀刻停止在第一掩模层的顶面上。执行第二光刻第二蚀刻以在第二掩模层中形成第二通孔图案,其中,第二光刻第二蚀刻停止在第一掩模层的顶面上。使用第二掩模层作为蚀刻掩模以蚀刻第一掩模层。蚀刻光刻胶和介电层以同时将第一通孔图案和第二通孔图案转印至介电层中。
根据本发明的一些实施例,一种方法包括在衬底上方形成低k介电层,蚀刻低k介电层以形成沟槽,在低k介电层上方形成第一掩模层,以及在第一掩模层上方形成第二掩模层。方法还包括,在第一图案化步骤中,在第二掩模层中形成第一通孔图案,以及在第二图案化步骤中,在第二掩模层中形成第二通孔图案。使用第二掩模层作为蚀刻掩模以蚀刻第一掩模层以同时将第一通孔图案和第二通孔图案转印至第一掩模层内。使用第一掩模层作为蚀刻掩模以蚀刻低k介电层以在低k介电层中形成第一通孔开口和第二通孔开口。
根据本发明的一些实施例,一种方法包括:在半导体衬底上方形成低k介电层,蚀刻低k介电层以形成第一沟槽和第二沟槽,施加具有填充第一沟槽的第一部分和填充第二沟槽的第二部分的光刻胶,形成第一掩模层覆盖光刻胶,以及在第一掩模层上面形成第二掩模层。第一掩模层是平坦的毯式层。使用分开的工艺步骤在第二掩模层中形成第一通孔开口和第二通孔开口。当形成第一通孔开口和第二通孔开口时,光刻胶完全由第一掩模层覆盖。蚀刻第一掩模层以将第一通孔开口和第二通孔开口延伸至第一掩模层中。第一通孔开口和第二通孔开口分别地延伸至光刻胶的第一部分和第二部分中。使用光刻胶作为蚀刻掩模以蚀刻低k介电层以在低k介电层中分别地形成第一通孔开口和第二通孔开口。
根据本发明的一个实施例,提供了一种使用多重光刻多重蚀刻的通孔图案化的方法,包括:形成介电层;在所述介电层上方形成光刻胶;在所述光刻胶上方形成第一掩模层;在所述第一掩模层上方形成第二掩模层;执行第一光刻第一蚀刻以在所述第二掩模层中形成第一通孔图案,其中,所述第一光刻第一蚀刻停止在所述第一掩模层的顶面上;执行第二光刻第二蚀刻以在所述第二掩模层中形成第二通孔图案,其中,所述第二光刻第二蚀刻停止在所述第一掩模层的所述顶面上;使用所述第二掩模层作为蚀刻掩模蚀刻所述第一掩模层;以及蚀刻所述光刻胶和所述介电层以同时将所述第一通孔图案和所述第二通孔图案转印至所述介电层内。
在上述方法中,使用蚀刻的所述光刻胶作为蚀刻掩模以蚀刻所述介电层。
在上述方法中,还包括在所述介电层中形成沟槽,其中,所述光刻胶填充所述沟槽,并且所述第一通孔图案被转印为位于所述沟槽下面的且连接至所述沟槽的通孔开口。
在上述方法中,还包括用导电材料填充所述沟槽和所述通孔开口以分别形成导电线和通孔。
在上述方法中,还包括:在所述第一掩模层下面形成第三掩模层,其中,蚀刻所述第一掩模层停止在所述第三掩模层的顶面上;以及使用所述第一掩模层作为蚀刻掩模蚀刻所述第三掩模层。
在上述方法中,使用三层来执行所述第一光刻第一蚀刻和所述第二光刻第二蚀刻的每个。
在上述方法中,所述光刻胶具有平坦的顶面,以及所述第一掩模层和所述第二掩模层是平坦的层。
根据本发明的另一实施例,还提供了一种使用多重光刻多重蚀刻的通孔图案化的方法,包括:在衬底上方形成低k介电层;蚀刻所述低k介电层以形成沟槽;在所述低k介电层上方形成第一掩模层;在所述第一掩模层上方形成第二掩模层;在第一图案化步骤中,在所述第二掩模层中形成第一通孔图案;在第二图案化步骤中,在所述第二掩模层中形成第二通孔图案;使用第二掩模层作为蚀刻掩模蚀刻所述第一掩模层以同时将所述第一通孔图案和所述第二通孔图案转印至所述第一掩模层内;以及使用所述第一掩模层作为蚀刻掩模蚀刻所述低k介电层以在所述低k介电层中形成第一通孔开口和第二通孔开口。
在上述方法中,还包括在所述低k介电层上方形成光刻胶,其中,所述光刻胶填充所述沟槽,并且所述第一掩模层在所述光刻胶上面。
在上述方法中,所述沟槽具有位于所述低k介电层的顶面和底面之间的中间水平处的底部。
在上述方法中,所述第一掩模层包括金属,以及所述第二掩模层包括氧化硅。
在上述方法中,还包括位于所述第一掩模层下面的额外的氧化硅层。
在上述方法中,使用包括两个光刻胶的三层执行所述第一图案化步骤和所述第二图案化步骤的每个。
在上述方法中,还包括填充所述沟槽、所述第一通孔开口以及所述第二通孔开口以分别形成导电线、第一通孔以及第二通孔。
在上述方法中,在形成所述沟槽和形成所述导电线之间的整个周期期间,存在单一光刻胶灰化步骤,当暴露所述低k介电层的部分时执行所述单一光刻胶灰化步骤,以及当暴露所述低k介电层时不执行额外的光刻胶灰化步骤。
根据本发明的又一实施例,还提供了一种使用多重光刻多重蚀刻的通孔图案化的方法,包括:在半导体衬底上方形成低k介电层;蚀刻所述低k介电层以形成第一沟槽和第二沟槽;施加具有填充所述第一沟槽的第一部分和填充所述第二沟槽的第二部分的光刻胶;形成覆盖所述光刻胶的第一掩模层,其中,所述第一掩模层是平坦的毯式层;在所述第一掩模层上面形成第二掩模层;使用分开的工艺步骤在所述第二掩模层中形成第一通孔开口和第二通孔开口,其中,当形成所述第一通孔开口和所述第二通孔开口时,所述光刻胶被所述第一掩模层完全地覆盖;蚀刻所述第一掩模层以将所述第一通孔开口和所述第二通孔开口延伸至所述第一掩模层内;所述第一通孔开口和所述第二通孔开口分别地延伸至所述光刻胶的所述第一部分和所述第二部分内;以及使用所述光刻胶作为蚀刻掩模蚀刻所述低k介电层以在所述低k介电层中分别形成第一通孔开口和第二通孔开口。
在上述方法中,还包括同时去除所述光刻胶的所述第一部分和所述第二部分。
在上述方法中,还包括:填充所述第一沟槽和所述第二沟槽以分别地形成第一金属线和第二金属线。
在上述方法中,还包括:填充所述第一通孔开口和所述第二通孔开口以分别地形成第一通孔和第二通孔。
在上述方法中,还包括:在所述第一掩模层下面形成第三掩模层;以及蚀刻所述第三掩模层以将所述第一通孔开口和所述第二通孔开口延伸至所述第三掩模层内,其中,使用所述第三掩模层作为蚀刻掩模将所述第一通孔开口和所述第二通孔开口延伸至所述光刻胶内。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种使用多重光刻多重蚀刻的通孔图案化的方法,包括:
形成介电层;
在所述介电层上方形成光刻胶;
在所述光刻胶上方形成第一掩模层;
在所述第一掩模层上方形成第二掩模层;
执行第一光刻第一蚀刻以在所述第二掩模层中形成第一通孔图案,其中,所述第一光刻第一蚀刻停止在所述第一掩模层的顶面上;
执行第二光刻第二蚀刻以在所述第二掩模层中形成第二通孔图案,其中,所述第二光刻第二蚀刻停止在所述第一掩模层的所述顶面上;
使用所述第二掩模层作为蚀刻掩模蚀刻所述第一掩模层;以及
蚀刻所述光刻胶和所述介电层以同时将所述第一通孔图案和所述第二通孔图案转印至所述介电层内。
2.根据权利要求1所述的方法,其中,使用蚀刻的所述光刻胶作为蚀刻掩模以蚀刻所述介电层。
3.根据权利要求1所述的方法,还包括在所述介电层中形成沟槽,其中,所述光刻胶填充所述沟槽,并且所述第一通孔图案被转印为位于所述沟槽下面的且连接至所述沟槽的通孔开口。
4.根据权利要求3所述的方法,还包括用导电材料填充所述沟槽和所述通孔开口以分别形成导电线和通孔。
5.根据权利要求1~4任一项所述的方法,还包括:
在所述第一掩模层下面形成第三掩模层,其中,蚀刻所述第一掩模层停止在所述第三掩模层的顶面上;以及
使用所述第一掩模层作为蚀刻掩模蚀刻所述第三掩模层。
6.根据权利要求1~4任一项所述的方法,其中,使用三层来执行所述第一光刻第一蚀刻和所述第二光刻第二蚀刻的每个。
7.根据权利要求1~4任一项所述的方法,其中,所述光刻胶具有平坦的顶面,以及所述第一掩模层和所述第二掩模层是平坦的层。
8.一种使用多重光刻多重蚀刻的通孔图案化的方法,包括:
在衬底上方形成低k介电层;
蚀刻所述低k介电层以形成沟槽;
在所述低k介电层上方形成第一掩模层;
在所述第一掩模层上方形成第二掩模层;
在第一图案化步骤中,在所述第二掩模层中形成第一通孔图案;
在第二图案化步骤中,在所述第二掩模层中形成第二通孔图案;
使用第二掩模层作为蚀刻掩模蚀刻所述第一掩模层以同时将所述第一通孔图案和所述第二通孔图案转印至所述第一掩模层内;以及
使用所述第一掩模层作为蚀刻掩模蚀刻所述低k介电层以在所述低k介电层中形成第一通孔开口和第二通孔开口。
9.根据权利要求8所述的方法,还包括在所述低k介电层上方形成光刻胶,其中,所述光刻胶填充所述沟槽,并且所述第一掩模层在所述光刻胶上面。
10.一种使用多重光刻多重蚀刻的通孔图案化的方法,包括:
在半导体衬底上方形成低k介电层;
蚀刻所述低k介电层以形成第一沟槽和第二沟槽;
施加具有填充所述第一沟槽的第一部分和填充所述第二沟槽的第二部分的光刻胶;
形成覆盖所述光刻胶的第一掩模层,其中,所述第一掩模层是平坦的毯式层;
在所述第一掩模层上面形成第二掩模层;
使用分开的工艺步骤在所述第二掩模层中形成第一通孔开口和第二通孔开口,其中,当形成所述第一通孔开口和所述第二通孔开口时,所述光刻胶被所述第一掩模层完全地覆盖;
蚀刻所述第一掩模层以将所述第一通孔开口和所述第二通孔开口延伸至所述第一掩模层内;
所述第一通孔开口和所述第二通孔开口分别地延伸至所述光刻胶的所述第一部分和所述第二部分内;以及
使用所述光刻胶作为蚀刻掩模蚀刻所述低k介电层以在所述低k介电层中分别形成第一通孔开口和第二通孔开口。
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CN104124203A (zh) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | 互连结构的形成方法 |
CN104216233A (zh) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | 曝光方法 |
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CN107799401A (zh) * | 2017-10-20 | 2018-03-13 | 上海华力微电子有限公司 | 一种增加高深宽比层次光刻工艺窗口的方法 |
CN110718451A (zh) * | 2018-07-12 | 2020-01-21 | 台湾积体电路制造股份有限公司 | 半导体结构的制造方法 |
CN110718451B (zh) * | 2018-07-12 | 2022-10-28 | 台湾积体电路制造股份有限公司 | 半导体结构的制造方法 |
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US20170365508A1 (en) | 2017-12-21 |
TWI603382B (zh) | 2017-10-21 |
KR20170083943A (ko) | 2017-07-19 |
US10510584B2 (en) | 2019-12-17 |
DE102016100766B4 (de) | 2019-02-07 |
US20190096752A1 (en) | 2019-03-28 |
US20190326164A1 (en) | 2019-10-24 |
US10141220B2 (en) | 2018-11-27 |
US20170200636A1 (en) | 2017-07-13 |
CN107017154B (zh) | 2019-11-01 |
TW201737312A (zh) | 2017-10-16 |
KR101910238B1 (ko) | 2018-10-19 |
US9412648B1 (en) | 2016-08-09 |
US9754818B2 (en) | 2017-09-05 |
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US10340178B2 (en) | 2019-07-02 |
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