CN106711045A - 切割金属栅极的方法 - Google Patents

切割金属栅极的方法 Download PDF

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Publication number
CN106711045A
CN106711045A CN201610993412.9A CN201610993412A CN106711045A CN 106711045 A CN106711045 A CN 106711045A CN 201610993412 A CN201610993412 A CN 201610993412A CN 106711045 A CN106711045 A CN 106711045A
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China
Prior art keywords
metal
hard mask
metal gate
fin
gate
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张博钦
王志豪
杨凱傑
洪士庭
吴伟豪
吴琬瑶
傅依婷
苏嘉伟
萧怡瑄
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种切割金属栅极的方法，此方法包括在基板上形成第一鳍与第二鳍。此第一鳍具有第一栅极区域且此第二鳍具有第二栅极区域。此方法亦包括在此第一及第二栅极区域上形成金属栅极接线。此金属栅极接线从第一鳍延伸至第二鳍。此方法亦包括施加线切割以将金属栅极接线分为第一子金属栅极接线及第二子金属栅极接线，并且在线切割中形成隔离区域。

Description

切割金属栅极的方法
技术领域
本揭露是关于一种切割金属栅极的方法。
背景技术
集成电路材料与设计的先进技术已产生数代集成电路，其中与前代相比各代具有更小且更复杂的电路。在集成电路发展过程中，功能密度(即，每晶片面积互连元件的数量)通常已增加而几何尺寸(即，使用制造制程可产生的最小组件(或接线))已减小。此按比例缩小制程一般通过增加生产效率并降低相关成本来提供优势。此按比例缩小亦增加集成电路处理与制造的复杂性，且对于这些进步而言，需要更多集成电路处理与制造的发展。
在一些集成电路设计中，一种作为技术节点(node)缩小实施的进展已经使用金属栅电极取代通常聚硅栅电极以改良具有减小特征尺寸的元件效能。尽管一般而言现存制造集成电路元件的方法针对预期目的已足够，但是在各方面并未完全满意。例如，将金属电极接线切割为子金属电极接线时会出现困难。
发明内容
本揭露的一实施例为一种用于制造半导体元件的方法包括在基板上形成第一鳍及第二鳍。第一鳍具有第一栅极区域而第二鳍具有第二栅极区域。此方法亦包括在第一及第二栅极区域上形成金属栅极线。此金属栅极线从第一鳍延伸至第二鳍。此方法亦包括施加线切割以将金属栅极线分为第一子金属栅极线与第二子金属栅极线，并且在线切割中形成隔离区域。
附图说明
当结合随附附图阅读时，自以下详细描述将最佳地理解本揭露的态样。应注意，根据工业中的标准实务，各特征并非按比例绘制。事实上，出于论述清晰的目的，可任意增加或减小各所示特征的尺寸。
图1为本揭露的部分实施例的制造半导体元件的方法的流程图；
图2A为本揭露的部分实施例的半导体元件的工件的透视图；
图2B为图2A中沿线A-A的半导体元件的工件的截面图；
图2C为图2A中沿线B-B的半导体元件的工件的截面图；
图3A、4A、5A、6A、6C及7A为依照一些实施例，在图2A中沿线A-A的半导体元件的截面图；
图3B、4B、5B、6B、6D及7B是依照一些实施例，在图2A中沿线B-B的半导体元件的截面图；
图8为本揭露的部分实施例的制造半导体元件的另一方法的流程图；
图9A、10A、11A、12A、13A、13C及14A是依照一些实施例，在图2A中沿线A-A的示例性半导体元件的截面图；
图9B、10B、11B、12B、13B、13D及14B是依照一些实施例，在图2A中沿线B-B的半导体元件的截面图；
图15为本揭露的部分实施例的制造的半导体元件的另一方法的流程图；
图16A、17A、18A、19A、20A、20C、21A、22A、23A、24A、24C及25A是依照一些实施例的在图2A中沿线A-A的半导体元件的截面图；
图16B、17B、18B、19B、20B、20D、21B、22B、23B、24B、24D及25B是依照一些实施例，在图2A中沿线B-B的半导体元件的截面图。
具体实施方式
以下揭示内容提供许多不同实施例或实例，以便实施本揭露的不同特征。下文描述元件及排列的特定实例以简化本揭露。当然，这些实例仅为实例且并不意欲为限制性。举例而言，以下描述中在第二特征上方或第二特征上形成第一特征可包括以直接接触形成第一特征及第二特征的实施例，且亦可包括可在第一特征与第二特征之间形成额外特征以使得第一特征及第二特征可不处于直接接触的实施例。另外，本揭露可在各实例中重复元件符号及/或字母。此重复是出于简明性及清晰的目的，且本身并不指示所论述的各实施例及/或配置之间的关系。
进一步地，为了便于描述，本文可使用空间相对性术语，诸如“在……之下”、“在……下方”、“下部”、“在……上方”、“上部”及类似术语，来描述诸图中所示的一个元件或特征与另一元件(或多个元件)或特征(或多个特征)的关系。除了诸图所描绘的定向外，空间相对性术语意欲包含在使用或操作中的装置的不同定向。装置可经其他方式定向(旋转90度或处于其他定向)且因此可同样相应解读本文所使用的空间相对性描述词。
本案是关于，但并非以其他方式受限于，鳍式场效晶体管(FinFET)元件。此元件可包括P-型金属氧化物半导体鳍式场效晶体管元件或N-型金属氧化物半导体鳍式场效晶体管元件。鳍式场效晶体管元件可为双栅极元件、三栅极元件、块状元件、绝缘体上硅(silicon on insulator；SOI)元件、及/或其他构造。一般技术者可了解可受益于本案态样的半导体元件其他实施例。例如，如本文描述的一些实施例亦可应用于环绕式栅极(GAA)元件、Ω-栅极元件、或Pi-栅极(II-栅极)元件。以下揭示内容将以鳍式场效晶体管实例继续来阐明本揭露的各实施例。然而，应了解此应用不应受限于特定类型的元件。
图1为本揭露的部分实施例的制造一或多个半导体元件的方法100的流程图。下文以在图2A至图7B中所示的半导体元件200来详细论述方法100。
参看图1、2A、2B、及2C，方法100通过接收半导体元件200的工件205起始于步骤102。工件205包括基板210。基板210可为块状硅基板。或者，基板210可包含元素半导体，诸如结晶结构的硅(Si)或锗(Ge)；化合物半导体，诸如锗化硅(SiGe)、碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)、及/或锑化铟(InSb)；或其组合。可能的基板210亦包括绝缘体上硅(SOI)基板。使用氧离子植入硅晶隔离法(separation byimplantation of oxygen；SIMOX)、晶圆接合、及/或其他适宜方法来制造绝缘体上硅基板。
一些示例性基板210亦包括绝缘体层。此绝缘体层包含任何适宜材料，包括氧化硅、蓝宝石、及/或其组合。示例性绝缘体层可为内埋式氧化物层(BOX)。通过任何适宜制程，诸如注入(例如，氧离子植入硅晶隔离法)、氧化、沉积、及/或其他适宜制程来形成此绝缘体。在一些示例性半导体元件200中，绝缘体层是绝缘体上硅基板的组件(例如，一层)。
基板210亦可包括各掺杂区域。掺杂区域可掺杂有P-型掺杂剂，诸如硼或二氟化硼(BF2)；N-型掺杂剂，诸如磷或砷；或其组合。可直接在基板210上、在P-阱结构中、在N-阱结构中、在双-阱结构中、及/或使用凸起结构来形成掺杂区域。基板210可进一步包括各种有效区域，诸如针对N-型金属氧化物半导体晶体管元件配置的区域及针对P-型金属氧化物半导体晶体管元件配置的区域。
基板210亦包括各种隔离特征220。隔离特征220分离基板210的各元件区域。隔离特征220包括通过使用不同处理技术形成的不同结构。例如，隔离特征220可包括浅沟槽隔离(STI)特征。形成浅沟槽隔离可包括在基板210中蚀刻沟槽并使用绝缘体材料(诸如氧化硅、氮化硅、或氮氧化硅)填充此沟槽。经填充的沟槽可具有多层结构，诸如热氧化衬层，其中氮化硅填充此沟槽。可进行化学机械研磨(chemical mechanical polishing；CMP)来回磨平过量绝缘体材料并使隔离特征220的顶面平坦。
工件205亦包括在基板210上形成的多个鳍特征230。鳍特征230可包括硅(Si)、硅锗(SiGe)、锡锗硅(SiGeSn)、砷化镓(GaAs)、砷化铟(InAs)、磷化铟(InP)、或其他适宜材料。在一些实施例中，通过包括各沉积、光微影、及/或蚀刻制程的任何适宜制程来形成鳍特征230。例如，通过图案化及蚀刻部分基板210来形成鳍特征230。
工件205亦包括在基板210上的栅极区域242中的多个虚设栅极堆叠240，并包覆部分的鳍特征230。在本实施例中，虚设栅极堆叠240后续将由高介电常数/金属栅极取代。虚设栅极堆叠240可包括介电层、聚硅层。可通过任何适宜制程或制程等，诸如沉积、图案化及蚀刻，来制造虚设栅极堆叠240。
沿虚设栅极堆叠240的侧壁形成侧壁间隔245。侧壁间隔245可包括介电材料，诸如氧化硅。或者，侧壁间隔245可包括氮化硅、碳化硅、氮氧化硅、或其组合。在实施例中，侧壁间隔245具有多个层。如在此项技术中已知，可通过沉积栅极侧壁间隔层并随后各向异性干蚀刻此栅极侧壁间隔层来形成侧壁间隔245。
除虚设栅极堆叠240(具有侧壁间隔245)之外，工件205亦包括在基板210上的源极/漏极区域252中的源极/漏极特征250。在一些实施例中，源极/漏极特征250为源极特征，且另一源极/漏极特征250为漏极特征。源极/漏极特征250由虚设栅极堆叠240分离。在一实施例中，对虚设栅极堆叠240以外的部分鳍特征230进行开槽以形成源极/漏极沟槽并随后通过包括化学气相沉积(chemical vapor deposition；CVD)沉积技术(例如，汽相磊晶(vapor-phase epitaxy；VPE)及/或超高真空化学气相沉积(UHV-CVD))、分子束磊晶法、及/或其他适宜制程的磊晶生长制程在此源极/漏极沟槽上形成源极/漏极特征250。源极/漏极特征250可包括锗(Ge)、硅(Si)、砷化镓(GaAs)、砷化镓铝(AlGaAs)、硅锗(SiGe)、磷化砷镓(GaAsP)、锑化镓(GaSb)、锑化铟(InSb)、砷化镓铟(InGaAs)、砷化铟(InAs)、或其他适宜材料。继由源极/漏极特征250填充源极/漏极沟槽之后，源极/漏极特征250顶层的进一步磊晶生长，往水平方向延伸并可开始形成侧面，诸如菱形侧面。在磊晶制程期间可原位掺杂源极/漏极特征250。在一些实施例中，未原位掺杂源极/漏极特征，进行注入制程(即，接合注入制程)来掺杂源极/漏极特征250。可进行一或多个退火制程来活化掺杂剂。退火制程包括快速热退火(rapid thermal annealing；RTA)及/或激光退火制程。
工件205亦包括在基板210上沉积的层间介电(interlayer dielectric；ILD)层260，包括形成在各虚设栅极堆叠240之间/之上及在源极/漏极特征250上。可通过化学气相沉积、原子层沉积(atomic layer deposition；ALD)、旋涂式涂覆法、或其他适宜技术沉积层间介电层260。层间介电层260可包括氧化硅、氮化硅、氮氧化物、具有低于热氧化硅的介电场数(k)的介电材料(由此称为低介电常数介电材料层)，及/或其他适宜介电材料层。层间介电层260可包括单一层或多个层。可进行化学机械研磨来回磨平层间介电层260以曝露虚设栅极堆叠240的顶面。
应注意，图2B是沿图2A中的线A-A的工件205的截面图，此工件位于两个源极/漏极特征250间。图2C是沿垂直于线A-A的线B-B的工件205的截面图并位于栅极区域242中。
参看图1、3A及3B，一旦接收工件205，方法100即通过移除虚设栅极堆叠240以形成栅极沟槽310进行至步骤104。在一些实施例中，此蚀刻制程可包括选择性湿式蚀刻及/或选择性干式蚀刻，这些蚀刻对于鳍特征230、侧壁间隔245及层间介电层260具有足够的蚀刻选择性。在一实施例中，选择性湿式蚀刻溶液包括氢氧化四甲铵(TMAH)、氢氟酸(HF)/硝酸(HNO3)/乙酸(CH3COOH)溶液、或其他适宜溶液。各蚀刻制程可经各蚀刻参数调整，这些蚀刻参数诸如使用的蚀刻剂、蚀刻温度、蚀刻溶液浓度、蚀刻压力、电源、射频偏压、射频偏压功率、蚀刻剂流速、及/或其他适宜参数。例如，湿式蚀刻溶液可包括氨水(NH4OH)、氢氧化钾(KOH)、氢氟酸(HF)、氢氧化四甲铵(TMAH)、其他适宜湿式蚀刻溶液、或其组合。在另一实例中，干式蚀刻制程包括使用氯基化学试剂的偏压等离子蚀刻制程。其他干式蚀刻剂气体包括四氟化碳(CF4)、三氟化氮(NF3)、六氟化硫(SF6)，及氦(He)。亦可使用如深反应性离子蚀刻(deep reactive-ion etching；DRIE)的此机制各向异性地进行干蚀刻。或者，可通过包括光微影、图案化及回蚀刻的一系列制程来移除虚设栅极堆叠240。
参看图1、4A及4B，方法100进行至步骤106，通过在元件200的栅极沟槽310中形成栅极堆叠410，且覆盖鳍特征230的上部分。可进行化学机械研磨制程以从栅极金属层414移除过量金属层，以此提供栅极金属层414实质上平坦的顶面。由此，沿线B-B的方向，栅极堆叠410从一鳍特征230继续延伸至另一鳍特征230以形成栅极线410L。栅极堆叠410可为高介电常数/金属栅极堆叠，而其他组分是可能的。
在本实施例中，在栅极沟槽310中形成高介电常数/金属栅极堆叠410，包括包覆部分鳍特征230。在各实施例中，高介电常数/金属栅极堆叠410包括分界层、在分界层上形成的栅极介电层412及在栅极介电层412上形成的栅极金属层414。如本文中使用及描述，栅极介电层包括具有高介电常数的介电材料，例如，大于热氧化硅的介电常数(～3.9)的介电材料。栅极金属层414可包括金属、金属合金、及/或金属硅化物。此外，制造高介电常数/金属栅极堆叠410可包括沉积以形成各栅极材料、一或多个衬层、及一或多个化学机械研磨制程来移除过量栅极金属并由此使半导体元件200的顶面平坦化。
在一些实施例中，分界层可包括介电材料，诸如氧化硅(SiO2)、硅酸铪(HfSiO)、及/或氮氧化硅(SiON)。此分界层可通过化学氧化、热氧化、原子曾沉积、化学气相沉积、及/或其他适宜方法来形成。栅极介电层412可包括诸如氧化铪(HfO2)的高介电常数介电层。或者，栅极介电层412可包括其他高介电常数介电材料，诸如二氧化钛(TiO2)、氧化锆铪(HfZrO)、三氧化二钽(Ta2O3)、硅酸铪(HfSiO4)、二氧化锆(ZrO2)、硅酸锆(ZrSiO2)、氧化镧(LaO)、氧化铝(AlO)、氧化锆(ZrO)、氧化钛(TiO)、五氧化二钽(Ta2O5)、氧化钇(Y2O3)、钛酸锶(SrTiO3；STO)、钛酸钡(BaTiO3；BTO)、氧化钡锆(BaZrO)、氧化锆铪(HfZrO)、氧化铪镧(HfLaO)、氧化铪硅(HfSiO)、氧化镧硅(LaSiO)、氧化硅铝(AlSiO)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、钛酸锶钡((Ba,Sr)TiO3；BST)、氧化铝(Al2O3)、氮化硅(Si3N4)、氮氧化物(SiON)、其组合、或其他适宜材料。高介电常数栅极介电层412可通过原子层沉积、物理气相沉积、化学气相沉积、氧化、及/或其他适宜方法来形成。
栅极金属层414可包括单一层或者多层结构，诸如具有经选择功函数以增强元件效能的金属层(功函数金属层)、衬层、润湿层、粘合层、金属合金或金属硅化物的各种组合。举例而言，栅极金属层414可包括钛(Ti)、金(Ag)、铝(Al)、氮化钛铝(TiAlN)、碳化钽(TaC)、氮碳化钽(TaCN)、氮硅化钽(TaSiN)、氮化钛(TiN)、氮化钽(TaN)、锰(Mn)、锆(Zr)、钌(Ru)、钼(Mo)、铝(Al)、氮化钨(WN)、铜(Cu)、钨(W)、铼(Re)、铱(Ir)、钴(Co)、镍(Ni)、其他适宜金属材料或其组合。在各实施例中，栅极金属层414可由原子层沉积、物理气相沉积、化学气相沉积、电子束蒸镀、或其他适宜制程形成。此外，可分别针对可使用不同金属层的N-场效晶体管及P-场效晶体管形成栅极金属层414。在各实施例中，可进行化学机械研磨制程以从栅极金属层414移除过量金属，以此提供栅极金属层414的大体上平坦顶面。
参看图1、5A、及5B，在形成高介电常数/金属栅极堆叠410之后，方法100通过在栅极金属层414上形成经图案化的硬遮罩510而进行至步骤108。经图案化的硬遮罩510具有界定待后续形成的线切割的开口515。在开口515内曝露部分高介电常数/金属栅极线410L(高介电常数/金属栅极堆叠)。在一些实施例中，开口515具有沿线A-A的方向的较大宽度，以使得相邻侧壁间隔245及层间介电层260在开口515中曝露以获得优点，诸如放宽微影制程解析度限制，尤其是当元件200按比例缩小时，使得在两个相邻鳍特征230之间的空间变得越来越小。
在一些实施例中，经图案化的硬遮罩510可包括经图案化的光阻层并通过微影制程形成。示例性微影制程可包括形成光阻层、通过微影曝光制程曝光此光阻层、进行后曝光烘烤制程、及显像此光阻层以形成经图案化的光阻层。或者，可通过沉积硬遮罩层、在硬遮罩层上通过微影制程形成经图案化的光阻层，再通过经图案化光阻层蚀刻此硬遮罩材料层来形成经图案化的硬遮罩510。
参看图1、6A、及6B，方法100借由通过开口515移除经曝露的高介电常数/金属栅极堆叠410以形成线切割610来进行至步骤110。在本实施例中，线切割610延伸至隔离特征220并将高介电常数/金属栅极线410L分为两个子高介电常数/金属栅极线410LA及410LB。子高介电常数/金属栅极线410LA沿着线B-B方向通过具有宽度d的线切割610与子高介电常数/金属栅极线410LB分离。
蚀刻制程可包括湿式蚀刻、干式蚀刻、及/或其组合。例如，干式蚀刻制程可实施含氟气体(例如，四氟化碳(CF4)、六氟化硫(SF6)、二氟甲烷(CH2F2)、三氟甲烷(CHF3)及/或六氟乙烷(C2F6))、含氯气体(例如，氯(Cl2)、三氯甲烷(CHCl3)、四氯化碳(CCl4)及/或三氯化硼(BCl3))、含溴气体(例如，溴酸(HBr)及/或三溴甲烷(CHBr3))、含碘气体、其他适宜气体及/或等离子、及/或上述气体的组合。在一些实施例中，执行选择蚀刻制程以选择性蚀刻高介电常数/金属栅极堆叠410，而实质上并不蚀刻侧壁间隔245及层间介电层260。如图所示，针对其中部分侧壁间隔245及层间介电层260曝露在开口515中(如在图5A及5B中所示)的情况，经曝露部分的侧壁间隔245及层间介电层260一起充当子蚀刻遮罩。因此，可放宽制程限制的自动对准性质形成线切割610。
在形成线切割610之后，如在图6C及6D中显示，通过蚀刻制程移除经图案化的硬遮罩510。在其中经图案化的硬遮罩510是光阻图案的一实例中，通过湿式剥离及/或等离子灰化移除经图案化的硬遮罩510。
参看图1、7A及7B，方法100通过使用介电层710填充线切割610以在两子高介电常数/金属栅极线410LA及410LB之间形成隔离区域715而进行至步骤112。可通过化学气相沉积、原子层沉积、旋涂式涂覆法、或其他适宜技术沉积介电层710。介电层710可包括氧化硅、氮化硅、氮氧化物、具有低于热氧化硅介电常数(k)的介电材料(由此称为低介电常数介电材料层)，及/或其他适宜介电材料层。可进行化学机械研磨来回磨平介电层710，以此提供高介电常数/金属栅极堆叠410与介电层710具有实质上平坦顶面。由此，将高介电常数/金属栅极线410L切割为子高介电常数/金属栅极线410LA及410LB，并且高介电常数/金属栅极线410L通过隔离区域715分离。
在方法100之前、期间、或之后可提供额外步骤，且可围绕方法100的额外实施例取代、消除、或移动所描述的一些步骤。其他替代或实施例可不脱离本案的精神及范围存在。
图8是包括制造半导体元件2000的半导体制造的方法1000。步骤1002、1003、1004、1005至步骤1006分别与上文在方法100的步骤102至106中论述的彼等内容相似。因此，上文关于步骤102至106的论述分别适用于步骤1002至1006。本案可在各实例中重复元件符号及/或字母。此重复是出于简明性及清晰的目的，以使得除非另作声明，否则重复的元件符号及/或字母指明在各实施例间的相似特征。
参看图8、9A、及9B，方法1000通过开槽高介电常数/金属栅极堆叠410以在栅极沟槽310中形成子沟槽1210来进行至步骤1008。后文将开槽后的高介电常数/金属栅极堆叠410称为高介电常数/金属栅极堆叠410’。蚀刻制程可包括湿式蚀刻、干式蚀刻、及/或其组合。例如，干式蚀刻制程可实施含氟气体(例如，四氟化碳(CF4)、六氟化硫(SF6)、二氟甲烷(CH2F2)、三氟甲烷(CHF3)及/或六氟乙烷(C2F6))、含氯气体(例如，氯(Cl2)、三氯甲烷(CHCl3)、四氯化碳(CCl4)及/或三氯化硼(BCl3))、含溴气体(例如，溴酸(HBr)及/或三溴甲烷(CHBr3))、含碘气体、其他适宜气体及/或等离子、及/或上述气体的组合。在一些实施例中，执行选择蚀刻制程以选择性蚀刻高介电常数/金属栅极堆叠410而实质上并不上蚀刻侧壁间隔245及层间介电层260。
参看图8、10A、及10B，方法1000通过在子沟槽1210中，包括在高介电常数/金属栅极线410L上的高介电常数/金属栅极堆叠410’上形成硬遮罩1220而进行至步骤1010。在一些实施例中，硬遮罩1220在随后源极/漏极接触蚀刻制程中，通过在移除层间介电层260期间保护高介电常数/金属栅极堆叠410’提供针对高介电常数/金属栅极堆叠410’的保护。硬遮罩1220可包括氮化硅、碳化硅、氮氧化硅、及/或其他适宜材料。在本实施例中，硬遮罩1220包括不同于侧壁间隔245及层间介电层260的材料以在随后蚀刻制程期间达成蚀刻选择性。在实施例中，硬遮罩1220包括氮化硅而侧壁间隔245及层间介电层260包括氧化硅。可通过化学气相、原子层沉积、及/或其他适当技术沉积硬遮罩1220。可进行化学机械研磨来回磨平硬遮罩1220及以此提供关于层间介电层260及侧壁间隔245的硬遮罩1220的大体上平坦顶面。
参看图8、11A、及11B，在高介电常数/金属栅极堆叠410’上形成硬遮罩1220之后，方法1000通过在硬遮罩1220上形成经图案化的硬遮罩1230而进行至步骤1012。经图案化的硬遮罩1230具有界定待后续形成的线切割的开口1235。开口1235对准高介电常数/金属栅极线410L的指定部分(例如，在两个鳍特征230之间)，此部分随后可移除。在一些实施例中，开口1235沿线A-A的方向具有较大宽度，以使得相邻侧壁间隔245及部分层间介电层260在开口1235中曝露以获得优点，诸如放宽微影制程解析限制，尤其是当元件2000按比例缩小时，两个相邻鳍特征230之间的空间变得越来越小。在众多方面中，经图案化的硬遮罩1230与上文结合图5A及5B论述的经图案化硬遮罩510的方法相似，包括其中论述的材料。
参看图8、12A、及12B，方法1000借由通过开口1235移除硬遮罩1220以曝露部分高介电常数/金属栅极堆叠410’来进行至步骤1014。此蚀刻制程可包括湿式蚀刻、干式蚀刻、及/或上述蚀刻的组合。在一些实施例中，执行选择此蚀刻制程以选择性蚀刻硬遮罩1220而实质上并不蚀刻侧壁间隔245及层间介电层260。如图所示，针对其中侧壁间隔245及部分层间介电层260在开口1235中曝露的情况(如在图11A中所示)，经曝露的侧壁间隔245与部分层间介电层260一起充当子蚀刻遮罩。因此，使用放宽制程限制的自动对准性质移除硬遮罩1220。
参看图8、13A、及13B，方法1000借由通过开口1235移除经曝露的高介电常数/金属栅极堆叠410’以形成线切割1240来进行至步骤1016。在本实施例中，线切割1240延伸至隔离特征220并将高介电常数/金属栅极线410L分为两子高介电常数/金属栅极线410LA及410LB。子高介电常数/金属栅极线410LA通过沿图2A的线B-B方向宽度d的线切割1240与子高介电常数/金属栅极线410LB分离开。此蚀刻制程是在众多方面与上文结合第6A及6B图论述的蚀刻制程相似。在形成线切割1240之后，如在图13C及13D中所示，通过蚀刻制程移除经图案化的硬遮罩1230。在其中经图案化的硬遮罩1230是光阻图案的一实例中，通过湿剥离及/或等离子灰化移除经图案化的硬遮罩1230。
参看图8、14A、及14B，方法1000通过使用介电层1250填充线切割1240以在两子高介电常数/金属栅极线410LA及410LB间形成隔离区域1255来进行至步骤1018。在众多方面中，形成介电层1250的方法与上文结合第7A及7B图论述的介电层710相似，包括其中论述的材料。可进行化学机械研磨以回磨平介电层1250并以此提供硬遮罩1220顶面的介电层1250实质上平坦顶面。由此，将高介电常数/金属栅极线410L切割为子高介电常数/金属栅极线410LA及410LB，并且高介电常数/金属栅极线410L通过隔离区域1255分离。
在方法1000之前、期间、或之后可提供额外步骤，且可围绕方法1000的额外实施例取代、消除、或移动所描述的一些步骤。其他替代或实施例可不脱离本案的精神及范围存在。
图15是包括制造半导体元件4000的半导体制造的方法3000。步骤3002、3003、3004、3005至步骤3006是分别与上文在方法100的步骤102至106中论述的彼等内容相似。步骤3008及步骤3010是分别与上文在方法1000的步骤1008及1010中论述的彼等内容相似。因此，上文有关步骤102至106的论述分别适用于步骤1002至1006。相似地，上文有关步骤1008及1010的论述分别适用于步骤3008及3010。本案可在各实施例中重复元件符号及/或字母。此重复是出于简明性及清晰的目的，以使得除非另作声明，否则重复的元件符号及/或字母指明在各实施例间的相似特征。
参看图15、16A及16B，在子沟槽1210中形成硬遮罩1220之后，方法3000通过开槽硬遮罩1220以形成第一沟槽3210而进行至步骤3012。经开槽的硬遮罩1220是称为硬遮罩1220’。开槽硬遮罩1220的蚀刻制程可包括湿式蚀刻、干式蚀刻、及/或上述蚀刻的组合。在一些实施例中，选择此蚀刻制程以选择性蚀刻第一硬遮罩1220而不大体上蚀刻侧壁间隔245及层间介电层260。因此，使用放宽制程限制的自动对准性质形成第一沟槽3210。
参看图15、17A及17B，方法3000通过开槽侧壁间隔245以更宽地扩展(或加大)第一沟槽3210，下述称为第二沟槽3210’而进行至步骤3014。此蚀刻制程可包括湿式蚀刻、干式蚀刻、及/或上述蚀刻的组合。在一些实施例中，选择此蚀刻制程以选择性蚀刻侧壁间隔245而不大体上蚀刻层间介电层260及硬遮罩1220。因此，使用放宽制程限制的自动对准性质形成经扩展的第二沟槽3210’。经开槽的侧壁间隔245称为侧壁间隔245’。在一些实施例中，控制蚀刻制程使得经开槽的侧壁间隔245’的顶面是大体上与硬遮罩1220’的顶面共面。
参看图15、18A及18B，方法3000通过在第二沟槽3210’中形成第二硬遮罩3230而进行至步骤3016。在一些实施例中，第二硬遮罩3230覆盖硬遮罩1220’并延伸以覆盖侧壁间隔245’以在随后蚀刻制程中增强对高介电常数/金属栅极堆叠410’的保护，诸如通过在随后源极/漏极接触蚀刻制程中移除层间介电层260期间保护经开槽的高介电常数/金属栅极堆叠410’，并改良对随后源极/漏极接触微影制程的容差。
在众多方面中，与上文结合图10A及10B论述的硬遮罩1220相似地形成第二硬遮罩3230，包括其中论述的材料。在本实施例中，第二硬遮罩3230包括不同于层间介电层260的材料以在随后蚀刻制程期间达成蚀刻选择性。或者，进行化学机械研磨来磨平过量第二硬遮罩3230。
参看图15、19A及19B，方法3000通过在第二硬遮罩3230上形成第一经图案化的硬遮罩3240而进行至步骤3018。第一经图案化的硬遮罩3240具有界定待后续形成的源极/漏极触点的开口3245。开口3245对准在指定源极/漏极特征250上的层间介电层260。在一些实施例中，开口3245具有沿线A-A方向的较大宽度，以使得相邻第二硬遮罩3230在开口3245中曝露以获得优点，诸如放宽微影制程解析限制，特定言之当元件4000按比例缩小时，以使得在两个相邻鳍特征230之间的空间变得越来越小。在众多方面中，形成第一经图案化的硬遮罩3240的方法与上文结合第5A及5B图论述的经图案化的硬遮罩510相似，包括其中论述的材料。
参看图15、20A、20B及20C，方法3000借由通过开口3245移除层间介电层260来形成源极/漏极接触沟槽3250而进行至步骤3020。由此，在源极/漏极接触沟槽3250中曝露指定的源极/漏极特征250。如先前提及，执行选择此沟槽蚀刻制程来选择性移除层间介电层260而实质上不蚀刻第二硬遮罩3230。如图所示，针对其中部分第二硬遮罩3230在开口3245中曝露的情况(如在图19A及19B中所示)，第二硬遮罩3230充当子蚀刻遮罩。因此，使用放宽制程限制的自动对准性质形成源极/漏极接触沟槽3250。沟槽蚀刻可包括选择性湿式蚀刻、选择性干式蚀刻、及/或上述蚀刻的组合。例如，沟槽蚀刻包括使用氟基化学，诸如四氟化碳(CF4)、六氟化硫(SF6)、二氟甲烷(CH2F2)、三氟甲烷(CHF3)及/或六氟乙烷(C2F6)的等离子干式蚀刻制程。
在形成源极/漏极接触沟槽3250之后，如在第20D图中所示，通过蚀刻制程移除第一经图案化的硬遮罩3240。在其中第一经图案化硬遮罩3240是光阻图案的一实例中，通过湿汽提及/或等离子灰化移除第一经图案化的硬遮罩3240。
参看图15、21A及21B，方法3000通过在源极/漏极接触沟槽3250中沉积导电层以形成源极/漏极接触金属3310而进行至步骤3022。如图所示，源极/漏极接触金属3310在源极/漏极接触沟槽3250中延伸至源极/漏极特征250。源极/漏极接触金属3310可包括铜(Cu)、铝(Al)、钨(W)、铜、镁铜(CuMn)、铝铜(CuAl)或硅铜(CuSi)、及/或其他适宜导电材料。可通过物理气相沉积、化学气相沉积、金属有机化学气相沉积(metal-organic chemical vapordeposition；MOCVD)、或电镀形成源极/漏极接触金属3310。在一些实施例中，进行化学机械研磨制程以从第二硬遮罩3230移除过量源极/漏极接触金属3310，以此提供与第二硬遮罩3230的顶面大体上共面的顶面。
参看图15、22A及22B，在形成源极/漏极接触金属3310之后，方法3000通过在第二硬遮罩3230及源极/漏极接触金属3310上形成第二经图案化的硬遮罩3410而进行至步骤3024。此第二经图案化的硬遮罩3410具有界定待后续形成的线切割的开口3415。开口3415对准高介电常数/金属栅极线410L的指定部分(例如，在两个鳍特征230间)，随后将其移除。在一些实施例中，开口3415具有沿线A-A方向的较大宽度，以使得相邻开槽的侧壁间隔245’及部分源极/漏极接触金属3310在开口3415中以获得优点，诸如放宽微影制程解析限制，尤其是当元件4000按比例缩小时，以使得在两个相邻鳍特征230之间的空间变得越来越小。在众多方面中，形成第二经图案化的硬遮罩3410的方法与上文结合图5A及5B论述的经图案化硬遮罩510相似，包括其中论述的材料。
参看图15、23A及23B，方法3000借由通过开口3415移除第二硬遮罩3230、硬遮罩1220’及侧壁间隔245’以曝露高介电常数/金属栅极堆叠410’的指定部分来进行至步骤3026。此蚀刻制程可包括湿式蚀刻、干式蚀刻、及/或上述蚀刻的组合。在一些实施例中，选择此蚀刻制程以选择性蚀刻第二硬遮罩3230及侧壁间隔245’而实质上不蚀刻高介电常数/金属栅极堆叠410’及源极/漏极接触金属3310。如图所示，针对其中部分源极/漏极接触金属3310在开口3415中曝露的情况(如在图22A及22B中所示)，源极/漏极接触金属3310充当子蚀刻遮罩。
参看图15、24A及24B，方法3000借由通过开口3415移除经曝露的高介电常数/金属栅极堆叠410’以形成线切割3420而进行至步骤3028。在本实施例中，线切割3420延伸至隔离特征220并将高介电常数/金属栅极线410L分为两子高介电常数/金属栅极线410LA及410LB。子高介电常数/金属栅极线410LA沿着图2A的线B-B方向与子高介电常数/金属栅极线410LB分离，且其距离具有宽度d。在众多方面中，此蚀刻制程是与上文结合图6A及6B论述的蚀刻制程相似。在形成线切割3420之后，如在第24C及24D图中所示，通过蚀刻制程移除第二经图案化的硬遮罩3410。
参看图15、25A及25B，方法3000通过使用介电层3510填充线切割3420以在两子高介电常数/金属栅极线410LA及410LB之间形成隔离区域3515而进行至步骤3030。在众多方面中，与上文结合图7A及7B论述的介电层710相似地形成介电层3510，包括其中论述的材料。可进行化学机械研磨来回磨平介电层3510并以此提供关于第二硬遮罩3230的顶面的介电层3510的大体上平坦顶面。由此，将高介电常数/金属栅极线410L切割为子高介电常数/金属栅极线410LA及410LB，并且高介电常数/金属栅极线410L由隔离区域3515分离。
在方法3000之前、期间、或之后可提供额外步骤，且可围绕方法3000的额外实施例取代、消除、或移动所描述的一些步骤。其他替代或实施例可不脱离本案的精神及范围存在。
半导体元件200、2000及4000可经进一步互补式金属氧化物半导体或金属氧化物半导体技术处理以形成在此项技术中已知的各特征及区域。例如，后续处理可在基板210上形成各触点/通道/接线及多层互连特征(例如，金属层及层间介电)，这些特征经配置以连接鳍式场效晶体管元件200的各特征或结构。例如，多层互连包括垂直互连，诸如常规通道或触点，及水准互连，诸如金属线。各互连特征可实施包括铜、钨、及/或硅化物的各导电材料。在一实例中，镶嵌及/或双重镶嵌制程是用于形成铜相关多层互连结构。
基于上文，可了解本案提供在高介电常数/金属栅极取代虚设栅极堆叠之后切割金属栅极线的方法。此方法提供切割金属栅极线的各制程方案，诸如在高介电常数/金属栅极取代虚设栅极堆叠之后切割金属栅极线或在形成源极/漏极接触金属之后切割金属栅极线。此方法阐明用于切割金属栅极线的可行且挠性制程。
本案提供制造半导体元件的众多不同实施例，此半导体元件提供在现存途径基础上的一或多个改良。本揭露的一实施例为一种用于制造半导体元件的方法包括在基板上形成第一鳍及第二鳍。第一鳍具有第一栅极区域而第二鳍具有第二栅极区域。此方法亦包括在第一及第二栅极区域上形成金属栅极线。此金属栅极线从第一鳍延伸至第二鳍。此方法亦包括施加线切割以将金属栅极线分为第一子金属栅极线与第二子金属栅极线，并且在线切割中形成隔离区域。
依据本揭露的部分实施例，其中施加线切割以将金属栅极线分为第一子金属栅极线与第二子金属栅极线包括形成第一经图案化的硬遮罩于金属栅极线上方，其中第一经图案化的硬遮罩界定一开口。经由开口蚀刻金属栅极线。
依据本揭露的部分实施例，其中在线切割中形成隔离区域包括形成介电层于线切割中，以及开槽介电层。
依据本揭露的部分实施例，此方法更包含先形成金属栅极线于第一栅极区域及第二栅极区域上方，并形成虚设栅极堆叠于第一栅极区域及第二栅极区域上方。形成层间介电层于基板以及虚设栅极堆叠上方。
依据本揭露的部分实施例，其中形成金属栅极线于第一栅极区域及第二栅极区域上方包含移除虚设栅极堆叠以曝露第一栅极区域及第二栅极区域的一部分。沉积栅极介电层于第一栅极区域及第二栅极区域的曝露的部分上方。沉积金属线于第一栅极区域及第二栅极区域内的栅极介电层上方。
依据本揭露的部分实施例，其中形成金属栅极线于第一栅极区域及第二栅极区域上方包括移除虚设栅极堆叠以曝露第一栅极区域及第二栅极区域的一部分。沉积栅极介电层于第一栅极区域及第二栅极区域的曝露的部分上方。沉积金属栅极线于第一栅极区域及第二栅极区域内的栅极介电层上方。开槽第一栅极区域及第二栅极区域内的栅极金属层的一部分。以及形成硬遮罩于经开槽的第一栅极区域及第二栅极区域内的栅极金属层的部分上方。
依据本揭露的部分实施例，其中施加线切割以将金属栅极线分为第一子金属栅极线与第二子金属栅极线包括形成经图案化的硬遮罩于硬遮罩上方，其中经图案化的硬遮罩具有开口，使得金属栅极线的一部分对齐开口。经由开口蚀刻硬遮罩。经由开口蚀刻金属栅极线。
依据本揭露的部分实施例，其中形成金属线于第一栅极区域及第二栅极区域内的栅极介电层上方包括形成金属栅极线于侧壁间隔之间。其中侧壁间隔及介电层的一部分自开口中曝露。其中经由开口蚀刻金属栅极线包含将曝露的侧壁间隔及介电层的一部分作为蚀刻遮罩。
本揭露的另一实施例为一种用于制造半导体元件的方法包括在基板上形成多个金属栅极堆叠，以使得此多个栅极堆叠彼此连接以形成金属栅极线。此多个金属栅极堆叠具有沿着金属栅极堆叠侧壁配置的侧壁间隔。此方法亦包括在邻近金属栅极堆叠的基板中形成源极/漏极特征、在金属栅极堆叠及源极/漏极特征上形成介电层、开槽多个金属栅极堆叠及侧壁间隔、在经开槽的多个金属栅极堆叠及经开槽的侧壁间隔上形成硬遮罩、移除部分介电层以曝露源极/漏极特征，同时此硬遮罩保护开槽的金属栅极堆叠及经开槽的侧壁间隔。此方法亦包括在经曝露的源极/漏极特征上形成接触金属层、形成线切割以将金属栅极线切割为子金属栅极线，并在线切割中形成隔离区域。
依据本揭露的部分实施例，其中在基板上形成多个金属栅极堆叠，以使得此多个栅极堆叠彼此连接以形成金属栅极线包括形成延伸自基板外的多个鳍，各鳍具有源极/漏极区域及栅极区域。形成虚设栅极堆叠于各栅极区域中。移除虚设栅极堆叠以曝露各鳍的部分。形成多个金属栅极堆叠于曝露的鳍的部分上方。
依据本揭露的部分实施例，其中开槽多个金属栅极堆叠及侧壁间隔包括开槽多个栅极堆叠而实质上不蚀刻侧壁间隔。形成另一硬遮罩于经开槽的栅极堆叠上方。开槽侧壁间隔而实质上不蚀刻另一硬遮罩，其中经开槽的侧壁间隔的上表面与硬遮罩的上表面实质上共平面。
依据本揭露的部分实施例，其中在经开槽的多个金属栅极堆叠及经开槽的侧壁间隔上形成硬遮罩包括形成硬遮罩于另一硬遮罩上方，并开槽侧壁间隔。
依据本揭露的部分实施例，其中形成线切割以将金属栅极线切割为子金属栅极线包括形成经图案化的硬遮罩于金属栅极线上方，其中经图案化的硬遮罩具有开口。经由开口蚀刻金属栅极线。
依据本揭露的部分实施例，其中经开槽的侧壁间隔及接触金属层的一部分曝露于开口中。其中经由开口蚀刻金属栅极线包括将侧壁间隔及接触金属层的部分作为蚀刻遮罩。
依据本揭露的部分实施例，其中在线切割中形成隔离区域包括以介电层填补于线切割内。开槽介电层。
本揭露的又一实施例为一种切割金属栅极的方法包括在基板上形成多个鳍，这些鳍中的各者具有栅极区域，在各栅极区域中形成虚设栅极堆叠，沿各虚设栅极堆叠的侧壁形成侧壁间隔，在包括除虚设栅极堆叠以外的基板上形成层间介电层。此方法亦包括移除虚设栅极堆叠以在此栅极区域中曝露部分鳍，在经曝露的部分鳍上形成金属栅极堆叠，其中此金属栅极堆叠形成金属栅极线，开槽金属栅极堆叠，在经开槽的金属栅极堆叠上形成硬遮罩，形成线切割以将金属栅极线切割为子金属栅极线，同时此硬遮罩保护金属栅极堆叠并在线切割中形成隔离区域。
依据本揭露的部分实施例，其中开槽金属栅极堆叠包括开槽金属栅极堆叠而实质上不蚀刻侧壁间隔及层间介电层。
依据本揭露的部分实施例，其中在经开槽的金属栅极堆叠上形成硬遮罩包括形成硬遮罩于另一硬遮罩上方。
依据本揭露的部分实施例，其中形成线切割以将金属栅极线切割为子金属栅极线包括形成经图案化的硬遮罩于金属栅极线上方，其中经图案化的硬遮罩具有开口。经由开口蚀刻硬遮罩。以及经由开口蚀刻金属栅极线。
依据本揭露的部分实施例，其中在线切割中形成隔离区域包括以介电层填补于线切割内。开槽介电层。
上文概述若干实施例的特征，使得熟悉此项技术者可更好地理解本揭露的态样。熟悉此项技术者应了解，可轻易使用本揭露作为设计或修改其他制程及结构的基础，以便实施本文所介绍的实施例的相同目的及/或达成相同优点。熟悉此项技术者亦应认识到，此类等效结构并未脱离本揭露的精神及范畴，且可在不脱离本揭露的精神及范畴的情况下进行本文的各种变化、替代及更改。

Claims (1)

1.一种切割金属栅极的方法，其特征在于，包含：
在一基板上形成一第一鳍及一第二鳍，该第一鳍具有一第一栅极区域及该第二鳍具有一第二栅极区域；
在该第一栅极区域与该第二栅极区域上形成一金属栅极线，其中该金属栅极线从该第一鳍延伸至该第二鳍；
施加一线切割以将该金属栅极线分为一第一子金属栅极线与一第二子金属栅极线；以及
在该线切割中形成一隔离区域。
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