CN109786463B - 金属栅极结构及其制造方法 - Google Patents

金属栅极结构及其制造方法 Download PDF

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CN109786463B
CN109786463B CN201811355119.5A CN201811355119A CN109786463B CN 109786463 B CN109786463 B CN 109786463B CN 201811355119 A CN201811355119 A CN 201811355119A CN 109786463 B CN109786463 B CN 109786463B
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opening
gate structure
fin
gate
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CN109786463A (zh
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杨宜伟
洪志昌
古淑瑗
陈嘉仁
张铭庆
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

半导体器件及其形成方法包括每个均从衬底延伸的第一鳍和第二鳍。第一栅极段设置在第一鳍上方，并且第二栅极段设置在第二鳍上方。层间介电(ILD)层邻近第一栅极段和第二栅极段。切割区域(例如，第一栅极结构和第二栅极结构之间的开口或间隙)在第一和第二栅极段之间延伸。切割区域具有第一部分和第二部分，第一部分具有第一宽度，第二部分具有第二宽度，第二宽度大于第一宽度。第二部分插入第一和第二栅极段，并且第一部分限定在ILD层内。本发明实施例涉及金属栅极结构及其制造方法。

Description

金属栅极结构及其制造方法
技术领域
本发明实施例涉及金属栅极结构及其制造方法。
背景技术
电子工业经历了对更小且更快的电子器件需求的不断增长，它们同时能够支持更多数量的越来越复杂和尖端的功能。因此，半导体工业中的持续的趋势是制造低成本、高性能和低功耗的集成电路(IC)。到目前为止，已经通过按比例缩小半导体IC尺寸(例如，最小部件尺寸)在很大程度上实现了这些目标，从而提高了生产效率并且降低了相关成本。然而，这种按比例缩小也增加了半导体制造工艺的复杂性。因此，实现半导体IC和器件的持续发展需要半导体制造工艺和技术中的类似发展。
已经引入多栅极器件以通过增加栅极-沟道耦合、减小截止电流和降低短沟道效应(SCE)致力于改进栅极控制。已经引入的一种这样的多栅极器件是鳍式场效应晶体管(FinFET)。FinFET的名字来源于鳍状结构，鳍状结构从衬底(其上形成该鳍状结构)延伸，并且鳍状结构用于形成FET沟道。FinFET与传统的互补金属氧化物半导体(CMOS)工艺兼容并且它们的三维结构允许它们在保持栅极控制和减轻SCE的同时积极地按比例缩小。此外，已经引入金属栅电极来替换多晶硅栅电极。金属栅电极提供了优于多晶硅栅电极的许多优势，诸如避免多晶硅耗尽效应，通过选择适当的栅极金属来调整功函数，以及其他益处。例如，金属栅电极制造工艺可以包括金属层沉积以及随后的后续金属层切割工艺。在一些情况下，金属栅极线切割工艺可能导致层间电介质(ILD)的部分损失、不期望的金属层的残留物和/或包括可能导致器件可靠性降低的那些问题的其他问题。
因此，现有技术并非在所有方面都已完全令人满意。
发明内容
根据本发明的一些实施例，提供了一种半导体器件，包括：第一鳍和第二鳍，各自均从衬底延伸；第一栅极段和第二栅极段，所述第一栅极段设置在所述第一鳍上方，所述第二栅极段设置在所述第二鳍上方；层间介电(ILD)层，邻近所述第一栅极段和所述第二栅极段；以及切割区域，在所述第一栅极段和所述第二栅极段之间延伸，其中，所述切割区域具有第一部分和第二部分，所述第一部分具有第一宽度，并且所述第二部分具有第二宽度，所述第二宽度大于所述第一宽度，并且其中，所述第二部分插入所述第一栅极段和所述第二栅极段，并且所述第一部分限定在所述层间介电层内。
根据本发明的另一些实施例，还提供了一种制造半导体器件的方法，包括：形成从半导体衬底延伸的第一鳍和第二鳍，其中，浅沟槽隔离件(STI)在所述第一鳍和所述第二鳍之间延伸；形成在所述第一鳍和所述第二鳍上方延伸的栅极结构；提供邻近所述栅极结构的介电层；蚀刻所述栅极结构和所述介电层以在所述栅极结构中形成至少延伸至所述浅沟槽隔离件的顶面的开口，其中，所述蚀刻形成的所述开口具有：开口的第一部分，具有第一宽度，所述第一部分可以由所述栅极结构的所述第一切割段的第一侧壁和所述栅极结构的第二切割段的第二侧壁限定；开口的第二部分，具有第二宽度，所述开口的第二部分具有由所述介电层限定的边缘，并且其中，所述第一宽度大于所述第二宽度；以及开口的第三部分，在顶视图中设置在所述第一部分和所述第二部分之间；以及用所述介电材料填充所述开口。
根据本发明的又一些实施例，还提供了一种制造半导体器件的方法，包括：将金属栅极结构切割成第一金属栅极段和共线的第二金属栅极段，其中，所述切割包括：实施第一工艺以沉积硅层；实施第二工艺以实施穿透蚀刻；实施所述金属栅极结构的功函金属层的蚀刻，其中，所述蚀刻可以包括高偏置和高占空比；实施聚合物沉积步骤；以及重复所述第一工艺、所述第二工艺、所述蚀刻和所述聚合物沉积步骤。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据本发明的一个或多个方面的FinFET器件的实施例的立体图；
图2是根据一些实施例的相邻的鳍、金属栅极结构和金属栅极切割图案的顶视图；
图3A和图3B示出了根据本发明的实施例的其中已经切割金属栅极线的FinFET结构的相应截面图；
图4示出了根据本发明的实施例的其中已经切割金属栅极线的FinFET结构的顶视图；
图5是根据本发明的一个或多个方面的半导体制造方法的流程图；
图6A、图7A、图8A、图9A、图10A、图11A、图12A、图13A和图14A示出了沿着与由图1的截面XX’限定的平面基本平行的平面并且根据图5的方法的实施例制造的FinFET结构的截面图；
图6B、图7B、图8B、图9B、图10B、图11B、图12B、图13B和图14B示出了沿着与由图1的截面YY’限定的平面基本平行的平面并且根据图5的方法的实施例制造的FinFET结构的截面图；以及
图12C和图14C示出了诸如图1中提供的并且根据图5的方法的实施例制造的FinFET结构的顶视图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
还应注意，本发明以多栅极晶体管或鳍式多栅极晶体管(本文称为FinFET器件)的形式来呈现实施例。这种器件可以包括P型金属氧化物半导体FinFET器件或N型金属氧化物半导体FinFET器件。FinFET器件可以是双栅极器件、三栅极器件、块状器件、绝缘体上硅(SOI)器件和/或其他配置。本领域普通技术人员可以意识到可以受益于本发明的各个方面的半导体器件的其他实例。例如，本文中描述的一些实施例也可以应用于全环栅(GAA)器件、欧米茄栅极(Ω栅极)器件或Pi栅极(Π栅极)器件。在其他实施例中，可以使用本文所讨论的一种或多种结构或方法来制造平面器件。
还应注意，示出的附图是形成在衬底上的器件的示例性部分，因此，在一些实例中示出了两个鳍，在其他实例中示出了其他额外的鳍，在一些实例中示出了两个栅极，在其他实例中示出了单个栅极或额外的栅极。如本领域普通技术人员理解的，在半导体器件中通常存在多个栅极和鳍，并且因此，附图中示出的栅极或鳍的数量仅用于参考，并且不旨在限制其应用。
本申请通常涉及金属栅极结构和相关方法。具体地，本发明针对金属栅极切割工艺和相关的结构。已经引入金属栅电极来替换多晶硅栅电极。金属栅电极提供了优于多晶硅栅电极的许多优势，诸如避免多晶硅耗尽效应、通过选择适当的栅极金属来调整功函数，以及其他益处。例如，金属栅电极制造工艺可以包括金属层沉积。在形成横跨衬底的区域延伸的金属栅极之后，可能需要将某些金属栅极线“切割”或分成彼此隔离的段，以提供设计所需的晶体管级功能。因此，根据本文讨论的实施例，金属栅电极的形成之后可以是随后的金属栅极切割工艺。
本发明的实施例提供了优于现有技术的若干优势，但是应该理解，其他的实施例可以提供不同的优势，不是所有的优势都必需在此处讨论，并且没有特定的优势对所有实施例都是需要的。通常，根据本文公开的实施例，提供了金属栅极切割工艺和相关的结构。本发明的至少一些实施例可以用于提供切割栅极段的轮廓和通过切割实现的开口，其允许金属栅极结构的现切割段之间的改进的隔离。例如，在至少一些现有工艺中，可以提供逐渐变细的轮廓，从而使得在切割栅极段之间难以实现合适的分隔距离以及随后难以用介电材料填充切割区域。这些困难可能导致切割栅极段之间的隔离效果不足。为了减轻一个或多个问题，本发明提供了切割金属栅极工艺和结构，在一些实施例中，这些工艺和结构可以改进切割栅极段之间的隔离。
图1中示出的是FinFET器件100。本文描述的各个实施例可以用于制造FinFET器件100和/或可以呈现在FinFET器件100的最终结构中。FinFET器件100包括一个或多个鳍基多栅极场效应晶体管(FET)。FinFET器件100包括衬底102、从衬底102延伸的鳍元件(或鳍)104、隔离结构106和设置在一些鳍104上和周围的栅极结构108。衬底102可以是诸如硅衬底的半导体衬底。衬底可以包括各个层，包括形成在半导体衬底上的导电或绝缘层。取决于本领域已知的设计要求，衬底可以包括各种掺杂配置。衬底也可以包括其他半导体，诸如锗、碳化硅(SiC)、硅锗(SiGe)或金刚石。可选地，该衬底可以包括化合物半导体和/或合金半导体。此外，在一些实施例中，该衬底可以包括外延层(epi层)，该衬底可以是应变的以增强性能，该衬底可以包括绝缘体上硅(SOI)结构和/或该衬底可以具有其他合适的增强部件。
与衬底102类似，鳍104可以包括硅或另一元素半导体，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、InGaAs、GaInP和/或GaInAsP；或它们的组合。可以使用包括光刻和蚀刻工艺的合适的工艺来制造鳍104。光刻工艺可以包括：在衬底上面(例如，硅层上)形成光刻胶层(抗蚀剂)，将光刻胶暴露于图案，实施曝光后烘烤工艺以及显影光刻胶以形成包括光刻胶的掩蔽元件。在一些实施例中，可以使用极紫外(EUV)光刻工艺或电子束(e束)光刻工艺来实施图案化光刻胶，以形成掩蔽元件。然后，掩蔽元件可以通过蚀刻工艺在硅层中形成凹槽的同时用于保护衬底的区域，从而留下延伸的鳍104。可以使用干蚀刻(例如，化学氧化物去除)、湿蚀刻和/或其他合适的工艺来蚀刻凹槽。也可以使用在衬底102上形成鳍104的许多其他方法实施例。
多个鳍104的每个也包括源极区域105和漏极区域107，其中，源极/漏极区域105、107形成在鳍104中、上和/或周围。可以在鳍104或它们的部分上方外延生长源极/漏极区域105、107。晶体管的沟道区域设置在栅极结构108下面的鳍104内。在一些实例中，鳍104的沟道区域包括诸如锗的高迁移率材料，以及以上讨论的任何化合物半导体或合金半导体和/或它们的组合。高迁移率材料包括电子迁移率大于硅的那些材料。
隔离区域106可以是浅沟槽隔离(STI)部件。可选地，可以在衬底102上和/或内实现场氧化物、LOCOS部件和/或其他合适的隔离部件。隔离结构106可以由氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料、它们的组合和/或本领域已知的其他合适的材料组成。在实施例中，隔离结构是STI部件并且通过在衬底102中蚀刻沟槽形成。随后可以用隔离材料填充沟槽，以及随后是化学机械平坦化(CMP)工艺。然而，其他实施例是可能的。在一些实施例中，隔离区域106可以包括多层结构(例如，具有一个或多个衬垫层)。
栅极结构108包括栅极堆叠件，在一些实施例中，栅极堆叠件具有形成在鳍104的沟道区域上方的界面层、形成在界面层上方的栅极介电层110以及形成在栅极介电层110上方的至少一个金属层112。界面层可以包括诸如氧化硅层(SiO2)或氮氧化硅(SiON)的介电材料。可以通过化学氧化、热氧化、原子层沉积(ALD)、化学汽相沉积(CVD)和/或其他合适的方法来形成界面层。栅极介电层110可以包括诸如氧化铪(HfO2)的高k介电层。可选地，高k介电层可以包括其他高k电介质，诸如TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、它们的组合或其他合适的材料。在仍一些其他实施例中，栅极介电层可以包括二氧化硅或其他合适的电介质。可以通过ALD、物理汽相沉积(PVD)、氧化和/或其他合适的方法形成介电层。金属层112代表一种或多种金属组分，并且可以包括导电层，诸如W、TiN、TaN、WN、Re、Ir、Ru、Mo、Al、Co、Ni、它们的组合和/或其他合适的组分。在一些实施例中，金属层112可以包括用于N型FinFET的第一金属材料和用于P型FinFET的第二金属材料。因此FinFET器件100可以包括双功函金属栅极配置。例如，第一金属材料(例如，用于N型器件)可以包括具有与衬底导带的功函数基本匹配，或至少与鳍104的沟道区域的导带的功函数基本匹配的功函数的金属。同样地，例如，第二金属材料(例如，用于P型器件)可以包括具有与衬底价带的功函数基本匹配，或至少与鳍104的沟道区域的价带的功函数基本匹配的功函数的金属。金属层112可以包括另外的并且包括那些提供功函数的各个层，各个层包括例如阻挡层、晶种层、覆盖层、填充层和/或其他合适的组成和功能，包括下面讨论的那些。因此，金属层112可以为包括N型和P型FinFET器件100的FinFET器件100提供栅电极。可以使用PVD、CVD、电子束(e束)蒸发和/或其他合适的工艺形成金属层112。在一些实施例中，在栅极结构108的侧壁上形成侧壁间隔件116。侧壁间隔件116可以包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅或它们的组合的介电材料。硬掩模层114(例如，氮化硅等)可以设置在栅极结构108的金属层112的区域上方。
应该注意，层间介电(ILD)层可以设置在衬底102上，包括在隔离区域106和源极/漏极区域105/107上方。为了便于说明其他层，图1中未示出ILD层。如下面讨论的，金属栅极切割图案(例如，图2的210)用于限定去除栅极结构108的部分的区域，从而提供栅极结构108的不连续切割金属栅极段(108A、108B)。金属栅极切割图案内的栅极结构的去除部分形成开口118。开口118的细节可以基本如下，包括参照图3A、图3B和图4的轮廓。随后可以用包括下面诸如图13A、图13B、图14A、图14B以及图14C的实例中讨论的绝缘材料填充开口118。
参照图2，其中示出了相邻鳍104和设置在鳍104上方并且基本垂直于鳍104的金属栅极结构108的顶视图。在一些实施例中，图2的截面XX’可以基本平行于由图1的截面XX’限定的平面，并且图2的截面YY’可以基本平行于由图1的截面YY’限定的平面。在一些情况下，鳍104可以与上述鳍104基本相同，并且金属栅极结构108在至少一些方面可以与上述栅极结构108类似。例如，图2示出了金属栅极切割图案210，其在一些示例中可以由图案化的硬掩模层(包括下面描述的)限定。在一些实施例中，金属栅极切割图案210提供位于例如图案化的硬掩模层中的开口(也称为插入金属栅极结构的段的间隔或区域)，通过该开口，实施金属栅极线切割工艺。可以切割开口下方的金属栅极结构108的部分212，从而使得在开口内从衬底去除金属栅极结构，从而提供不连续的金属栅极结构段的第一和第二部分(例如，108A、108B)以及位于它们之间的开口(例如，118)。在一些实施例中，金属栅极切割图案210(例如，硬掩模中的开口)的形状基本为如图2中示出的矩形。在一些实施例中，金属栅极切割图案210具有限定的矩形形状，而使用所述形状的图案210形成的所得开口(或区域)118(见图1、图3A、图3B和图4)可以不是矩形，而具有下面讨论的轮廓。在一些实施例中，开口118的轮廓由与金属栅极切割图案210结合使用的蚀刻工艺限定。如本文描述的金属栅极切割工艺可以包括干蚀刻工艺、湿蚀刻工艺或它们的组合，如下面详细讨论的，其用于去除由金属栅极切割图案210限定的区内的金属栅极结构108的部分。例如，金属栅极线切割工艺可以用于将金属栅极线切割成分离的、电断开的和不连续的线段108A和108B。在一些实施例中，作为金属栅极线切割工艺的一部分，可以在线切割区域(例如，已经去除金属栅极层的部分的位置、图1的开口118)内形成介电层。如图所示，金属栅极切割图案210可以与设置在衬底上的隔离区域(诸如图1的隔离区域106)重叠。然而，在其他实施例中，金属栅极切割图案210可以位于诸如鳍104的鳍上面，例如，其中金属栅极切割图案210下面的鳍104整个或部分是伪鳍。
参照图3A，示出了沿着基本平行于由图1和/或图2的截面YY’限定的平面的平面的FinFET结构100的部分的截面图。参照图3B，其中示出了沿着基本平行于由图1和/或图2的截面XX’限定的平面的平面的FinFET结构100的部分的截面图。FinFET结构100包括已经切割的金属栅极结构108(108A、108B)。可以根据包括参照图5的本文讨论的一些实施例切割金属栅极结构108。FinFET结构100可以包括以上参照图1和图2描述的一个或多个部件，诸如从衬底102延伸的鳍元件104、隔离区域106以及设置在鳍元件104上和周围的栅极结构108。栅极结构108可以与以上讨论的图1和/或图2的栅极结构108基本类似。栅极结构108可以是金属栅极结构，诸如包括具有栅极介电层和形成在栅极介电层上方的金属层的栅极堆叠件。在一些实例中，金属层可以包括多种金属材料，包括例如第一金属材料(例如，诸如P型功函金属(PWFM))、位于第一金属材料上方的第二金属材料(例如，诸如N型功函金属(NWFM))以及位于第二金属材料上方的第三金属材料(例如，诸如填充金属(例如，钨))等。硬掩模层302和304设置在栅极结构108上方。硬掩模层302和/或304可以与以上在图1中示出的硬掩模层114基本类似。在实施例中，硬掩模层302包括氮化硅。在实施例中，层304包括氮化钛(TiN)。然而，其他合适的组分是可能的。
图3A还示出了由硬掩模层304、302限定的金属栅极切割区域210。在该开口下方限定金属栅极切割区域210，栅极结构108被“切割”，从而使得它是不连续的并且在它们之间形成开口118。“切割”可以形成为如包括参照图5的本文描述的金属栅极线切割工艺的一部分。在各种情况下，在随后的工艺步骤中，可以在开口118的区域内形成插入栅极段108A、108B的介电层。介电层可以是与隔离区域106的材料和/或邻近ILD层的介电材料不同的介电组分，如下面讨论的。
应该注意，金属栅极切割区域210提供延伸至STI 106或延伸至STI 106内的开口118(也称为沟槽)。在实施例中，开口118从金属栅极结构108的最上金属层的顶面至开口118的最低点延伸距离D1。D1可以在约150纳米(nm)和180nm之间。开口的距离D1大于T1，T1是包括栅极电介质110和位于栅极电介质110上面的多个金属层的金属栅极的厚度。如图3A的实施例示出的，开口118延伸至STI 106内。开口118可以延伸到至STI 106内距离D2。距离D2可以在约30nm和70nm之间。在实施例中，深度D2是STI 106的厚度T2的至少约45％。可以提供过蚀刻(例如，45％过蚀刻(OE))以减轻金属栅极结构108的残留物在金属栅极切割区域210的开口118中的风险。
在实施例中，由金属栅极切割区域210限定的开口118的轮廓具有基本线性侧壁308。基本线性侧壁308基本垂直于衬底102的顶面。如本文提供的术语“基本”意味着在金属栅极108的整个厚度T1上，侧壁在垂直于衬底102的顶面的约10％内。应该注意，通常在本申请中，在制造控制的合理容限(例如，10％)内，诸如“基本”或“约”的术语可以被解释为本领域普通技术人员将意识到的。
在实施例中，开口118的轮廓在开口的顶部具有宽度W1，并且在开口的底部具有宽度W4。在进一步实施例中，在金属栅极结构108的最上金属层的顶面处测量W1。在进一步实施例中，在栅极108的部分下面的隔离结构106的顶面测量W4。W4可以大于W1。在实施例中，W4比W1大至少10％。W4可以在约15nm和25nm之间，并且W1可以在10nm和30nm之间。在进一步实施例中，开口118的介于W1和W4的测量位置之间的宽度可以小于W1。在一些实施例中，在邻近栅极的开口118中测量的W1和/或宽度(从金属栅极108A至金属栅极108B的侧壁的宽度)可以比W4小约20％(nm)。
在一些实施例中，开口118的轮廓也可以表征为具有如图4中示出的角度θ。角度θ可以小于约45度。如图4中示出的角度θ测量为开口118的侧壁和平行于栅极结构108的侧壁(垂直于鳍104的方向)的水平面之间的角度。
图3B示出了来自图1的XX’的金属栅极切割区域210的开口118。ILD层(以上讨论的)示出为ILD 306。ILD层306可以通过化学汽相沉积(CVD)或其他合适的沉积工艺形成，并且在一些实施例中，可以在沉积之后平坦化。作为其组分的非限制性实例，ILD层306可以包括二氧化硅、氮化硅、氮氧化硅、含碳电介质、TEOS以及这些的组合，并且可以是低k、高k或氧化物电介质，并且可以由用于ILD层的其他已知材料形成。应该注意，ILD层306示出为单层，但是该器件通常也包括其他介电材料，诸如额外的间隔件元件、蚀刻停止层等。应该注意，开口118延伸至STI 106的顶面，在一些实施例中，开口118延伸至STI 106内(如参照图3A讨论的)。
图4示出了诸如图1的FinFET器件100的示例性器件的部分的顶视图。示出的鳍104、金属栅极结构108和ILD 306可以与以上讨论的基本类似。开口118(由以上讨论的金属栅极切割区域210限定的)在顶视图中具有包括宽度W3和宽度W2的轮廓。开口具有与金属栅极结构108共线的更大宽度W3。换句话说，金属栅极切割区域210的去除金属栅极结构的部分处的开口118的宽度大于金属栅极切割区域210的邻近于金属栅极结构但是与金属栅极结构间隔开的部分(换句话说，围绕栅极108的介电区域(诸如，ILD 306(图3B)))处的开口118的宽度。这可能是由于下面讨论的金属栅极切割工艺的蚀刻工艺。在实施例中，开口118具有从较大宽度(例如，W3)延伸至较窄宽度(例如，W2)部分的基本曲线的侧壁。如图所示，图4的W3对应于(例如，等于)图3A的YY’切割的W1。
现在参照图5，其中示出了根据至少一些实施例的半导体制造方法500的流程图。也可以在方法500之前、期间和之后提供额外的步骤，并且对于该方法的额外的实施例，可以在其他步骤之前或之后替换、消除或移动所描述的一些步骤。应该注意，方法500是示例性的，并且除了权利要求中的明确列举的之外，方法500不旨在限制本发明。方法500将在下面结合图6A、图6B、图7A、图7B、图8A、图8B、图9A、图9B、图10A、图10B、图11A、图11B、图12A、图12B、图12C、图13A、图13B、图14A、图14B和图14C进一步描述。图6A、图7A、图8A、图9A、图10A、图11A、图12A、图13A和图14A示出了沿着基本平行于由图1的截面XX’限定的平面的平面的FinFET结构600的截面图，并且图6B、图7B、8B、图9B、图10B、图11B、图12B、图13B和图14B示出了沿着基本平行于由图1的截面YY’限定的平面的平面的结构600的截面图。
在各个实施例中，方法500开始于框502，其中，提供包括鳍和隔离区域的衬底。参照图6A和图6B的实例，并且在框502的实施例中，示出了示例性结构600。子结构600可以是诸如FinFET结构100的FinFET结构的一部分。结构600可以包括以上参照图1描述的一个或多个部件，诸如从衬底102延伸的鳍元件104、隔离区域106、邻接金属栅极结构108的侧壁间隔件116以及ILD层306。
在一些实施例中，方法500通过替换栅极工艺提供金属栅极结构108，其中，在鳍上方形成伪栅极(例如，多晶硅)并且随后去除伪栅极以形成沟槽，在沟槽内形成金属栅极结构108。沟槽可以由诸如间隔件元件116的间隔件元件限定。
然后，方法500进行至框504，其中，在衬底102上形成金属栅极结构。金属栅极结构可以形成在由伪栅极的去除而提供的沟槽中。金属栅极结构可以包括多个层，该多个层包括界面层、栅极介电层、功函层、阻挡层、粘合层、扩散层、金属填充层和/或形成在沟槽内的其他合适的层中的一个或多个。
参照图6A和图6B的实例，在衬底102上(包括在鳍104上方和鳍104的侧壁上)形成金属栅极结构108。金属栅极结构108具有栅极介电层110和上面的金属层。
在一些实施例中，金属栅极结构108的上面的金属层可以包括一个或多个功函层。在一些实施例中，功函金属层包括p型功函金属(PWFM)。仅举例来说，PWFM层可以包括Ni、Pd、Pt、Be、Ir、Te、Re、Ru、Rh、W、Mo、WN、RuN、MoN、TiN、TaN、WC、TaC、TiC、TiAlN、TaAlN或它们的组合。在各个实施例中，可以使用PVD、CVD、电子束(e束)蒸发和/或其他合适的工艺形成PWFM层。金属栅极结构108可以额外地或可选地包括金属层的功函层，该功函层包括n型功函层(NWFM)，其可以包括例如Ni、Pd、Pt、Be、Ir、Te、Re、Ru、Rh、W、Mo、WN、RuN、MoN、TiN、TaN、WC、TaC、TiC、TiAlN、TaAlN或它们的组合。在各个实施例中，可以使用PVD、CVD、电子束(e束)蒸发和/或其他合适的工艺来形成NWFM层。在一些实施例中，填充金属层、阻挡层、扩散层和/或其他合适的层包括在金属栅极结构的多个层中。金属栅极结构108的示例性金属层可以包括其他金属，诸如Ni、Pd、Pt、Be、Ir、Te、Re、Ru、Rh、W、Mo、WN、RuN、MoN、TiN、TaN、WC、TaC、TiC、TiAlN、TaAlN或它们的组合。
金属栅极结构108也包括位于金属栅极结构108的金属层下方的栅极介电层110(并且在一些情况下包括下面的界面层)。栅极介电层110可以包括诸如氧化铪的高k电介质。可以使用原子层沉积(ALD)、物理汽相沉积(PVD)、包括等离子体增强CVD的CVD和/或其他合适的沉积工艺来形成金属栅极结构108的这些层中的任何一个或多个。应该注意，方法500可以包括在金属栅极结构的形成期间实施的一个或多个化学机械抛光(CMP)工艺。
方法500进行至框506，其中，在衬底上沉积硬掩模层并且图案化硬掩模层以提供限定金属栅极切割区域的开口。硬掩模层可以是设置在衬底102和栅极结构108上方的一个或多个层。在一些实施例中，硬掩模层可以包括图案化的氮化硅(SiN)层。在进一步实施例中，硬掩模层可以包括图案化的氮化硅(SiN)层和下面的氮化钛(TiN)层。可选地或额外地，在一些实施例中，硬掩模层可以包括其他介电材料，诸如氮氧化硅、碳化硅或其他合适的材料。
参照图7A和图7B的实例，沉积硬掩模层堆叠件702。硬掩模层堆叠件702包括第一层702A和第二层702B。在实施例中，第一层702A包括氮化硅，并且第二层702B包括氮化钛。在一些实施例中，可以通过原子层沉积(ALD)或其他合适的沉积方法形成硬掩模层堆叠件702。在一些实施例中，硬掩模堆叠件702的厚度可以在约25nm和100nm之间。
参照图8A和图8B的实例，在硬掩模层堆叠件702上方形成图案化层。随后，可以将图案化层的图案转印至硬掩模层堆叠件702。如图8A和图8B中示出的，在衬底102上方形成三层光刻胶802的图案化层。三层光刻胶802可以包括底层802A、中间层802B和上层802C。在实施例中，上层802C是使用合适的光刻技术在其内曝光和显影图案的光刻胶。如图8A和图8B中示出的，在图案化层中形成开口804。可以限定开口804以提供以上讨论的金属切割栅极区域210。开口804可以限定将在其下方实施金属栅极线切割的区域(例如，矩形形状)。应该注意，单个开口804可以在待“切割”的多个金属栅极上方延伸。此外，应该注意，可以在衬底102上方同时形成多个开口804。
参照图9A和图9B的实例，将形成在光刻胶802中的图案转印至硬掩模层堆叠件702，从而在硬掩模层堆叠件702中形成开口902。开口902可以暴露待切割的或部分地从衬底去除的一个或多个金属栅极结构108。开口902可以对应于以上讨论的切割金属栅极图案210。可以通过包括例如等离子体蚀刻的合适的蚀刻工艺处理形成开口902(例如，硬掩模开口)。
在一些实施例中，如图10A和图10B中示出的，在硬掩模层堆叠件702中形成开口902之后，实施再沉积工艺。再沉积工艺可以包括原子层沉积(ALD)。在一些实施例中，再沉积工艺包括沉积与第一层702A中提供的材料相同的材料。例如，在一些实施例中，在再沉积工艺中沉积氮化硅，而第一层702A也包括氮化硅。在实施例中，可以在硬掩模层堆叠件702上再沉积小于10纳米(例如，5nm、4nm、3nm)的再沉积层1002。如图11A和图11B中示出的，在再沉积工艺之后，可以实施硬掩模打开(HMO)工艺以从开口902的底部去除再沉积层1002，而保留开口902的侧壁上的再沉积层1002。由图11A和图11B提供的开口与金属栅极切割区域210基本类似。例如，开口902可以是基本矩形的形状并且暴露待切割的一个或多个栅极结构108的部分。
应该注意，在硬掩模层堆叠件702中形成开口的上述工艺可以包括半导体制造的典型的各个其他工艺，包括光刻胶剥离和/或去渣、检查、清洁、测量和/或其他合适的工艺。在实施包括以上讨论的一个或多个步骤的框506之后，设置在栅极结构上方的硬掩模层包括限定与上述金属栅极切割区域210类似的栅极切割区域的开口。然后，硬掩模层和相关开口可以用作下面讨论的随后的栅极切割蚀刻工艺中的掩蔽元件。
然后，方法500进行到框508，其中，在使用图案化的硬掩模作为掩蔽元件的同时实施金属栅极线切割工艺。在一些实施例中，金属栅极线切割工艺包括按照顺序的多个沉积和蚀刻步骤。应该注意，待形成的开口的高宽比可以大于10。例如，使用图3A说明，开口的深度(D1)可以在约140和170nm之间，而开口的宽度W1可以为D1的10％。由于这种侵略性高宽比，沉积可以与去除蚀刻结合实施，以精确地控制产生的开口(例如118)的轮廓。
在实施例中，切割金属栅极工艺包括第一系列工艺以及随后的第二系列工艺。在一些实施例中，在实施多次第二系列工艺之前实施多次第一系列工艺。在实施例中，在实施第二系列工艺之前实施六(6)次第一系列工艺。在一些实施例中，在实施(例如，多次)第一系列工艺之后实施多次第二系列工艺。例如，在实施例中，实施八(8)次第二系列工艺。因此，例如，在实施例中，实施六(6)次第一系列工艺，以及随后实施(8)次第二系列工艺。
切割工艺的第一系列工艺：在实施例中，第一系列工艺可以通过干蚀刻设备实施。在实施例中，第一系列工艺包括以下步骤中的一个或多个：
Figure GDA0003381596430000151
在实施例中，以上沉积步骤可以提供硅基层在开口的侧壁上的沉积。形成的示例性层包括SiOC和氧化硅(SiO2)。示例性工艺条件包括：
·功率-500-1500瓦(W)
·持续时间-3-8秒
·工艺温度-80-120摄氏度(C)
·压力-5至15mTorr(mT)
·流速-50至100sccm
在实施例中，穿透蚀刻步骤提供蚀刻穿过形成在成形开口上的任何氧化物。示例性工艺条件包括：
·功率-50-250W
·持续时间-5-30s
·工艺温度-80-120C
·压力-5-15mT
·流速-10-150sccm
金属(功函)蚀刻可以包括对蚀刻的金属栅极结构层具有选择性的蚀刻化学物质，同时最小化对周围电介质(例如，STI 106、ILD 306、间隔件116)的蚀刻。除了以上实例之外，金属蚀刻工艺可以包括其他含氯气体(例如，Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如，HBr和/或CHBr3)、含碘气体、其他合适的气体和/或等离子体和/或它们的组合。示例性工艺条件包括：
·功率-1000-2000W
·持续时间-20-50s
·工艺温度-80-120摄氏度(C)
·压力-5-15mT
·流速-500-1000sccm
参照以上第一系列工艺的最终步骤，可控沉积步骤，该步骤可以提供聚合物沉积，其与其他步骤一起可以控制所得开口的轮廓。例如，CH4与O2一起可以提供具有控制能力的C-H聚合物沉积步骤(例如，通过该步骤中提供的O2灰化控制沉积的量)。在一些实施例中，该可控沉积可以防止或减轻弯曲轮廓。参照以上第一系列工艺，O2可以通过金属氧化来控制切割金属栅极临界尺寸。可控沉积步骤可以可选地包括其他蚀刻化学物质，诸如C2H4、SO2。示例性工艺条件包括：
·功率-300-800W
·持续时间-5-20s
·工艺温度-80-120度
·压力-5-30mTorr
·流速-100-300sccm
切割工艺的第二系列工艺：在实施例中，第二系列工艺也可以通过干蚀刻设备实施。第二系列工艺可以在与第一系列工艺相同的蚀刻器中实施。在实施例中，第二系列工艺包括以下步骤中的一个或多个：
Figure GDA0003381596430000161
Figure GDA0003381596430000171
在实施例中，沉积步骤可以与以上参照第一系列工艺讨论的基本类似。
在实施例中，穿透蚀刻步骤可以与以上参照第一系列工艺讨论的类似。
金属(功函)蚀刻可以包括具有高偏置功率的等离子体蚀刻。高偏置功率包括1500W以上的功率和60V以上的偏置电压。在实施例中，金属(功函)蚀刻可以包括具有高占空比的等离子体蚀刻。高占空比包括大于25％的占空比。在一些实施例中，占空比频率在约50Hz(赫兹)和150Hz之间的范围。
金属(功函)蚀刻可以包括对蚀刻的金属栅极结构层具有选择性的蚀刻化学物质，同时最小化对周围电介质(例如，STI 106、ILD 306、间隔件116)的蚀刻。金属蚀刻工艺可以包括其他含氯气体(例如，Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如，HBr和/或CHBr3)、含碘气体、其他合适的气体和/或等离子体和/或它们的组合。
·持续时间-10％至50％
·频率–50Hz至150Hz
·蚀刻化学物质-He/Cl2/SiCl4/BCl3
·工艺温度-80-120度
·压力-5-15mTorr
·流速-500-1000sccm
可控沉积步骤(例如，CH4、O2)可以与以上参照第一系列工艺讨论的基本类似。
在一些实施例中，第一系列工艺和第二系列工艺步骤的性能提供了金属栅极切割区域中的开口的轮廓，诸如示例性图12A、图12B和图12C中示出的。开口1202可以与以上参照图1、图3A、图3B和图4描述的开口118基本类似。例如，包括W1、W2、D1、D2、T1和T2的尺寸关系的相同轮廓也可以适用于图12A、图12B和图12C的器件600。在实施例中，角度θ可以与以上讨论的基本类似。应该注意，图12C示出了切割两个栅极结构108的开口。然而，开口可以延伸任何数量的栅极结构108。
如上所述的框508中的一系列蚀刻步骤，本发明的实施例可以提供切割区域，由于开口轮廓的加宽(例如，开口118的W2，其也适用于开口1202)，该切割区域允许合适的蚀刻剂可以以增加的速率到达开口(例如，1202)的底部。在一些实施例中，这可以在栅极结构的切割段之间提供更完全的隔离，这可以减轻电流泄漏并因此有益于晶体管性能。
方法500进入框510和512，其中，继续制造结构600。在一些实施例中，在切割区域(例如，开口1202)中沉积介电层。在进一步实施例中，在介电层的沉积之后实施CMP工艺。可以在如以上参照框506描述的硬掩模层上方沉积介电层。在其他实施例中，可以在沉积介电层之前去除框506的硬掩模层。
参照图13A和图13B的实例，在框512的实施例中，可以沉积介电层1402。在一些实施例中，然后实施CMP工艺以平坦化介电层1402的顶面(见图14A、图14B和图14C)。在一些实施例中，介电层1402可以包括氧化硅、氮化硅、氮氧化物和/或其他合适的介电材料层。因此，在各个实施例中，介电层1402可以进一步用于电隔离相邻栅极堆叠件的栅极金属线。介电层1402可以是与ILD层306和/或隔离区域106不同的组分。在填充开口1202之后，应该注意，插入栅极结构108的介电层1402具有与以上讨论的相同的尺寸和轮廓。
FinFET结构600可以继续经受进一步处理以形成本领域中已知的各个部件和区域。例如，随后的工艺可以在衬底上形成各个接触件/通孔/线和多层互连部件(例如，金属层和层间电介质)，被配置为连接各个部件以形成可以包括一个或多个FinFET器件的功能电路。在进一步实例中，多层互连件可以包括诸如通孔或接触件的垂直互连件，以及诸如金属线的水平互连件。各个互连部件可以采用各种导电材料，包括铜、钨和/或硅化物。在一个实例中，镶嵌和/或双镶嵌工艺用于形成铜相关的多层互连结构。
根据本发明的一些实施例，提供了一种半导体器件，包括：第一鳍和第二鳍，各自均从衬底延伸；第一栅极段和第二栅极段，所述第一栅极段设置在所述第一鳍上方，所述第二栅极段设置在所述第二鳍上方；层间介电(ILD)层，邻近所述第一栅极段和所述第二栅极段；以及切割区域，在所述第一栅极段和所述第二栅极段之间延伸，其中，所述切割区域具有第一部分和第二部分，所述第一部分具有第一宽度，并且所述第二部分具有第二宽度，所述第二宽度大于所述第一宽度，并且其中，所述第二部分插入所述第一栅极段和所述第二栅极段，并且所述第一部分限定在所述层间介电层内。
在上述半导体器件中，所述切割区域的从所述第一部分延伸至所述第二部分的侧壁相对于与所述第一鳍的长度垂直定向并且与所述衬底的顶面垂直定向的平面以角度θ设置。
在上述半导体器件中，所述第一宽度和所述第二宽度从所述切割区域的顶视图测量。
在上述半导体器件中，用介电材料填充所述切割区域。
在上述半导体器件中，所述切割区域延伸至所述第一鳍和所述第二鳍之间的浅沟槽隔离部件内。
在上述半导体器件中，所述切割区域在所述浅沟槽隔离部件的顶面处具有第三宽度，并且在所述第一栅极段和所述第二栅极段之间具有在所述第三宽度之上的所述第二宽度，其中，所述第三宽度和所述第二宽度在平行于所述衬底的顶面的平面上测量。
在上述半导体器件中，所述第一栅极段具有第一线性侧壁，并且所述第二栅极段具有第二线性侧壁，其中，所述介电材料在所述第一线性侧壁和所述第二线性侧壁之间延伸。
根据本发明的另一些实施例，还提供了一种制造半导体器件的方法，包括：形成从半导体衬底延伸的第一鳍和第二鳍，其中，浅沟槽隔离件(STI)在所述第一鳍和所述第二鳍之间延伸；形成在所述第一鳍和所述第二鳍上方延伸的栅极结构；提供邻近所述栅极结构的介电层；蚀刻所述栅极结构和所述介电层以在所述栅极结构中形成至少延伸至所述浅沟槽隔离件的顶面的开口，其中，所述蚀刻形成的所述开口具有：开口的第一部分，具有第一宽度，所述第一部分可以由所述栅极结构的所述第一切割段的第一侧壁和所述栅极结构的第二切割段的第二侧壁限定；开口的第二部分，具有第二宽度，所述开口的第二部分具有由所述介电层限定的边缘，并且其中，所述第一宽度大于所述第二宽度；以及开口的第三部分，在顶视图中设置在所述第一部分和所述第二部分之间；以及用所述介电材料填充所述开口。
在上述方法中，所述开口的第三部分包括以角度θ设置的侧壁，其中，所述角度θ相对于与所述栅极结构的侧壁平行的平面小于45度。
在上述方法中，所述蚀刻包括一系列沉积步骤和蚀刻步骤。
在上述方法中，一系列沉积步骤包括聚合物沉积步骤。
在上述方法中，一系列沉积步骤还包括沉积硅。
根据本发明的又一些实施例，还提供了一种制造半导体器件的方法，包括：将金属栅极结构切割成第一金属栅极段和共线的第二金属栅极段，其中，所述切割包括：实施第一工艺以沉积硅层；实施第二工艺以实施穿透蚀刻；实施所述金属栅极结构的功函金属层的蚀刻，其中，所述蚀刻可以包括高偏置和高占空比；实施聚合物沉积步骤；以及重复所述第一工艺、所述第二工艺、所述蚀刻和所述聚合物沉积步骤。
在上述方法中，所述高偏置包括大于1500瓦(W)的功率和大于60伏(V)的偏压。
在上述方法中，所述高占空比大于25％。
在上述方法中，所述切割在所述金属栅极结构和邻近的介电层中形成开口。
在上述方法中，所述金属栅极结构中的开口的宽度大于邻近的介电层中的开口的宽度，所述宽度在与包括所述金属栅极结构的半导体衬底的顶面平行的平面上测量。
在上述方法中，所述切割在所述金属栅极结构和下面的浅沟槽隔离(STI)部件中形成开口。
在上述方法中，所述金属栅极结构中的开口的第一宽度小于所述浅沟槽隔离部件中的开口的第二宽度，所述第一宽度和所述第二宽度的每个均可以在与所述金属栅极结构的长度平行的平面上测量，所述第一宽度限定在第二宽度之上的平面上。
在上述方法中，实施所述重复七次。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。
在示例性实施例中，半导体器件包括每个均从衬底延伸的第一鳍和第二鳍。第一栅极段设置在第一鳍上方，第二栅极段设置在第二鳍上方。层间介电(ILD)层邻近第一栅极段和第二栅极段。切割区域(例如，第一栅极结构和第二栅极结构之间的开口或间隙)在第一和第二栅极段之间延伸。切割区域具有第一部分和第二部分，第一部分具有第一宽度，第二部分具有第二宽度，第二宽度大于第一宽度。第二部分插入第一和第二栅极段，第一部分限定在ILD层内。
在进一步实施例中，切割区域的从第一部分延伸至第二部分的侧壁相对于与第一鳍的长度垂直定向并且与衬底的顶面垂直定向的平面设置为角度θ。在进一步实施例中，第一宽度和第二宽度从该区域的顶视图测量。在一些实施例中，用介电材料填充切割区域。在一些实施例中，切割区域延伸至第一鳍和第二鳍之间的浅沟槽隔离部件内。在进一步实施例中，切割区域在浅沟槽隔离部件的顶面处具有第三宽度，并且在第一栅极段和第二栅极段之间具有超越第三宽度的第二宽度。在平行于衬底的顶面的平面上测量第三宽度和第二宽度。在实施例中，第一栅极段具有第一基本线性侧壁，并且第二栅极段具有第二基本线性侧壁，其中，介电材料在第一和第二基本线性侧壁之间延伸。
在进一步实施例中，提供了制造半导体器件的方法。该方法包括形成从半导体衬底延伸的第一鳍和第二鳍，其中，浅沟槽隔离(STI)在第一和第二鳍之间延伸。形成在第一和第二鳍上方延伸的栅极结构。介电层邻近栅极结构设置。蚀刻栅极结构和介电层以在栅极结构中形成至少延伸至STI的顶面的开口。蚀刻提供具有第一宽度的开口的第一部分，第一部分可以由栅极结构的第一切割段的第一侧壁和栅极结构的第二切割段的第二侧壁限定。开口的第二部分具有第二宽度，开口的第二部分具有由介电层限定的边缘。第一宽度大于第二宽度。在顶视图中，开口的第三部分设置在第一部分和第二部分之间。用介电材料填充开口。
在一些进一步实施例中，开口的第三部分包括以角度θ设置的侧壁，其中，角度θ相对于与栅极结构的侧壁平行的平面小于45度。在一些实施例中，蚀刻包括一系列沉积步骤和蚀刻步骤。在一些实施例中，该系列沉积步骤包括聚合物沉积步骤。在一些实施例中，该系列沉积步骤还包括沉积硅。
在进一步实施例中，提供半导体器件制造的方法，其包括将金属栅极结构切割成第一金属栅极段和共线的第二金属栅极段。切割包括实施第一工艺以沉积硅层并且实施第二工艺以实施穿透蚀刻。该实施例可以包括实施金属栅极结构的功函金属层的蚀刻。蚀刻可以包括高偏置和高占空比。可以实施聚合物沉积步骤。重复第一工艺、第二工艺、蚀刻和聚合物沉积步骤。
在进一步实施例中，高偏置包括大于约1500瓦(W)的功率和大于约60伏(V)的偏压。在实施例中，高占空比大于约25％。在实施例中，切割在金属栅极结构和邻近的介电层中形成开口。在实施例中，金属栅极结构中的开口的宽度大于邻近介电层中的开口的宽度，该宽度在与包括金属栅极结构的半导体衬底的顶面平行的平面上测量。在进一步实施例中，切割在金属栅极结构和下面的浅沟槽隔离(STI)部件中形成开口。在进一步实施例中，金属栅极结构中的开口的第一宽度小于STI部件中的开口的第二宽度。可以在与金属栅极结构的长度平行的平面上测量第一宽度和第二宽度的每个，第一宽度限定在第二宽度之上的平面上。在实施例中，实施该重复七次。

Claims (20)

1.一种半导体器件，包括：
第一鳍和第二鳍，各自均从衬底延伸；
第一栅极段和第二栅极段，所述第一栅极段设置在所述第一鳍上方，所述第二栅极段设置在所述第二鳍上方；
层间介电(ILD)层，邻近所述第一栅极段和所述第二栅极段；以及
切割区域，在所述第一栅极段和所述第二栅极段之间延伸，其中，所述切割区域具有第一部分和第二部分，所述第一部分具有第一宽度，并且所述第二部分具有第二宽度，所述第二宽度大于所述第一宽度，并且其中，所述第二部分插入所述第一栅极段和所述第二栅极段，并且所述第一部分限定在所述层间介电层内。
2.根据权利要求1所述的半导体器件，其中，所述切割区域的从所述第一部分延伸至所述第二部分的侧壁相对于与所述第一鳍的长度垂直定向并且与所述衬底的顶面垂直定向的平面以角度θ设置。
3.根据权利要求1所述的半导体器件，其中，所述第一宽度和所述第二宽度从所述切割区域的顶视图测量。
4.根据权利要求1所述的半导体器件，其中，用介电材料填充所述切割区域。
5.根据权利要求1所述的半导体器件，其中，所述切割区域延伸至所述第一鳍和所述第二鳍之间的浅沟槽隔离部件内。
6.根据权利要求5所述的半导体器件，其中，所述切割区域在所述浅沟槽隔离部件的顶面处具有第三宽度，并且在所述第一栅极段和所述第二栅极段之间具有在所述第三宽度之上的所述第二宽度，其中，所述第三宽度和所述第二宽度在平行于所述衬底的顶面的平面上测量。
7.根据权利要求1所述的半导体器件，其中，所述第一栅极段具有第一线性侧壁，并且所述第二栅极段具有第二线性侧壁，其中，介电材料在所述第一线性侧壁和所述第二线性侧壁之间延伸。
8.一种制造半导体器件的方法，包括：
形成从半导体衬底延伸的第一鳍和第二鳍，其中，浅沟槽隔离件(STI)在所述第一鳍和所述第二鳍之间延伸；
形成在所述第一鳍和所述第二鳍上方延伸的栅极结构；
提供邻近所述栅极结构的介电层；
蚀刻所述栅极结构和所述介电层以在所述栅极结构中形成至少延伸至所述浅沟槽隔离件的顶面的开口，其中，所述蚀刻形成的所述开口具有：
开口的第一部分，具有第一宽度，所述第一部分由所述栅极结构的第一切割段的第一侧壁和所述栅极结构的第二切割段的第二侧壁限定；
开口的第二部分，具有第二宽度，所述开口的第二部分具有由所述介电层限定的边缘，并且其中，所述第一宽度大于所述第二宽度；以及
开口的第三部分，在顶视图中设置在所述第一部分和所述第二部分之间；以及
用介电材料填充所述开口。
9.根据权利要求8所述的方法，其中，所述开口的第三部分包括以角度θ设置的侧壁，其中，所述角度θ相对于与所述栅极结构的侧壁平行的平面小于45度。
10.根据权利要求8所述的方法，其中，所述蚀刻包括一系列沉积步骤和蚀刻步骤。
11.根据权利要求10所述的方法，其中，一系列沉积步骤包括聚合物沉积步骤。
12.根据权利要求11所述的方法，其中，一系列沉积步骤还包括沉积硅。
13.一种制造半导体器件的方法，包括：
将金属栅极结构切割成第一金属栅极段和共线的第二金属栅极段，其中，所述切割包括：
实施第一工艺以沉积硅层；
实施第二工艺以实施穿透蚀刻；
实施所述金属栅极结构的功函金属层的蚀刻，其中，所述蚀刻包括高偏置和高占空比；
实施聚合物沉积步骤；以及
重复所述第一工艺、所述第二工艺、所述蚀刻和所述聚合物沉积步骤，
其中，所述切割在所述金属栅极结构和邻近的介电层中形成开口，其中，所述金属栅极结构中的开口的宽度大于邻近的介电层中的开口的宽度，所述宽度在与包括所述金属栅极结构的半导体衬底的顶面平行的平面上测量。
14.根据权利要求13所述的方法，其中，所述高偏置包括大于1500瓦(W)的功率和大于60伏(V)的偏压。
15.根据权利要求13所述的方法，其中，所述高占空比大于25％。
16.根据权利要求13所述的方法，还包括，在所述切割之前，在所述金属栅极结构上方形成硬掩模层堆叠件，以及在所述硬掩模层堆叠件中形成第二开口。
17.根据权利要求16所述的方法，还包括，在形成所述第二开口之后，实施再沉积工艺。
18.根据权利要求13所述的方法，其中，所述切割在所述金属栅极结构和下面的浅沟槽隔离(STI)部件中形成第三开口。
19.根据权利要求18所述的方法，其中，所述金属栅极结构中的第三开口的第一宽度小于所述浅沟槽隔离部件中的第三开口的第二宽度，所述第一宽度和所述第二宽度的每个均在与所述金属栅极结构的长度平行的平面上测量，所述第一宽度限定在第二宽度之上的平面上。
20.根据权利要求13所述的方法，其中，实施所述重复七次。
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