TW201926685A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201926685A
TW201926685A TW107135763A TW107135763A TW201926685A TW 201926685 A TW201926685 A TW 201926685A TW 107135763 A TW107135763 A TW 107135763A TW 107135763 A TW107135763 A TW 107135763A TW 201926685 A TW201926685 A TW 201926685A
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layer
gate
drain region
semiconductor device
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TW107135763A
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TWI721325B (zh
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黃國長
盧富鵬
劉峻昌
黃鎮球
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台灣積體電路製造股份有限公司
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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Abstract

一種半導體裝置，包含具有通道區之基板、位於通道區上之閘極堆疊、覆蓋於閘極堆疊之側壁的密封間隔物，密封間隔物包含氮化矽、覆蓋於密封間隔物之側壁的閘極間隔物，閘極間隔物包含氧化矽，該閘極間隔物具有第一垂直部分以及第一水平部分，以及第一介電層覆蓋閘極間隔物之側壁，第一介電層包含氮化矽。

Description

半導體裝置及其製造方法
本揭露是關於一種半導體裝置元件及其製造方法，特別是有關於閘極間隔物結構以及閘極間隔物結構的製造方法。
半導體積體電路(integrated circuit,IC)產業歷經了指數性成長。IC材料和設計上之技術改良已產生許多IC世代，而每一世代比起前一世代又具有更小以及更複雜之電路。在IC的進化過程中，功能密度(即每單位晶片面積具有之內連接裝置數目)逐漸成長，而幾何大小(即以製程可生成之最小元件或配線)逐漸減小。此類微縮過程通常藉由提升生產效率以及降低成本來提供益處。該微縮亦會增加處理與製造IC之複雜度，為了使這些進展得以實現，於IC處理與製造領域，相似的發展是需要的。
舉例而言，一般希望減少在場效電晶體之元件間的寄生電容(stray capacitance)，例如：閘極結構與源/汲極接觸之間的電容，以增加開關速度、減少開關電源消耗、及/或減少電晶體的雜訊耦合。某些低介電常數材料是被建議作為包圍閘極結構之絕緣體，以提供較低的介電常數(或是相對電容率)與減少寄生電容。然而，隨著半導體科技進展至更小的幾 何尺寸，閘極結構與源/汲極接觸件間之距離進一步縮減，導致其仍然具有較大之寄生電容。因此，雖然現有的電晶體之製造方法在大致上合乎其預期目的，但並非在所有方面都完全令人滿意。
本揭露實施例提供一種半導體裝置，包含具有通道區之基板、位於通道區上之閘極堆疊、覆蓋於閘極堆疊之側壁的密封間隔物，密封間隔物包含氮化矽、覆蓋於密封間隔物之側壁的閘極間隔物，閘極間隔物包含氧化矽，閘極間隔物具有第一垂直部分以及第一水平部分，以及第一介電層覆於閘極間隔物之側壁，第一介電層包含氮化矽。
本揭露實施例提供另一種半導體裝置，包含基板，其具有源/汲極區與介於該源/汲極區之間之通道區、位於通道區之上的閘極堆疊、覆蓋於閘極堆疊側壁之介電層，介電層包含氮化物、覆蓋於介電層側壁之間隔物層。間隔物層包含一氧化物，間隔物層之側壁包含上側壁、水平表面與下側壁，藉此形成階梯輪廓；以及覆蓋於間隔物層側壁之接觸蝕刻停止層，接觸蝕刻停止層包含氮化物。
本揭露實施例提供了一種半導體裝置的製造方法，包含形成閘極結構於基板上、形成一覆蓋閘極結構之密封間隔物、藉由原子層沉積製程形成覆蓋密封間隔物之閘極間隔物，閘極間隔物具有第一垂直部分與第一水平部分。形成覆蓋閘極間隔物之硬遮罩層，硬遮罩層具有第二垂直部分與第二水平部分、移除硬遮罩層之第二水平部分以及位於硬遮罩層之第 二水平部分之下的閘極間隔物之第一水平部分；以及形成覆蓋閘極間隔物之接觸蝕刻停止層。
102、104、106、108、110、112、114、116、118、120、122、124、126‧‧‧步驟
200‧‧‧半導體裝置
202‧‧‧基板
208‧‧‧閘極堆疊
210‧‧‧界面層
212‧‧‧電極層
214‧‧‧密封間隔物層
214b、214a‧‧‧垂直部分、水平部分
215‧‧‧通道區
216‧‧‧輕摻雜源/汲極區
220‧‧‧閘極間隔物層
220a、220b‧‧‧垂直部分、水平部分
224‧‧‧硬遮罩層
225‧‧‧側壁
226‧‧‧頂面
228‧‧‧側壁
230‧‧‧重摻雜源/汲極區
231‧‧‧金屬矽化物
246‧‧‧接觸蝕刻停止層
252‧‧‧層間介電層
253‧‧‧虛線
290‧‧‧閘極堆疊
292‧‧‧介電層
294‧‧‧導電層
本案揭露之各面向可由以下之詳細說明並配合所附圖式來完整了解。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可能任意地放大或縮小元件的尺寸，以清楚地表現出本揭露的特徵。
第1A、1B、及1C圖係根據本案揭露之不同面向，繪示出形成半導體裝置的流程圖。
第2、3、4、5、6、7、8、9、10、11、12、13、14、15、16以及17圖係根據一些實施例，在製程期間根據第1A、1B、及1C圖之方法之部份半導體裝置的剖面示意圖。
以下的揭示內容提供許多不同的實施例或範例，以展示本揭露的不同部件。以下將揭示本說明書各部件及其排列方式之特定範例，用以簡化本揭露敘述。當然，這些特定範例並非用於限定本揭露。例如，若是本說明書以下的發明內容敘述了將形成第一部件於第二部件之上或上方，即表示其包括了所形成之第一及第二部件是直接接觸的實施例，亦包括了尚可將附加的部件形成於上述第一及第二部件之間，則第一及第二部件為未直接接觸的實施例。此外，本揭露說明中的各式範例可能使用重複的參照符號及/或用字。這些重複符號或用字的目的在於簡化與清晰，並非用以限定各式實施例及/或所述配置之間的關係。
此外，其與空間相關用詞，例如「在...下方」、「下方」、「下部」、「上方」、「上部」及諸如此類用語，係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包含使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
本揭露是關於半導體裝置及其形成方法。特別是，本揭露為關於在半導體製程中提供用於降低場效電晶體(field-effect transistor，FETs)之閘極結構與源/汲極接觸件間寄生電阻的低介電常數閘極間隔物結構以及形成方法。當形成場效電晶體時，期望提高開關速度、降低開關功率損耗以及降低耦合雜訊(coupling noise)。寄生電阻通常對於這些參數具有負面影響，特別是透過閘極結構與源/汲極接觸件間之寄生電阻。隨著半導體科技進展至更小的幾何尺寸，閘極結構與源/汲極接觸件間之距離進一步縮減，導致其仍然具有較大之寄生電容。因此，FET中之寄生電阻問題越發嚴重。本揭露提供形成環繞閘極堆疊(例如多晶矽閘極或是金屬閘極)之低介電常數閘極間隔物結構。相較於傳統上由氮化矽(例如，Si3N4)所形成之閘極間隔物，低介電常數閘極間隔物結構降低了閘極與源/汲極接觸件間的介電常數(或是相對電容率(relative permittivity))，從而降低其寄生電容。此外，低介電常數閘極間隔物結構有助於降低閘極堆疊與源/汲極區之間的界面應力，且因此提高了通道載子遷移率(channel carrier mobility)。
第1A、1B、1C圖係根據本揭露繪示出用於形成半導體裝置之方法100的流程圖。方法100僅為範例，且並非用以對本揭露作出超過請求項清楚記載的限制。於方法100之前、期間或之後可提供額外之操作步驟，且對於方法的額外實施例，可替換、刪除、或重置一些所描述的操作。方法100將於下文中搭配第2至16圖進行說明，所述圖式繪示出根據方法100之一些實施例，於不同製程步驟中之半導體裝置200的剖面示意圖。
裝置200可為於積體電路(integrated circuit,IC)製程期間、或是其中一部分之中間裝置，上述IC可包含靜態隨機存取記憶體(static random-access memory，SRAM)、及/或邏輯電路、被動組件，如：電阻器、電容器、電感器，以及主動組件，如：P型FET、N型FET、鰭式場效電晶體、MOSFET互補式金屬氧化物半導體(complementary metal-oxide-semiconductor,CMOS)電晶體、雙極式電晶體、高壓電晶體、高頻電晶體、其他儲存單元、以及上述之組合。此外，於本揭露的多個實施例中所提供各種部件包含電晶體、閘極堆疊、主動區、隔離結構、以及其他部件，是用以簡化以及便於了解，並非是限制實施例於任何類型之裝置、任何數量之裝置、任何數量之區域、或是任何配置之結構或區域。
於步驟102，方法100(參見第1A圖)提供一裝置結構200(參見第2圖)。為方便討論，裝置結構200亦被稱作裝置200。裝置200可包含基板202以及各種形成於其中或其上之部件。基板202於所述的實施例中是矽基板。或者，基板202可包含其他 元素半導體，例如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或上述之組合。在其他選擇中，基板202是絕緣體上覆半導體(semiconductor on insulator,SOI)。在一些實施例中，基板202包含多個鰭狀半導體區(複數鰭片)以形成鰭式場效電晶體。可藉由任何合適的方法圖案化複數鰭片。舉例而言，可使用一個或多個光微影製程圖案化複數鰭片，包含雙重曝光(double-patterning)或多重曝光(multi-patterning)製程。一般而言，雙重曝光或多重曝光製程結合光微影與自我對準(self-aligned)製程，可使產生的圖案相較於使用一次、直接曝光所得的具有較小之節距(pitch)。例如，在一實施例中，一犧牲層形成於基板202之上並經光微影製程進行圖案化。複數間隔藉由自對準製程，沿著圖案化後之犧牲層形成。其後，犧牲層將被移除，剩下之複數間隔或心軸(mandrels)可用於圖案化基板202以形成複數鰭片。在某些實施例中，複數鰭片可包含一或多層磊晶成長之半導體材料。
在一些實施例中，基板202包含可由氧化矽、氮化矽、氮氧化矽、摻氟矽玻璃(fluoride-doped silicate glass,FSG)、低介電常數介電材料及/或其他合適絕緣材料所形成之絕緣體(或是隔離結構)。絕緣體可為淺溝槽隔離(shallow trench isolation,STI)部件。在一實施例中，絕緣體藉由在基板202中蝕刻出溝槽(例如前述形成鰭片的部份製程)，以絕緣材料填充該溝槽，並對包含絕緣材料之基板202進行化學機械平坦化 (chemical mechanical planarization,CMP)製程。基板202可包含其他隔離結構，例如場氧化層與矽的局部氧化(LOCal Oxidation of Silicon,LOCOS)。基板202可包含多層隔離結構。
於步驟104，方法100(參照第1A圖)形成閘極堆疊208於基板202之上(參照第2圖)。在不同實施例中，閘極堆疊208為多層結構。在一些實施例中，閘極堆疊208為多晶矽閘極結構，包含具有氧化矽(silicon oxide)或氮氧化矽(oxynitride)之界面層210以及具有多晶矽之電極層212。據此，於一些實施例中，形成閘極堆疊208包含藉由化學氧化(chemical oxidation)、熱氧化(thermal oxidation)、原子層沉積(atomic layer deposition,ALD)、化學氣相沉積(chemical vapor deposition,CVD)、或其他合適方法沉積界面層210於基板202之上；藉由低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)、或其他合適方法沉積電極層212於界面層210之上；其後，於光微影製程中圖案化界面層210與電極層212形成閘極堆疊208。於基板202或基板202之鰭片中，閘極堆疊208定義出其下的通道區215。於所述的實施例中，通道區215具有通道長度D，範圍從約5奈米至約180奈米。
在一特定的實施例中，方法100包含替換閘極(replacement gate)製程，其將於之後進一步說明。於替換閘極製程，閘極堆疊208是一暫時閘極結構。界面層210可為具有氧化矽或氮氧化矽的暫時界面層，而電極層212可為具有多晶矽的暫時電極層。
步驟104可進一步包含形成覆蓋裝置200的密封間 隔物層214。在所述的實施例中，該密封間隔物層214作為毯覆層(blanket layer)沉積於閘極堆疊208的頂部與側壁以及基板202的上表面之上。進一步說明所述實施例，密封間隔物層214包含氮化矽(如：Si3N4)，並可藉由電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)、LPCVD、ALD、或其他合適方法來沉積。密封間隔物層214之沉積厚度可為約0.5奈米至約10奈米，例如約3奈米。
於步驟106，方法100(參照第2圖)對密封間隔物層214施加非等向性蝕刻製程(參照第3圖)。非等向性蝕刻製程設計為選擇性地蝕刻密封間隔物層214而不會蝕刻基板202。步驟106從基板202之表面移除部分密封間隔物層214，從而露出基板202之表面。由於高方向性蝕刻的緣故，閘極堆疊208側壁上的部分密封間隔物層214大致上保持未蝕刻。另外，藉由此非等向性蝕刻製程可以或可以不暴露閘極堆疊208的頂面。在密封間隔物層214包含氮化矽的實施例中，步驟106可採用帶有含氟氣體(如CF4、NF3或SF6)的遠程O2/N2離子放電(remote O2/N2 discharge)，且可額外地包含氫氣或甲烷。亦可使用其他不同選擇性蝕刻密封間隔物層214的方法。為求簡潔，圖案化後的密封間隔物層214可表示為密封間隔物214。在一特定實施例中，密封間隔物214與閘極堆疊208之側壁共形(conformal)，且在靠近該閘極堆疊208底部具有錐形輪廓(tapering profile)。因此，由於錐形輪廓，密封間隔物214可視為是包含水平部分214a與垂直部分214b。水平部分214a連接垂直部分214b之底部，並且朝遠離閘極堆疊208的方向橫向延伸。水平部分214a可具有 沿著X軸之寬度，範圍約0.5奈米至5奈米，例如約3奈米。
於步驟108，方法100(參見第1圖)藉由進行離子佈植製程218(參見第4圖)於基板202中形成輕摻雜源/汲極區216(lightly doped source/drain region,LDD)。離子佈植製程218可使用N型摻質，如磷或砷，以形成NFET；或是使用P型摻質，如硼或銦，以形成PFET。輕摻雜源/汲極區216與閘極堆疊208和密封間隔物214自對準(self-aligned)。當輕摻雜源/汲極區216經受離子佈植製程218時，可使用遮罩層(未繪示)覆蓋基板202之其他區域。在一些實施例中，遮罩層為圖案化光阻。在一些實施例中，遮罩層為一材料之圖案化硬遮罩，例如氧化矽、氮化矽、氮氧化矽或是以上之組合。在輕摻雜源/汲極區216完成輕摻雜佈植後，移除遮罩層。於第4圖中所示的實施例中，步驟108在步驟106後執行。在另一實施例中，步驟108於步驟106前執行。
於步驟110，方法100(參照第1圖)形成覆蓋裝置200的閘極間隔物層220(參照第5圖)。在所述的實施例中，閘極間隔物層220作為毯覆層沉積於密封間隔物214側壁、閘極堆疊208頂部以及基板202上表面之上。在一些裝置中，氮化矽於半導體製程中一直作為閘極間隔物材料。然而，氮化矽具有相對高之介電常數，通常位於範圍6.8至8.3之間，例如約7.5，而這導致在閘極堆疊與源/汲極接觸件之間或/及在某些情況下與其他FET元件之間具有高寄生電容。為降低寄生電容，使用非氮化矽之低介電常數材料作為閘極間隔物是有其需求的。在一實施例中，閘極間隔物層220包含氧化矽(例如，SiO2)。相較於氮 化矽，氧化矽具有較低之介電常數，通常範圍為3.4至4.2，例如約3.9。在一些實施例中，閘極間隔物層220的沉積包含引入含矽化合物與含氧化合物，兩者反應生成介電材料。閘極間隔物層220可包含未摻雜之矽酸鹽玻璃(undoped silicate glass，USG)、摻氟之矽酸鹽玻璃(FSG)、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、或是硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)。在另一實施例中，閘極間隔物層220包含氧化鍺，例如GeO2。閘極間隔物層220可藉任何合適的技術形成，包含PECVD、LPCVD與ALD。於所述的實施例中，閘極間隔物層220包含二氧化矽，並藉由共形沉積技術進行沉積，例如ALD製程。閘極間隔物層220可沉積至具有厚度T1，其為通道區215之長度D的約10%至約70%。在一些實施例中，厚度T1於約3奈米至約20奈米左右之範圍內，例如約5奈米。
於步驟112，方法100(參見第1圖)形成覆蓋閘極間隔物層220之硬遮罩層224(參照第6圖)。硬遮罩層224可包含介電材料，例如氮化矽、氧化矽、氮氧化矽(silicon oxynitride)、碳氮化矽(silicon carbonitride)、氮氧化碳矽(silicon carbon oxynitride)、其他介電材料或以上之組合。藉由選擇硬遮罩層224之組成，使硬遮罩層224相對於閘極間隔物層220具有一些蝕刻選擇性。在一些實施例中，硬遮罩層224包含氮化矽(如Si3N4)。硬遮罩層224可藉由任何合適的技術形成，例如PECVD、LPCVD與ALD。在所述的實施例中，藉由LPCVD製程沉積硬遮罩層224。硬遮罩層224可沉積至厚度T2，其為通道區 215之長度D的約10%至約70%左右。在一些實施例中，厚度T2於約3奈米至約20奈米之範圍內，例如約4奈米。在一些實施例中，硬遮罩層224較閘極間隔物層220薄(T2<T1)，例如：至多較閘極間隔物層220薄約1奈米。
於步驟114，方法100(參見第1圖)對硬遮罩層224以及閘極間隔物層220施加蝕刻製程(參見第7圖)。在一實施例中，蝕刻製程包含非等向性蝕刻。由於高方向性蝕刻的緣故，於閘極間隔物層220側壁上之部分硬遮罩層224大致上保持未蝕刻，如第7圖所示。在硬遮罩層224包含氮化矽的實施例中，步驟114可採用帶有含氟氣體(如CF4、NF3或SF6)的遠程O2/N2離子放電，且可額外地包含氫氣或甲烷。非等向性蝕刻可進一步蝕刻在移去部分硬遮罩層224後露出的閘極間隔物層220。或者，蝕刻製程可包含使用不同蝕刻化學性質的多次蝕刻步驟，例如針對硬遮罩層224的特定材料之非等向性蝕刻，以及其後使用未蝕刻硬遮罩層224作為蝕刻遮罩，針對閘極間隔物層220之濕式或乾式蝕刻。藉由此蝕刻製程可以或可以不暴露閘極堆疊208之頂面。
仍然參照第7圖，為求簡潔，圖案化閘極間隔物層220可表示為閘極間隔物220，而圖案化硬遮罩層224可表示為硬遮罩224。閘極間隔物220包含水平部分220a，其直接位於硬遮罩224下方，以及垂直部分220b，其覆蓋密封間隔物214之側壁。垂直部分220b包含側壁225。側壁225被硬遮罩224覆蓋。在一些實施例中，側壁225大致上與基板202之頂面垂直(亦即沿著Z軸方向)。水平部分220a包含頂面226以及側壁228。側壁 228可大致上與基板202之頂面垂直(亦即沿著Z軸方向)。側壁225、頂面226以及側壁228形成階梯輪廓。硬遮罩224直接設置於頂面226上方。在一實施例中，硬遮罩224完全覆蓋頂面226。在另一實施例中，由於在步驟114硬遮罩224之較高的側壁蝕刻損失，硬遮罩224較水平部分220a之寬度W 1 薄(T 2 <W 1 )。因此，鄰近側壁228之部分頂面226被露出，其可沿X軸的方向具有約0.5奈米至約2奈米的寬度。頂面226與側壁225相交，於頂面226和側壁225之間形成θ角。在一些實施例中，θ角之範圍為約85度至95度，且頂面226可被視為大致上與側壁225垂直。在不同的實施例中，水平部分220a之高度H1與通道區215之長度D之比例約為10%至約70%。在一特定實施例中，高度H 1 與垂直部分220b之厚度T 1 相同(H 1 =T 1 )。在一實施例中，高度H 1 與垂直部分220b之厚度T 1 並不相同(H 1 ≠T 1 )，例如H 1 較厚度T 1 多或少1奈米。水平部分220a之最高點可較密封間隔物214的水平部分214a之最高點高。
於步驟118，方法100(參照第1B圖)形成重摻雜源/汲極區(heavily doped source/drain(HDD)region)230於基板202中(參照第8圖)。重摻雜源/汲極區230可為N型摻雜區及/或P型摻雜區以形成主動區。重摻雜源/汲極區230與輕摻雜源/汲極區216共同地視為源/汲極區(S/D region)。重摻雜源/汲極區230較輕摻雜源/汲極區216具有更高之摻雜濃度。重摻雜源/汲極區230可藉離子佈植製程232形成。離子佈植製程232可使用N型摻質，如磷或砷，以形成NFET，或是使用P型摻質，如硼或銦，以形成PFET。重摻雜源/汲極區230與閘極堆疊208以及閘極間 隔物220自對準。當重摻雜源/汲極區230經受離子佈植製程232時，可使用遮罩層(未繪示)覆蓋基板202之其他區域。在一些實施例中，遮罩層為圖案化光阻。在一些實施例中，遮罩層為一些材料之圖案化硬遮罩，例如氧化矽、氮化矽、氮氧化矽或是以上之組合。在重摻雜源/汲極區230完成重摻雜佈植後，移除遮罩層。
重摻雜源/汲極區230之形成亦可包含於基板202中的第一蝕刻源/汲極區凹槽，其後磊晶成長重摻雜源/汲極區230於對應之凹槽中。在一些閘極堆疊208與閘極間隔物220厚於預期之實施例中，可形成大致上具有鑽石型輪廓之重摻雜源/汲極區230，如第9圖所示之重摻雜源/汲極區230。參照第9圖，重摻雜源/汲極區230之一些側壁於閘極間隔物220之下，朝閘極堆疊208延伸，例如於垂直部分220b之下。在一實施例中，重摻雜源/汲極區230於密封間隔物214的水平部分214a之下進一步延伸，但非於垂直部分214b之下。在其他實施例中，重摻雜源/汲極區230在閘極堆疊208之下進一步延伸。在一範例中，以蝕刻製程形成源/汲極區凹槽，其包含乾式與濕式蝕刻，其中蝕刻製程之蝕刻參數(例如使用之蝕刻劑、蝕刻溫度、蝕刻溶液濃度、蝕刻壓力、蝕刻源功率、射頻偏壓(radio frequency bias voltage)、射頻偏功率、蝕刻劑流速、以及其他合適參數。)經調整以達到預期之凹槽形狀。重摻雜源/汲極區230可包含於其頂面上之金屬矽化物(silicide)231。部分金屬矽化物231可被閘極間隔物220之水平部分220a及/或垂直部分220b覆蓋。由於矽化物部231(又稱金屬矽化物231)的提升的高度，水平部分 220a之底面可能較垂直部分220b之底面高。為方便討論，將使用具有如第8圖所示之重摻雜源/汲極區形狀的裝置200作為後續步驟的範例。本領域具有通常知識者應了解具有如第9圖所示之重摻雜源/汲極區形狀的裝置200亦可用於後續步驟。
回頭參見第8圖，在一實施例中，重摻雜源/汲極區230進一步包含矽化(silicidation)或矽鍺化(germanosilicidation)(未繪示)。舉例而言，矽化物可由包含沉積金屬層、退火金屬層，藉此使金屬層與矽反應形成矽化物且接著移除未反應金屬層之製程形成。步驟118可進一步包含一或多個退火製程以活化源/汲極區。活化後，輕摻雜源/汲極區216可於密封間隔物214之下朝閘極堆疊208延伸，而重摻雜源/汲極區230可延伸至部分閘極間隔物220的水平部分220a之下。換言之，密封間隔物214和閘極間隔物220的垂直部分220b可與輕摻雜源/汲極區216物理接觸，而閘極間隔物220的水平部分220a可與輕摻雜源/汲極區216以及重摻雜源/汲極區230雙方物理接觸。閘極間隔物220材料組成之低介電常數亦能幫助減低閘極堆疊與源/汲極區間之界面應力，因而增加通道載子遷移率。在一實施例中，裝置200包含鰭狀主動區以形成、多閘極FET，例如FinFET。更進一步，源/汲極區與通道區215可形成於鰭片之中或之上。通道區215位於閘極堆疊208之下並介入一對輕摻雜區216之間。當裝置200開啟時，通道區215於相應源/汲極區之間導通電流，例如藉由偏壓閘極電極層212。
於步驟120，方法100(參見第1B圖)形成覆蓋裝置200之接觸蝕刻停止層246(參見第10圖)。在所述的實施例中， 接觸蝕刻停止層246作為毯覆層沉積於閘極間隔物220、硬遮罩224、密封間隔物214、閘極堆疊208之側壁與頂部以及於重摻雜源/汲極區230頂面之上。接觸蝕刻停止層246可包含一介電材料，如氮化矽、氧化矽、氮氧化矽、碳氮化矽、氮氧化碳矽、其他介電材料或以上之組合。接觸蝕刻停止層246可由電漿增強化學氣相沉積(plasma-enhanced CVD，PECVD)製程及/或其他合適沉積或氧化製程形成。在所述的實施例中，硬遮罩224以及蝕刻停止層246皆包含氮化矽(例如Si3N4)，而硬遮罩224由LPCVD形成、接觸蝕刻停止層246由PECVD形成，因此於硬遮罩224以及接觸蝕刻停止層246中之氮化矽材料具有不同的晶體結構。在一特定的實施例中，由於水平部分220a與在接觸蝕刻停止層246之下的硬遮罩224的側壁輪廓，接觸蝕刻停止層246沿著其垂直側壁具有階梯輪廓248。
於步驟122，方法100(參見第1B圖)於蝕刻終止層上形成層間介電層(inter-layer dielectric layer)252。層間介電層252可包含氧化矽、摻雜氧化矽，如硼磷矽玻璃(borophosphosilicate glass)、四乙氧基矽烷(tetraethylorthosilicate)、未摻雜矽玻璃、熔融矽玻璃(fused silica glass)、磷矽酸鹽玻璃、摻硼矽玻璃、低介電常數介電材料及/或其他合適介電材料。層間介電層222可藉PECVD、流動式CVD、或其他合適之沉積技術形成。接觸蝕刻停止層246以及層間介電層252藉由選擇其組成，使接觸蝕刻停止層246相對於層間介電層252具有一些之蝕刻選擇性。
於步驟124，方法100(參見第1B圖)進行一或多個化 學機械平坦化製程以拋光層間介電層252並使閘極堆疊208露出(參見第12圖)。在一些實施例中，相較於閘極堆疊208，層間介電層252於平坦化期間具有較多的表面損失，例如由於相對較低的材料密度，且層間介電層252之頂面具有凹陷輪廓，如圖中點線253所示。層間介電層252之頂面的最底部可能低於閘極堆疊208之頂面約0.1奈米至25奈米之間。
於步驟126，方法100(參見第1B圖)進行後續製程以完成裝置200之製造。舉例而言，方法100在閘極置換製程中可形成金屬閘極堆疊。
在閘極置換製程中，閘極堆疊208為暫時閘極結構。暫時閘極結構可由沉積以及蝕刻製程形成。其後，步驟126移除暫時閘極結構以形成閘極溝槽(未繪示)於密封間隔物214之間，並沉積高介電常數金屬閘極堆疊290於閘極溝槽中(參見第13圖)。高介電常數金屬閘極堆疊290可包含高介電常數介電層292以及其上之導電層294。高介電常數金屬閘極堆疊290可進一步包含界面層(例如SiO2，此處並未繪出)於高介電常數介電層292與通道區215之間。界面層可藉由使用化學氧化、熱氧化、ALD、CVD及/或其他合適之方法形成。
高介電常數介電層292可包含一個或多個高介電常數介電材料(或是一層或多層高介電常數介電材料)，例如氧化矽鉿(HfSiO)、二氧化鉿(HfO2)、氧化鋁(Al2O3)、氧化鋯(ZrO2)、氧化鑭(La2O3)、氧化鈦(TiO2)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3)、或上述之組合。高介電常數介電層292可藉由使用CVD、ALD及/或其他合適之方法沉積而成。
導電層294可包含一個或多個金屬層，例如功函數金屬層、導電阻障層、以及金屬填充層。根據電晶體之型態(P型或N型)，功函數金屬層可為P型或N型功函數層。P型功函數層包含選擇自但不限於由氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、鎢(W)、鉑(Pt)、或上述之組合所組成之群組的金屬。N型功函數層包含選擇自但不限於由鈦(Ti)、鋁(Al)、碳化鉭(TaC)、氰化鉭(TaCN)、氮矽化鉭(TaSiN)、氮矽化鈦(TiSiN)、或上述之組合所組成之群組的金屬。金屬填充層可包含鋁(Al)、鎢(W)、鈷(Co)及/或其他合適之材料。導電層294可藉由使用CVD、PVD、電鍍及/或其他合適方法沉積。
步驟126可包含其他製程以完成裝置200之製造。例如，步驟126可形成源/汲極接觸件(未繪示)以及形成多層內連線結構，多層內連線結構將閘極堆疊與源/汲極接觸件與裝置200的其他部分連接，以形成完整的積體電路。
方法100可以有多種實施利。例如，方法100於步驟114與步驟118之間可有選擇性步驟116(參見第1C圖)，以從閘極間隔物220的側壁移除硬遮罩224，如第14圖所示。在所述的實施例中，硬遮罩224包含氮化矽，其具有較閘極間隔物220之材料組成更高之介電常數。藉由移除硬遮罩224，閘極堆疊208與源/汲極接觸件(未繪示)之間之隔離材料整體的介電常數進一步降低，使FET部件之間具有更低之寄生電容。
硬遮罩224之移除可包含任何合適的蝕刻技術，例如濕式蝕刻、乾式蝕刻、RIE、灰化(ashing)及/或其他蝕刻製程。在一些實施例中，選擇蝕刻劑以使硬遮罩224與閘極間隔 物220具有高蝕刻選擇性。舉例而言，硬遮罩224與閘極間隔物220間之蝕刻選擇性的比例為5：1或更高，例如於5：1至20：1的範圍。蝕刻製程亦可修正閘極間隔物220之水平部分220a的輪廓。在一實施例中，頂面226縮減至通道區215之寬度D的約3%至約30%，例如約1奈米至8奈米(如2奈米)，且側壁228成為錐狀並相對於側壁225具有小於45度的β角，例如約20度。方法100可接著進行至如前述之步驟118、120、122、124與126，以形成裝置200的其他部件，包含以經修正之閘極間隔物220作為遮罩，形成重摻雜區230、直接沉積接觸蝕刻停止層246於修飾過之閘極間隔物220之側壁上、以及形成層間介電層252於裝置200之上，如第15圖所示。另一實施例中，步驟116(參見第1C圖)修正掉水平部分220a之頂面226，使側壁228直接與側壁225以小於45度的β角相交(如約20度)，如第16圖所示。方法100可接著進行至步驟118、120、122、124以及126，以形成裝置200的其他部件，如第17圖所示，為求簡潔於此將不再贅述。
本揭露內容之一個或多個實施例對半導體裝置以及其形成方法提供許多優點，包含鰭式場效電晶體(FinFET)，但並非用以進行限制。舉例而言，鰭片可被圖案化以在部件間產生相對接近的間距，而前述之揭露是適用的。用於形成FinFET鰭片之閘極間隔物可根據前述揭露進行。例如，本揭露之實施例提供形成環繞閘極堆疊之低介電常數閘極間隔物的方法。於閘極堆疊與源/汲極接觸件間之隔離材料的介電常數被降低了，其減少了內連線間之干擾、雜訊與寄生耦合電容。此外，低介電常數閘極間隔物結構幫助減低閘極堆疊與 源/汲極區間之界面應力，因此提高了通道載子的遷移率。此外，所揭露之方法可簡單地整合至現有半導體製程當中。
在一例示面向中，本揭露所指為半導體裝置。在一實施例中，半導體裝置包含具有通道區之基板、位於通道區上之閘極堆疊、覆蓋於閘極堆疊之側壁的密封間隔物，密封間隔物包含氮化矽、覆蓋於密封間隔物之側壁的閘極間隔物，閘極間隔物包含氧化矽，閘極間隔物具有第一垂直部分以及第一水平部分，以及第一介電層覆於閘極間隔物之側壁，第一介電層包含氮化矽。在一實施例中，密封間隔物包含第二垂直部分與第二水平部分，以及第一介電層包含第三垂直部分與第三水平部分。在一實施例中，各第一、第二、以及第三水平部分與基板之頂面形成物理接觸。在一實施例中，第二水平部分之最高點，低於第一水平部分之最高點。在一實施例中，基板具有源/汲極區域，源/汲極區域具有鄰近於通道區之第一摻雜源/汲極區、鄰近於第一摻雜源/汲極區之第二摻雜源/汲極區，其中第二摻雜源/汲極區相較於第一摻雜源/汲極區具有較高之摻雜濃度、第一垂直部分偏離第二摻雜源/汲極區而與第一摻雜源/汲極區物理接觸、以及第一水平部分與第一摻雜源/汲極區以及第二摻雜源/汲極區皆物理接觸。在一實施例中，第一水平部分之高度大抵與第一垂直部分之寬度相同。在一實施例中，第一垂直部分具有第一側壁，第一側壁大抵與基板之頂面垂直，以及第一水平部分具有第二側壁，第二側壁與第一側壁之交角小於45度。在一實施例中，第一垂直部分具有第一側壁，第一側壁大抵與基板之頂面垂直，以及第一水平部分具有 一第二側壁，以及位於第一側壁與第二側壁之間的第一頂面，第一頂面大抵垂直於第一側壁。在一實施例中，半導體裝置進一步包含第二介電層，其介於閘極間隔物與第一介電層之間，第二介電層於第一水平部分之上，第二介電層與閘極間隔物具有不同材料組成。在一實施例中，第二介電層覆蓋部分第一頂面。在一實施例中，第二側壁為大抵垂直於基板的頂面。在一實施例中，閘極堆疊包含多晶矽閘極或是金屬閘極。
在另一例示面向中，本揭露所指為一種半導體裝置。在一實施例中，半導體裝置包含基板，其具有源/汲極區與介於源/汲極區之間之通道區、位於通道區之上的閘極堆疊、覆蓋於閘極堆疊側壁之介電層，介電層包含氮化物、覆蓋於介電層側壁之間隔物層，間隔物層包含一氧化物，其中間隔物層之側壁包含上側壁、水平表面與下側壁，並藉此形成階梯輪廓；以及覆蓋於間隔物層之側壁之接觸蝕刻停止層，接觸蝕刻停止層包含氮化物。在一實施例中，上側壁與水平表面相交，定義出一介於上側壁與水平表面之交角，交角之範圍為85度至95度。在一實施例中，半導體裝置進一步包含位於間隔物層與接觸蝕刻停止層之間的硬遮罩層，硬遮罩層之介電常數高於間隔物層之介電常數。在一實施例中，源/汲極區包含第一摻雜源/汲極區以及較第一摻雜源/汲極區更高摻雜濃度之第二摻雜源/汲極區，其中上側壁直接位於第一摻雜源/汲極區之上，而下側壁直接位於第二摻雜源/汲極區之上。在一實施例中，間隔物層之厚度為通道區長度的10%至70%。
在另一例示面向中，本揭露所指為一種半導體裝 置的製造方法。在一實施例中，該方法包含形成閘極結構於基板上、形成一覆蓋閘極結構之密封間隔物、藉由原子層沉積製程形成覆蓋密封間隔物之閘極間隔物，閘極間隔物具有第一垂直部分與第一水平部分、形成覆蓋閘極間隔物之硬遮罩層，硬遮罩層具有第二垂直部分與第二水平部分、移除硬遮罩層之第二水平部分以及部分閘極間隔物之第一水平部分，第一水平部分位於硬遮罩層之第二水平部分之下；以及形成覆蓋閘極間隔物之接觸蝕刻停止層。在一實施例中，方法進一步包含在形成接觸蝕刻停止層前，移除硬遮罩層之第二垂直部分。在一實施例中，閘極間隔物於密封間隔物、閘極間隔物、硬遮罩層以及接觸蝕刻停止層之群組中，具有最低之介電常數。在一實施例中，密封間隔物包含氮化矽、閘極間隔物包含氧化矽、接觸蝕刻停止層包含氮化矽。在一實施例中，該方法進一步包含在形成密封間隔物後與在形成閘極間隔物前，藉由離子佈植製程形成第一源/汲極區、以及在移除硬遮罩層的第二水平部分後與形成接觸蝕刻停止層前，形成鄰近於第一源/汲極區的第二源/汲極區，其中第二源/汲極區相較於第一源/汲極區具有較高之摻雜濃度。在一實施例中，閘極結構為多晶矽閘極結構或金屬閘極結構。
以上概略說明了本揭露數個實施例的特徵，使所屬技術領域內具有通常知識者對於本揭露可更為容易理解。任何所屬技術領域內具有通常知識者應瞭解到本說明書可輕易作為其他結構或製程的變更或設計基礎，以進行相同於本揭露實施例的目的及/或獲得相同的優點。任何所屬技術領域內具 有通常知識者亦可理解與上述等同的結構或製程並未脫離本揭露之精神及保護範圍內，且可在不脫離本揭露之精神及範圍內，當可作更動、替代與潤飾。

Claims (20)

  1. 一種半導體裝置，包含：一基板，具有一通道區；一閘極堆疊，位於該通道區上；一密封間隔物，覆蓋於該閘極堆疊之一側壁，該密封間隔物包含氮化矽；一閘極間隔物覆蓋於該密封間隔物之一側壁，該閘極間隔物包含氧化矽，該閘極間隔物具有一第一垂直部分以及一第一水平部分；以及一第一介電層，覆蓋於該閘極間隔物之一側壁，該第一介電層包含氮化矽。
  2. 如申請專利範圍第1項所述之半導體裝置，其中：該密封間隔物包含一第二垂直部分與一第二水平部分；以及該第一介電層包含一第三垂直部分與一第三水平部分。
  3. 如申請專利範圍第2項所述之半導體裝置，其中該第一、第二、以及第三水平部分各與該基板之頂面形成物理接觸。
  4. 如申請專利範圍第2項所述之半導體裝置，其中該第二水平部分之一最高點，低於該第一水平部分之一最高點。
  5. 如申請專利範圍第1項所述之半導體裝置，其中：該基板具有一源/汲極區域，該源/汲極區域具有一鄰近於通道區之第一摻雜源/汲極區；一鄰近於該第一摻雜源/汲極區之第二摻雜源/汲極區，其中該第二摻雜源/汲極區相較於該第一摻雜源/汲極區具有較高之摻雜濃度； 該第一垂直部分偏離該第二摻雜源/汲極區且與該第一摻雜源/汲極區物理接觸；以及該第一水平部分與該第一摻雜源/汲極區以及該第二摻雜源/汲極區皆物理接觸。
  6. 如申請專利範圍第1項所述之半導體裝置，其中該第一水平部分之高度大抵與該第一垂直部分之寬度相同。
  7. 如申請專利範圍第1項所述之半導體裝置，其中：該第一垂直部分具有一第一側壁，該第一側壁大抵與該基板之頂面垂直；以及該第一水平部分具有一第二側壁，該第二側壁與該第一側壁之交角小於45度。
  8. 如申請專利範圍第1項所述之半導體裝置，其中：該第一垂直部分具有第一側壁，該第一側壁大抵與該基板之頂面垂直；以及該第一水平部分具有一第二側壁，以及一位於該第一側壁與該第二側壁之間的一第一頂面，該第一頂面大抵垂直於該第一側壁。
  9. 如申請專利範圍第8項所述之半導體裝置，更包含：一第二介電層，其介於該閘極間隔物與該第一介電層之間，該第二介電層於該第一水平部分之上，該第二介電層與該閘極間隔物具有不同材料組成。
  10. 如申請專利範圍第9項所述之半導體裝置，其中該第二介電層覆蓋部分該第一頂面。
  11. 如申請專利範圍第9項所述之半導體裝置，其中該第二側壁 為大抵垂直於該基板的一頂面。
  12. 如申請專利範圍第1項所述之半導體裝置，其中該閘極堆疊包含一多晶矽閘極或是一金屬閘極。
  13. 一種半導體裝置，包含：一基板，其具有源/汲極區與介於該源/汲極區之間之一通道區；一閘極堆疊，位於該通道區之上；一介電層，覆蓋於該閘極堆疊側壁，該介電層包含一氮化物；一間隔物層，覆蓋於該介電層側壁，該間隔物層包含一氧化物，其中該間隔物層之一側壁包含一上側壁、一水平表面與一下側壁，藉此形成一階梯輪廓；以及一覆蓋於該間隔物層之側壁之接觸蝕刻停止層，該接觸蝕刻停止層包含一氮化物。
  14. 如專利申請範圍第13項所述之半導體裝置，其中該上側壁與該水平表面相交，定義出一介於該上側壁與該水平表面之交角，該交角之範圍為85度至95度。
  15. 如專利申請範圍第13項所述之半導體裝置，更包含：一位於該間隔物層與該接觸蝕刻停止層之間的硬遮罩層，該硬遮罩層之介電常數高於該間隔物層之介電常數。
  16. 如專利申請範圍第13項所述之半導體裝置，其中該源/汲極區包含一第一摻雜源/汲極區以及一較該第一摻雜源/汲極區更高摻雜濃度之第二摻雜源/汲極區，其中該上側壁直接位於該第一摻雜源/汲極區之上，而該下側壁直接位於該第 二摻雜源/汲極區之上。
  17. 如專利申請範圍第13項所述之半導體裝置，其中該間隔物層之厚度為通道區長度的10%至70%。
  18. 一種半導體裝置的製造方法，其包含：形成一閘極結構於一基板上；形成一覆蓋該閘極結構之密封間隔物；藉由一原子層沉積製程形成一覆蓋該密封間隔物之閘極間隔物，該閘極間隔物具有一第一垂直部分與一第一水平部分；形成一覆蓋該閘極間隔物之硬遮罩層，該硬遮罩層具有一第二垂直部分與一第二水平部分；移除該硬遮罩層之該第二水平部分以及位於該硬遮罩層之該第二水平部分之下的該閘極間隔物之該第一水平部分；以及形成一覆蓋該閘極間隔物之接觸蝕刻停止層。
  19. 如申請專利範圍第18項所述之半導體裝置的製造方法，進一步包含：在形成該接觸蝕刻停止層前，移除該硬遮罩層之該第二垂直部分。
  20. 如申請專利範圍第18項所述之半導體裝置的製造方法，其中該閘極間隔物於該密封間隔物、該閘極間隔物、該硬遮罩層以及該接觸蝕刻停止層之群組中，具有最低之介電常數。
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US11631745B2 (en) 2020-05-15 2023-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with uneven gate profile
TWI820775B (zh) * 2021-07-16 2023-11-01 台灣積體電路製造股份有限公司 半導體裝置結構及其形成方法

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US20190157419A1 (en) 2019-05-23
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US20210050431A1 (en) 2021-02-18
US10811519B2 (en) 2020-10-20

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