CN113130483A - 半导体结构 - Google Patents

半导体结构 Download PDF

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CN113130483A
CN113130483A CN202110136660.2A CN202110136660A CN113130483A CN 113130483 A CN113130483 A CN 113130483A CN 202110136660 A CN202110136660 A CN 202110136660A CN 113130483 A CN113130483 A CN 113130483A
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gate
layer
dummy fin
fin structures
gate structure
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潘冠廷
苏焕杰
游家权
朱熙甯
江国诚
詹易叡
庄礼阳
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/091,767 external-priority patent/US11799019B2/en
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Publication of CN113130483A publication Critical patent/CN113130483A/zh
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Abstract

半导体结构包括多个鳍状结构，沿着第一方向延伸；多个栅极结构部件，沿着第二方向延伸，第二方向正交于第一方向，其中栅极结构部件隔有多个虚置鳍状结构。半导体结构还包括导电层，位于栅极结构部件与虚置鳍状结构上，以电性连接至少一些栅极结构部件；以及切割结构，对准虚置鳍状结构的一者，以电性隔离虚置鳍状结构的一者的两侧上的栅极结构部件。

Description

半导体结构
技术领域
本公开实施例涉及半导体装置与其制作方法，更特别是涉及制作场效晶体管如全绕式栅极场效晶体管或鳍状场效晶体管的方法。
背景技术
半导体集成电路产业已经历指数成长。集成电路材料与设计的技术进展，使每一代的集成电路具有比前一代更小且更复杂的电路。在集成电路演进中，功能密度(单位晶片面积的内连线装置数目)通常随着几何尺寸(比如采用的制作制程所能产生的最小构件或线路)缩小而增加。尺寸缩小通常有利于增加产能与降低相关成本。尺寸缩小易增加集成电路结构(如三维晶体管)与制程的复杂度。为实现这些进展，处理与制造集成电路的方法需要类似发展。举例来说，随着装置尺寸持续缩小，场效晶体管的装置效能(如与多种缺陷相关的装置效能劣化)与制作成本的挑战也越来越大。虽然解决这些挑战的方法通常适用，但仍无法完全满足所有方面的需求。
发明内容
在一例中，半导体结构包括：多个鳍状结构，沿着第一方向延伸；多个栅极结构部件，沿着第二方向延伸，第二方向正交于第一方向，其中栅极结构部件隔有多个虚置鳍状结构。半导体结构还包括导电层，位于栅极结构部件与虚置鳍状结构上，以电性连接至少一些栅极结构部件；以及切割结构，对准虚置鳍状结构的一者，以电性隔离虚置鳍状结构的一者的两侧上的栅极结构部件。
在一例中，半导体结构包括：沿着第一方向的第一栅极结构部件与一第二栅极结构部件，其隔有沿着第二方向延伸的第一虚置鳍状结构，且第二方向正交于第一方向；第三栅极结构部件，其与第二栅极结构部件隔有沿着第二方向延伸的第二虚置鳍状结构；导电层，连接第一栅极结构部件与第二栅极结构部件；以及切割结构，位于第二虚置鳍状结构上，并隔离第二栅极结构部件与第三栅极结构部件。
在一例中，半导体结构的形成方法包括：形成多个鳍状结构，其延伸于第一方向中；形成多个虚置鳍状结构于鳍状结构之间；形成栅极结构于鳍状结构上；使栅极结构凹陷以露出虚置鳍状结构的上表面，并沿着第二方向将栅极结构分成多个栅极结构部件，且第二方向正交于第一方向；沉积导电层于栅极结构部件与虚置鳍状结构上，且导电层电性连接栅极结构部件；以及形成切割结构于虚置鳍状结构的至少一者上，以电性隔离虚置鳍状结构的至少一者的两侧上的栅极结构部件。
附图说明
图1A、图1B、图1C、图1D、图1E、图1F、及图1G是依据此处所述的原理的一例中，形成栅极切割结构的例示性制程的视图。
图2是依据此处所述的原理的一例中，栅极切割结构的上视图。
图3是依据此处所述的原理的一例中，形成栅极切割结构的例示性方法的流程图。
其中，附图标记说明如下：
102：基板
104：浅沟槽隔离区
105：覆盖材料
106a，106b，106c，106d：鳍状结构
108：硬遮罩层
110，112：层状物
114a，114b，114c：虚置鳍状结构
116：介电材料
118：氧化物层
120：高介电常数的介电层
122：虚置栅极
124：金属材料
124a，124b，124c，124d：金属栅极部件
126：导电层
130：介电层
132a，132b：切割结构
300：方法
302，304，306，308，310，312：制程
具体实施方式
下述详细描述可搭配附图说明，以利理解本公开的各方面。值得注意的是，各种结构仅用于说明目的而未按比例绘制，如本业常态。实际上为了清楚说明，可任意增加或减少各种结构的尺寸。
下述内容提供的不同实施例或例子可实施本公开实施例的不同结构。特定构件与排列的实施例是用以简化而非局限本公开。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。此外，本公开的多种实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外，空间性的相对用语如“下方”、“其下”、“下侧”、“上方”、“上侧”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。
本公开实施例涉及半导体装置与其制作方法，更特别涉及制作场效晶体管如全绕式栅极场效晶体管或鳍状场效晶体管的方法。在全绕式栅极晶体管装置中，栅极围绕通道的所有侧。举例来说，栅极完全围绕悬浮于主动的源极/漏极区之间的一或多个纳米结构。全绕式栅极装置的形成方法可为沉积交错的不同半导体材料层(比如硅层与硅锗层)。接着可图案化这些交错的层状物，以形成鳍状结构。在放置多种其他结构之后，可移除材料之一如硅锗，以保留纳米线或纳米片。接着可形成栅极层如高介电常数的介电层、功函数层、与金属栅极层，以完全围绕每一纳米线与纳米片。
鳍状场效晶体管比平面晶体管的效能好，应为鳍状场效晶体管中的栅极围绕通道的三侧。形成鳍状场效晶体管装置所用的现有方法，关于形成虚置栅极于一组平行的鳍状结构上。接着形成侧壁间隔物于栅极的侧壁上。在形成侧壁间隔物之后，可形成源极/漏极区于栅极结构两侧上的鳍状结构上。在形成源极/漏极区之后，可形成层间介电层于源极/漏极区上，并将虚置栅极置换成含有导电材料如金属材料的实际栅极。
制作半导体的挑战之一为设计图案并考虑切割栅极结构的空间需求。切割栅极结构的形成方法为蚀刻移除之前沉积的栅极的一部分，并将介电材料填入沟槽，进而切割金属栅极结构，使切割结构两侧上的栅极结构彼此电性隔离。
在此处所述的原理中，改变切割结构的深度可实质上改善切割结构与对准制程所用的空间限制。具体而言，介电虚置鳍状结构形成于功能鳍状结构之间。在一些例子中，介电虚置鳍状结构亦可视作混合鳍状结构。接着沉积栅极层于功能鳍状结构与虚置鳍状结构上。接着回蚀刻栅极层以露出虚置鳍状结构的上表面。因此每一虚置鳍状结构将栅极层分成不同的栅极部件。接着可沉积导电层如钨于栅极层与虚置鳍状结构上。导电层可电性连接栅极部件。为了切割栅极层，可形成切割结构于虚置鳍状结构的一者上。因此切割结构可切割虚置鳍状结构上的导电层，因此电性隔离两个相邻的栅极部件。
采用此处所述的原理，可减少切割结构所用的叠对限制，因为切割结构可位于虚置鳍状结构的任一处上。此外，可更紧密地排列鳍状结构以设计电路，即使在切割栅极结构处。
图1A所示的工件包含半导体的基板102与隔有浅沟槽隔离区104的鳍状结构106a、106b、106c、及106d。半导体的基板102可为硅基板。半导体基板可为硅晶圆的部分。亦可实施其他半导体材料。基板102可包含半导体元素(单一元素)如硅、锗、或其他合适材料；半导体化合物如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、及/或其他合适材料；半导体合金如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、磷砷化镓铟、及/或其他合适材料。基板102可为组成一致的单层材料。在其他实施例中，基板102可包含多个材料层，其可具有类似或不同组成以适用于制造集成电路装置。在一例中，基板102可为绝缘层上硅基板，其具有硅层形成于氧化硅层上。在另一例中，基板102可包含导电层、半导体层、介电层、其他层、或上述的组合。
鳍状结构106a、106b、106c、及106d可包含堆叠的通道结构，比如含有纳米线或纳米片的纳米结构。此结构可用于全绕式晶体管装置。在全绕式栅极晶体管装置中，栅极围绕通道的所有侧。举例来说，栅极完全围绕悬浮于主动的源极/漏极区之间的一或多个纳米结构。此处所述的原理可用于鳍状结构，其具有栅极于三侧上，且可对鳍状结构进行制程以包含纳米结构。此处所述的例子可包含纳米结构。因此此处所用的用语鳍状结构可包含自鳍状结构形成的纳米线或纳米片堆叠。
为形成鳍状结构106a、106b、106c、及106d，可沉积交错的不同半导体材料的层状物110及112于基板102上。举例来说，若基板为硅基板，接着可沉积交错的硅层与硅锗层。接着可沉积硬遮罩层108于交错的半导体层的顶部上。硬遮罩层108可包含氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮氧化硅、氧化铪、氧化铝、与氧化锆中的至少一者。亦可实施其他材料。接着可采用光阻材料以图案化硬遮罩层108。接着可由穿过光罩的光源曝光光阻。接着显影光阻以保留光阻的部分并移除光阻的其他部分。接着以蚀刻制程将显影光阻中的图案转移至硬遮罩层108，接着将图案转移至基板102与交错的半导体层。此步骤可形成图示的鳍状结构106a、106b、106c、及106d。鳍状结构可包含彼此平行且伸长的鳍状结构。
在形成鳍状结构106a、106b、106c、及106d之后，可沉积浅沟槽隔离区104，接着回蚀刻浅沟槽隔离区104至所需高度。浅沟槽隔离区104使鳍状结构彼此分开。可使浅沟槽隔离区104凹陷至鳍状结构的底部与顶部之间的近似一半处。然而一些例子中的浅沟槽隔离区104可凹陷至鳍状结构106a、106b、106c、及106d的不同高度处。
在形成浅沟槽隔离区104之后，可顺应性地沉积覆盖材料105于鳍状结构上。覆盖材料105与交错的半导体层的一者可为相同材料，特别是之后移除的半导体层。因此在交错的硅层如层状物112与硅锗层如层状物110的例子中，覆盖材料105可为硅锗。
如图1B所示，形成虚置鳍状结构114a、114b、及114c于实际的鳍状结构106a、106b、106c、及106d之间。虚置鳍状结构的形成方法可为多个制程。具体而言，介电材料116可顺应性地沉积于实际鳍状结构106a、106b、106c、及106d之间的沟槽中。举例来说，此介电材料可为氮化硅、氮氧化硅、或碳化硅。亦可采用其他介电材料。介电材料116的沉积方法可采用原子层沉积制程。
在形成顺应性的介电材料116之后，可沉积氧化物层118于介电材料116上。举例来说，氧化物层118可为氧化硅。在一些例子中，氧化物层118与浅沟槽隔离区104所用的材料可为相同种类。举例来说，氧化物层118的形成方法可采用化学气相沉积制程。亦可采用其他制程。在形成氧化物层118之后，可进行化学机械研磨制程以平坦化工件的上表面。化学机械研磨制程可施加研磨液至工件表面。研磨液可包含蚀刻化学剂与固体粒子。接着可移动研磨头以越过工件表面，而工件上的化学剂与机械力可由实质上类似的速率自工件移除材料，以产生平坦表面。
接着可进行蚀刻制程以选择性移除氧化物层118，而覆盖材料105维持实质上完整。举例来说，蚀刻制程可为干蚀刻制程。在一些例子中，蚀刻制程后的氧化物层118的上表面比鳍状结构106a、106b、106c、及106d的顶部通道如层状物112的上表面高约5nm至15nm。在一些例子中，若高度差异小于5nm，后续形成的高介电常数的介电层增加，进而增加寄生电容。在一些例子中，若高度差异大于15nm，后续形成的高介电常数的介电层在接点结构所用的蚀刻步骤时不足以保护栅极间隔物。
在部分回蚀刻氧化物层118之后，可沉积高介电常数的介电层120于虚置鳍状结构114a、114b、及114c的顶部。高介电常数的介电层120可填入回蚀刻氧化物层118的蚀刻制程所留下的空间。举例来说，高介电常数的介电层可为氧化铪、氧化锆、氧化铪铝、氧化铪硅、或氧化铝。高介电常数的介电层120的下表面，可比鳍状结构106a、106b、106c、及106d的顶部通道如层状物112的上表面高约5nm至15nm。
如图1C所示，形成暂时的虚置栅极122。虚置栅极位于最后形成金属栅极处。侧壁间隔物(未示出)可形成于虚置栅极的两侧上。接着可形成源极/漏极区(未示出)于鳍状结构106a、106b、106c、及106d的通道区如层状物112中。源极/漏极区的形成方法可为移除鳍状结构的部分，并置换成磊晶成长的掺杂区。在形成源极/漏极区之后，可移除虚置栅极122。
如图1D所示，移除覆盖材料105与鳍状结构106a、106b、106c、及106d的非通道区如层状物110。在通道部分如层状物112为硅而非通道区如层状物110为硅锗的例子中，之后移除非通道区如层状物110与覆盖材料105所用的蚀刻制程，可设置为选择性移除硅锗而实质上维持硅完整。在一些例子中，若覆盖材料105与非通道区如层状物110不同，则可采用两个分开的蚀刻制程移除覆盖材料105与非通道区如层状物110。在任何情况下，移除这些区域的蚀刻制程可为湿蚀刻制程。随着通道区如层状物112露出，可开始形成实际金属栅极所用的制程。此制程关于形成多种层状物如高介电常数的栅极介电层(未示出)及/或功函数层(未示出)于通道区如层状物112周围。此功函数金属设计为提供金属栅极所需的特性，以用于理想功能。p型功函数金属的例子可包含但不限于碳氮化钨、氮化钽、氮化钛、氮化钛铝、硫氮化钨、钨、钴、钼、或类似物。n型功函数金属的例子可包含但不限于铝、钛铝、碳化钛铝、碳化钛铝硅、碳化钽铝硅、或碳化铪。
在一些例子中，湿蚀刻制程可采用酸为主的蚀刻剂如硫酸、过氯酸、碘化氢、溴化氢、硝酸、氯化氢、乙酸、柠檬酸、过碘酸钾、酒石酸、苯甲酸、四氟硼酸、碳酸、氰化氢、亚硝酸、氢氟酸、或磷酸。在一些例子中，可采用碱为主的蚀刻剂。这些蚀刻剂可包含但不限于氢氧化铵或氢氧化钾。
如图1E所示，形成每一鳍状结构106a、160b、106c、及106d所用的金属栅极部件124a、124b、124c、及124d。形成金属栅极部件的方法，可先沉积金属材料124于之前移除制程所留下的空间中。金属材料124围绕每一通道区如层状物112。在沉积金属材料124之后，可回蚀刻金属材料124使金属材料124的上表面低于虚置鳍状结构114a、114b、及114c的上表面。举例来说，蚀刻制程可为干蚀刻制程。蚀刻制程可露出虚置鳍状结构114a、114b、及114c的上表面。可进行蚀刻制程，使金属栅极部件124a、124b、124c、及124d的上表面与虚置鳍状结构114a、114b、及114c的上表面之间的距离小于2nm。在一些例子中，若高度差异大于2nm，则损伤功函数金属的一部分并影响装置的临界电压。
如图1F所示，形成导电层126以覆盖金属栅极部件124a、124b、124c、及124d，并覆盖虚置鳍状结构114a、114b、及114c的上表面。因此导电层126使栅极部件124a、124b、124c、与124d彼此电性连接。导电层126可包含钨、钴、钌、与铜中的至少一者。在一些例子中，在沉积导电层之前可视情况沉积薄层。薄层包含钛、氮化钛、钽、氮化钽、钴、与钌中的至少一者。导电层126的沉积方法可采用多种沉积技术如化学气相沉积。
如图1G所示，形成介电层130以及切割结构132a及132b。介电层130以及切割结构132a及132b包含氮化硅、氮氧化硅、碳化硅、与碳氮化硅中的至少一者。在此例中，沉积介电层130于导电层126上。介电层130亦可视作自对准的盖层。在沉积介电层之后，可图案化介电层。图案化制程可观于沉积硬遮罩层与光阻层。接着以穿过光罩的光源曝光光阻。接着可显影光阻以保留图案于光阻中。接着可将图案转移至硬遮罩。接着可经由硬遮罩对介电层130进行蚀刻制程如干蚀刻制程。蚀刻制程可形成沟槽，其一直延伸至虚置鳍状结构。换言之，蚀刻制程可移除介电层130的部分与导电层126的部分，以露出一些虚置鳍状结构的上表面。因此蚀刻制程可切割导电层。
在进行蚀刻制程之后，可形成切割结构132a及132b于蚀刻制程所留下的沟槽中。切割结构132a及132b可包含介电材料，且一些例子中的切割结构132a及132b与介电层130可为相同材料。在一些例子中，切割结构132a及132b可包含不同的介电结构。
切割结构132a及132b可电性隔离不同的金属栅极部件。举例来说，切割结构132a可电性隔离金属栅极部件124b及124c。类似地，切割结构132b可电性隔离金属栅极部件124c及124d。由于虚置鳍状结构114a上无切割结构，金属栅极部分124a及124b经由导电层126维持电性连接。
在此例中，切割结构132a的宽度小于其连接的虚置鳍状结构114b的宽度。然而切割结构132b的宽度大于其连接的虚置鳍状结构114c的宽度。在一些例子中，切割结构132b可延伸至金属栅极部件124c及124d的上表面，且因此部分地覆盖虚置鳍状结构114c的侧表面的最顶部。
图2是栅极切割结构的上视图。因此图2显示实际的鳍状结构106a、106b、106c、及106d以及虚置鳍状结构114a、114b、及114c，其沿着第一方向。覆盖金属栅极部件124a、124b、124c、及124d的导电层126可延伸于第二方向中，且第二方向垂直于第一方向。如图所示，栅极切割结构132a位于虚置鳍状结构114b上，并切割鳍状结构106b及106c之间的导电层126的部分。类似地，栅极切割结构位于虚置鳍状结构114c上，并切割鳍状结构106c及106d之间的导电层126的部分。
图3的流程图显示栅极切割结构的例示性方法。在此例中，方法300包含的制程302可形成多个延伸于第一方向中的鳍状结构(如鳍状结构106a、106b、106c、及106d)。鳍状结构可包含纳米结构如纳米线或纳米片。这些结构可用于全绕式栅极晶体管装置。此处所述的原理可用于具有栅极于其三侧上的鳍状结构，以及可进行制程以包含纳米结构的鳍状结构。此处所述的例子包含纳米结构。
为形成鳍状结构，可沉积交错的不同半导体材料层(如层状物110及112)于基板(如基板102)上。举例来说，若基板为硅基板，接着可沉积交错的硅层与硅锗层。接着可沉积硬遮罩层108于交错的半导体层的顶部上。硬遮罩层108可包含氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮氧化硅、氧化铪、氧化铝、与氧化锆中的至少一者。亦可实施其他材料。接着可采用光阻材料以图案化硬遮罩层。接着可由穿过光罩的光源曝光光阻。接着可显影光阻以保留光阻的部分并移除光阻的其他部分。接着以蚀刻制程将显影后的光阻中的图案转移至硬遮罩层，接着将图案转移至基板与交错的半导体层。
形成鳍状结构之后，可沉积浅沟槽隔离区(如浅沟槽隔离区104)，接着回蚀刻浅沟槽隔离区至所需高度。浅沟槽隔离驱使鳍状结构彼此分开。可使浅沟槽隔离区凹陷至鳍状结构的底部与顶部之间的近似一半处。然而一些例子可使浅沟槽隔离区至鳍状结构的不同高度处。
在此例中，方法300还包含制程304以形成多个虚置鳍状结构(如虚置鳍状结构114a、114b、及114c)于多个鳍状结构之间。虚置鳍状结构的形成方法可为多个制程。具体而言，可顺应性沉积第一介电材料(如介电材料116)于实际鳍状结构之间的沟槽中，而覆盖材料(如覆盖材料105)可围绕第一介电材料。举例来说，介电材料可为氮化硅、氮氧化硅、或碳化硅。亦可采用其他介电材料。介电材料的沉积方法可采用原子层沉积制程。
在形成顺应性的介电层之后，可沉积第二介电层(如氧化物层118)于第一介电层上。第二介电层可为氧化物层。举例来说，氧化物层可为氧化硅、氧化铝、或氧化钛。亦可实施其他氧化物。在一些例子中，氧化物层与浅沟槽隔离区所用的材料种类可相同。举例来说，氧化物层的形成方法可采用化学气相沉积制程。亦可采用其他制程。在形成氧化物层118之后，可进行化学机械研磨制程以平坦化工件的上表面。
接着可进行蚀刻制程以选择性移除氧化物层，并保留实质上完整的覆盖材料。举例来说，蚀刻制程可为干蚀刻制程。在一些例子中，蚀刻制程之后的氧化物层的上表面可比鳍状结构的顶部通道(如层状物112)的上表面高约5nm至约15nm。
在部分回蚀刻氧化物层之后，可沉积高介电常数的介电层(如高介电常数的介电层120)于虚置鳍状结构的顶部。高介电常数的介电层可填入回蚀刻氧化物层的蚀刻制程所留下的空间。高介电常数的介电层可为氧化铪、氧化锆、氧化铪铝、氧化铪硅、或氧化铝。高介电常数的介电层的下表面可比鳍状结构的顶部通道的上表面高约5nm至15nm。
方法300还包含制程306，以形成栅极结构于鳍状结构上。栅极结构(如金属栅极部件124a、124b、124c、及124d)的形成方法可为沉积金属材料于鳍状结构上。在鳍状结构包括纳米结构如纳米线或纳米片的例子中，可在沉积栅极结构之前，移除围绕纳米片或纳米线的材料如层状物110。在沉积栅极结构之前，可沉积多种层状物以围绕通道如层状物112。这些层状物可包含高介电常数的栅极介电层及/或功函数层。
方法300还包括制程308使栅极结构凹陷以露出虚置鳍状结构的上表面，并将栅极结构分成沿着第二方向延伸的多个栅极结构部件(如金属栅极部件124a、124b、124c、及124d)，且第二方向正交于第一方向。举例来说，此蚀刻制程可为干蚀刻制程。蚀刻制程露出虚置鳍状结构的上表面。
方法还包含制程310以沉积导电层(如导电层126)于栅极结构部件与虚置鳍状结构上，且导电层电性连接栅极结构部件。举例来说，导电层可包含钨。在一些例子中，可在沉积导电层之前沉积薄层。举例来说，薄层可为氮化钛。导电层的沉积方法可采用多种沉积技术如化学气相沉积。
方法还包含制程312以形成切割结构(如切割结构132a或132b)于虚置鳍状结构的至少一者上，以电性隔离虚置鳍状结构的至少一者的两侧上的栅极结构部件。切割结构可形成于介电层(如介电层130)中，而介电层沉积于导电层的顶部上。举例来说，介电层以及切割结构可包含氮化硅。介电层可沉积于导电层上。在沉积介电层之后，可图案化介电层。图案化制程可关于沉积硬遮罩层与光阻层。接着可由穿过光罩的光源曝光光阻。接着可显影光阻以留下图案于光阻中。接着可将图案转移到硬遮罩。接着可经由硬遮罩对介电层进行蚀刻制程如干蚀刻制程。蚀刻制程可形成沟槽，其一直延伸到虚置鳍状结构。换言之，蚀刻制程可移除介电层的部分与导电层的部分，以露出一些虚置鳍状结构的上表面。因此蚀刻制程可切割导电层。在进行蚀刻制程之后，可形成切割结构于蚀刻制程所留下的沟槽中。切割结构可包含介电材料，且一些例子中的切割结构与介电层可为相同材料。在一些例子中，切割结构宽度可小于其连接的虚置鳍状结构宽度。然而一些例子中的切割结构宽度可大于其连接的虚置鳍状结构宽度。
依据此处所述的原理，因此改变切割结构的深度可实质上改善切割结构与对准制程所用的空间限制。与其他方式相较，结合虚置鳍状结构与切割结构可进一步减少单元高度，进而增加电路设计相关的图案密度。采用此处所述的原理可减少切割结构的叠对限制，因为切割结构可置于虚置鳍状结构上的任一处。此外，可更紧密地排列鳍状结构以设计电路，即使在切割栅极结构处。
在一例中，半导体结构包括：多个鳍状结构，沿着第一方向延伸；多个栅极结构部件，沿着第二方向延伸，第二方向正交于第一方向，其中栅极结构部件隔有多个虚置鳍状结构。半导体结构还包括导电层，位于栅极结构部件与虚置鳍状结构上，以电性连接至少一些栅极结构部件；以及切割结构，对准虚置鳍状结构的一者，以电性隔离虚置鳍状结构的一者的两侧上的栅极结构部件。
在一例中，虚置鳍状结构包括高介电常数的介电材料沉积于氧化物材料上。
在一例中，高介电常数的介电材料的底部高于鳍状结构的通道部分的顶部。
在一例中，虚置鳍状结构包括氧化物材料，与虚置鳍状结构的两侧上的介电片层。
在一例中，虚置鳍状结构的顶部高于栅极结构部件的顶部。
在一例中，虚置鳍状结构的顶部比栅极结构部件的顶部高约5nm至10nm。
在一例中，导电层包括钨。
在一例中，鳍状结构包括堆叠的通道结构。
在一例中，切割结构延伸至低于栅极结构部件的上表面的距离小于2nm。
在一例中，半导体结构包括：沿着第一方向的第一栅极结构部件与一第二栅极结构部件，其隔有沿着第二方向延伸的第一虚置鳍状结构，且第二方向正交于第一方向；第三栅极结构部件，其与第二栅极结构部件隔有沿着第二方向延伸的第二虚置鳍状结构；导电层，连接第一栅极结构部件与第二栅极结构部件；以及切割结构，位于第二虚置鳍状结构上，并隔离第二栅极结构部件与第三栅极结构部件。
在一例中，半导体结构还包括通道结构延伸穿过第一栅极结构部件、第二栅极结构部件、与第三栅极结构部件。
在一例中，通道结构包括纳米线。
在一例中，通道结构包括纳米片。
在一例中，半导体结构还包括自对准的盖结构位于导电层上。
在一例中，切割结构与自对准盖层包括相同材料。
在一例中，第一虚置鳍状结构与第二虚置鳍状结构包括：中心部分，包括第一介电材料；片部分，包括第二介电材料且位于中心部分的侧壁上；以及高介电常数的介电材料，位于中心部分的顶部上。
在一例中，高介电常数的介电材料的上表面高于第一栅极结构部件、第二栅极结构部件、与第三栅极结构部件的上表面。
在一例中，半导体结构的形成方法包括：形成多个鳍状结构，其延伸于第一方向中；形成多个虚置鳍状结构于鳍状结构之间；形成栅极结构于鳍状结构上；使栅极结构凹陷以露出虚置鳍状结构的上表面，并沿着第二方向将栅极结构分成多个栅极结构部件，且第二方向正交于第一方向；沉积导电层于栅极结构部件与虚置鳍状结构上，且导电层电性连接栅极结构部件；以及形成切割结构于虚置鳍状结构的至少一者上，以电性隔离虚置鳍状结构的至少一者的两侧上的栅极结构部件。
在一例中，形成虚置鳍状结构的步骤包括：顺应性沉积第一介电材料于两个鳍状结构之间的沟槽中；沉积第二介电材料于第一介电材料上，其中第二介电材料与第二介电材料不同；以及沉积第三介电材料于第一介电材料的顶部上。
在一例中，形成切割结构的步骤包括：形成介电层于导电层上；蚀穿介电层与一部分的导电层；以及沉积介电材料于蚀刻步骤所定义的孔洞中。
上述实施例的特征有利于本技术领域中具有通常知识者理解本公开。本技术领域中具有通常知识者应理解可采用本公开作基础，设计并变化其他制程与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中具有通常知识者亦应理解，这些等效置换并未脱离本公开精神与范畴，并可在未脱离本公开的精神与范畴的前提下进行改变、替换、或更动。

Claims (1)

1.一种半导体结构，包括：
多个鳍状结构，沿着一第一方向延伸；
多个栅极结构部件，沿着一第二方向延伸，该第二方向正交于该第一方向，其中该栅极结构部件隔有多个虚置鳍状结构；
一导电层，位于所述栅极结构部件与所述虚置鳍状结构上，以电性连接至少一些所述栅极结构部件；以及
一切割结构，对准所述虚置鳍状结构的一者，以电性隔离所述虚置鳍状结构的一者的两侧上的所述栅极结构部件。
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