CN114597162A - 半导体结构的形成方法 - Google Patents

半导体结构的形成方法 Download PDF

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CN114597162A
CN114597162A CN202210020733.6A CN202210020733A CN114597162A CN 114597162 A CN114597162 A CN 114597162A CN 202210020733 A CN202210020733 A CN 202210020733A CN 114597162 A CN114597162 A CN 114597162A
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layer
dielectric layer
semiconductor
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李振铭
李威养
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体结构的形成方法,包括:在基板的背侧上执行第一蚀刻制程,以露出虚设接触结构;执行第一沉积制程以在虚设接触结构周围沉积第一介电层;执行第二沉积制程以在第一介电层上沉积氧化层;移除虚设接触结构以形成沟槽;在沟槽的多个侧壁上沉积牺牲层;在牺牲层上沉积第二介电层;以导电材料填充沟槽;以及移除牺牲层以在第一介电层及第二介电层之间形成空气间隔物。

Description

半导体结构的形成方法
技术领域
本公开实施例是关于半导体结构,特别是关于具有空气间隔物的背向接触件的半导体结构及其形成方法。
背景技术
半导体集成电路(integrated circuit;IC)产业经历了快速成长。IC材料和设计上的技术进步产生了一代又一代的IC,每一代都比上一代的电路更小、更复杂。集成电路演进期间,功能密度(亦即,单位芯片面积的互连装置数目)通常会增加,而几何尺寸(亦即,即可使用制程生产的最小元件(或线))却减少。此微缩化的制程通常会以增加生产效率与降低相关成本而提供助益。然而,此微缩化的制程通常也会通过提高生产效率和降低相关成本来提供效益。这种微缩化也增加了集成电路结构(如三维晶体管)和加工的复杂性,为了实现这些演进,在集成电路加工和制造方面有类似的发展是必要的。例如,当装置尺寸继续缩小时,场效晶体管的装置性能(如与各种缺陷相关的装置性能退化)和制造成本变得更具挑战性。尽管解决这种挑战的方法一般来说是足够的,但其并非在所有面向都令人满意。
发明内容
本发明实施例提供一种半导体结构的形成方法,包括:在基板的背侧上执行第一蚀刻制程,以露出虚设接触结构;执行第一沉积制程以在虚设接触结构周围沉积第一介电层;执行第二沉积制程以在第一介电层上沉积氧化层;移除虚设接触结构以形成沟槽;在沟槽的多个侧壁上沉积牺牲层;在牺牲层上沉积第二介电层;以导电材料填充沟槽;以及移除牺牲层以在第一介电层及第二介电层之间形成空气间隔物。
本发明实施例提供一种半导体结构的形成方法,包括:执行蚀刻制程,以从基板的背侧移除虚设接触结构以及在沟槽的底部露出源极/漏极区;在沟槽的多个侧壁上沉积牺牲层;在牺牲层上沉积介电层;以导电材料填充沟槽;以及移除牺牲层。
本发明实施例提供一种半导体结构,包括:基板,具有前侧及背侧;晶体管,形成在基板的前侧上,晶体管包含源极/漏极区;接触件,从源极/漏极区的底部延伸至基板的背侧;以及第一介电层,沿着接触件的多个侧面设置;气隙,设置于第一介电层及第二介电层之间。
附图说明
由以下的详细叙述配合所附图式,可最好地理解本发明实施例。应注意的是,依据在业界的标准做法,各种特征并未按照比例绘制。事实上,可任意地放大或缩小各种元件的尺寸,以清楚地表现出本发明实施例的特征。
图1A、图1B、图1C、图1D、图1E、图1F、图1G、图1H、图1I、图1J、及图1K是根据本公开的一实施例,绘示出形成具有空气间隔物的背向接触件的示例性制程的图示。
图2是根据本公开的一实施例,绘示出形成具有空气间隔物的背向接触件的示例性方法的流程图。
其中,附图标记说明如下:
102:基板
104:栅极
106:通道
108:内间隔物
110:源极/漏极
111:移除制程
112:虚设接触结构
113:制程
114:氧化层
115:制程
116:第一介电层
117:制程
118:开口
119:制程
120:内隔层
122:虚设材料
123:制程
124:第二介电层
125:制程
126:金属栓塞
127:制程
130:气隙
132:密封层
具体实施方式
以下配合所附图式详述本公开各实施例,以便本公开所属技术领域中具有通常知识者可制作及使用本公开。在本公开所属技术领域中具有通常知识者应理解,他们能在阅读本公开后,在不脱离本公开的范围下将此处描述的示例进行各种改变或修改。因此,本公开不限于在此描述和说明的示例性实施例和应用。另外,本文公开的方法中,步骤的特定顺序和/或层级仅为示例性方法。根据设计偏好,可以在本公开的范围内重新设置所公开的方法或制程中步骤的特定顺序或层级。因此,所属技术领域中具有通常知识者将理解,本文公开的方法和技术以示例顺序呈现各种步骤或动作,除非另有明示,否则本公开内容不限于所呈现的特定顺序或层级。
再者,其中可能用到与空间相对用词,例如「在…之下」、「下方」、「较低的」、「上方」、「较高的」等类似用词,是为了便于描述图式中一个(些)部件或特征与另一个(些)部件或特征之间的关系。空间相对用词用以包括使用中或操作程式中的装置的不同方位,以及图式中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位),其中所使用的空间相对形容词也将依转向后的方位来解释。诸如「附接」、「固定」、「连接」和「互连」之类的术语是指一种关系,结构通过中间结构直接或间接地彼此固定或附接,以及可移动的或固定的附件或关系,除非另有明示。
本公开内容一般与半导体装置及其制造有关,特别是与制造场效晶体管(fabricating field-effect transistor;FET)的方法有关,例如鳍式场效晶体管(fin-like FET;FinFET)、全绕式栅极场效晶体管(gate-all-around FETs;GAA FET)和/或其他场效晶体管。
在一些示例性实施例中,为了形成GAA装置,半导体鳍片可包含总共三至十个半导体材料的交替层。例如,第一半导体材料可以是硅,而第二半导体材料可以是硅锗。任何一种半导体材料和(或两者)都可以掺入适合的掺杂物,如p型掺杂物或n型掺杂物,以形成所需的场效晶体管。半导体材料和可以各自通过外延制程形成,例如,分子束外延(molecularbeam epitaxy;MBE)制程、CVD制程和/或其他合适的外延生长制程。
半导体材料的交替层用于提供纳米导线或纳米片装置,例如GAA FET,其形成的细节在下文提供。GAA FET被引入,以致力于通过增加栅极-通道耦合、降低断态电流(OFF-state current)和减少短通道效应(short-channel effects)来改善闸控。如GAA FET的多栅极装置通常包含包围其通道区域(水平或垂直)延伸的栅极结构,在四周提供存取至通道区域。GAA FET通常与CMOS(complementary metal–oxide–semiconductor)制程相容,这使它们在维持闸控和减轻短通道效应的同时也积极地缩小规模。当然,本公开内容并不局限于形成GAA FET,可以提供其他三维FET,如FinFET。
在GAA装置中,通过沉积选择性蚀刻的半导体材料的交替层来形成通道堆叠。例如,第一种类型的半导体材料可以外延生长在基板上。然后,第二类半导体材料可以外延生长在上述的第一层上。此制程继续通过形成第一和第二类半导体材料的交替层进行。然后,可以将通道堆叠图案化成鳍片结构。因此,每个鳍片可以是交替的半导体层的鳍片堆叠。然后,可以使用蚀刻制程(例如,湿式蚀刻制程)来移除第二半导体材料,同时使第一半导体材料大抵上保持完整。因此,剩下的第二半导体材料可以形成在两个活性区域之间延伸的纳米导线或纳米片的堆叠。接着,可以形成栅极装置以完整地包围每个纳米导线或纳米片。在栅极装置的每一侧是源极区或漏极区。
在传统的制造技术中,源极/漏极特征是通过执行蚀刻制程形成源极和漏极特征的凹槽而形成的。这种凹槽通常以相似的深度形成。然后,使用外延生长制程以在凹槽内生成源极和漏极结构。在某些情况下,在源极和漏极结构形成后,可以形成对应源极结构的背向接触件。形成背向接触件可能涉及对晶圆的背侧进行图案化,以露出源极结构的底部,并形成导电接触结构以连接到源极结构。在某些情况下,形成背向接触件可能涉及更深入地蚀刻源极/漏极结构的沟槽,并用牺牲性的虚设接触结构填充底部。在翻转半导体基板以执行背侧加工后,将基板的部分移除以露出虚设接触结构。然后,虚设接触结构可以用导电(即金属)结构取代。最好是能提高此背向接触件的效能。
根据本文描述的原则,背向接触件包含沿着侧面的空气间隔物(也称为气隙)。此空气间隔物可通过沿沟槽的侧壁沉积牺牲材料而形成,此沟槽为移除虚设接触结构留下的。然后,可以在牺牲金属层上沉积介电层。在介电层形成后,用金属或其他导电材料来填充沟槽。然后,可将牺牲材料移除。这在金属接触件周围留下了气隙。气隙减少了电容,这可以改善装置的性能。
图1A、图1B、图1C、图1D、图1E、图1F、图1G、图1H、图1I、图1J、及图1K是根据本公开的一实施例,绘示出形成具有较宽部分以及较窄部分的放大的背向接触件的示例性制程的图示。图1A为显示说明性工件的剖面图。此工件包含半导体基板102。半导体基板102可以是硅基板。半导体基板可以是硅晶圆的一部分。也可以考虑其他半导体材料。基板102可以包含基本(单元素)的半导体,如硅、锗和/或其他合适的材料;化合物半导体,如碳化硅、砷化镓、磷化铟、砷化铟、锑化铟和/或其他合适的材料;合金半导体,如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInAsP和/或其他合适的材料。基板102可以是具有均匀成分的单层材料。或者,基板102可以包含具有类似或不同成分的多个材料层,适用于IC装置的制造。在一示例中,基板102可以是绝缘体上的硅(silicon-on-insulator;SOI)基板,具有在氧化硅层上形成的硅层。在另一示例中,基板102可以包含导电层、半导体层、介电层、其他层或其组合。
图1A绘示出包含由栅极104结构包围的几个通道106区域或纳米结构的鳍片堆叠。在鳍片堆叠之间的是源极/漏极结构110。内间隔物108沿着通道106之间的栅极104结构设置,以将栅极104结构与源极/漏极结构110隔离。
为了形成这种结构,在基板102上沉积了第一类半导体层。第一类的半导体材料是一种最终将被移除的牺牲材料。因此,此层也将被称为牺牲半导体层。接着,沉积第二类半导体材料。第二类半导体层最终将形成纳米结构晶体管装置的通道的部分。因此,第二类半导体层也将被称为通道半导体层。第一类半导体材料和第二类半导体材料的形成都可以使用外延生长制程来完成。形成第一类半导体材料和第二类半导体材料的制程可以重复进行,直到达到所需的层数。在达到所需的半导体层数后,可以在顶部形成最后将被实质的金属或导电及栅极取代的虚设栅极结构。
然后,使用图案化制程在要形成源极/漏极结构110的区域中的半导体层内形成凹槽。图案化制程可以包含光微影制程。例如,可以在工件上沉积硬遮罩层和光阻层。硬遮罩层可以包含至少一种氧化硅(SiO2)、氮化硅(SiN)、碳化硅(SiC)、氧氮化硅(SiON)、氧碳化硅(SiOCN)、氧化铪(HfO2)、氧化铝(Al2O3)和氧化锆(ZrO2)。
接着,可通过光罩将光阻层露出于光源下。然后,可将光阻剂显影。然后,可执行蚀刻制程以将光阻剂中的图案转移到硬遮罩层。在这个制程之后,硬遮罩露出了交替设置的层的部分。然后,使用定向蚀刻制程(directional etching process),如干式蚀刻制程,对半导体层进行图案化。
侧向蚀刻制程用于部分移除将形成内间隔物108的牺牲半导体层。横向蚀刻制程可以是,例如,湿式蚀刻制程。在一些示例中,也可以使用干式蚀刻制程。蚀刻制程可以设计成有选择性的,以便在不严重影响半导体层的情况下移除牺牲半导体层。例如,在牺牲半导体层是硅锗并且半导体层是硅的情况下,那么蚀刻制程可以用以在不影响硅的情况下移除硅锗)。
然后,执行沉积制程来形成内间隔物108。具体而言,内隔层120是通过保形沉积制程(conformal deposition process)形成的,以便内隔层沿着凹槽的侧壁形成,源极/漏极结构110将形成于上述凹槽中。内隔层可以是一种介电材料,如SiCN、SiOCN、或SiON或SiO2
接着可以使用回蚀制程来移除内隔层的部分并露出通道层106。蚀刻制程也从凹槽的底部及工件的顶部移除内隔层。内隔层的剩余部分用于将栅极104结构的部分与要形成的源极区和漏极区进行电性隔离。在一些示例中,剩余的内隔层可以在大约4-15纳米的宽度范围内变化。
为了形成背向接触件,将形成源极/漏极区的凹槽进一步蚀刻以形成更深的凹槽。此蚀刻制程可将凹槽的深度再延长45-65纳米。然后,虚设接触结构112可在沟槽的底部形成。这可以通过外延生长制程来完成。虚设接触结构可以是,例如,由不含掺杂物的硅锗制成。在一些示例中,硅锗与硅的比例可以在大约30-40%的范围内。
在形成虚设接触结构112后,可以形成源极/漏极结构110。在一些示例中,源极/漏极结构110是通过执行外延生长制程而形成的。外延生长制程包含在晶体基板上形成晶体结构。在本示例中,源极和漏极区是从虚设接触结构112和通道106区域生长而成的。在一些示例中,源极区和漏极区可以进行原位(in situ)掺杂,以获得所需的特性。
在源极/漏极结构110形成后,可以用实质的栅极104替换虚设的栅极结构和牺牲半导体材料。这可以通过用湿式蚀刻制程移除牺牲半导体材料和虚设的栅极结构来完成。湿式蚀刻制程可以是选择性的,以移除牺牲半导体层,使通道106层大抵上保持完整。湿式蚀刻制程可以使用酸基蚀刻剂,例如。硫酸(H2SO4)、过氯酸(HClO4)、氢碘酸(HI)、氢溴酸(HBr)、硝酸(HNO3)、盐酸(HCl)、乙酸(CH3COOH)、柠檬酸(C6H8O7)、高碘酸钾(KIO4)。酒石酸(C4H6O6)、苯甲酸(C6H5COOH)、四氟硼酸(HBF4)、碳酸(H2CO3)、氰化氢(HCN)、硝酸(HNO2)、氢氟酸(HF)或磷酸(H3PO4)。在一些示例中,可以使用碱基蚀刻剂。这种蚀刻剂可以包含但不限于氢氧化铵(NH4OH)和氢氧化钾(KOH)。也可以使用干式蚀刻制程,例如,用HF或F2气体。通过移除牺牲半导体层,通道106层成为在源极/漏极结构110之间延伸的纳米结构。
在移除虚设栅极结构后,形成实质的栅极结构。实质的栅极装置的形成可包含若干步骤。例如,可以沉积高介电层,以包围通道106层。高介电层可以包含,例如,氧化铝、氧化铪、氧化锆、氧化铪铝,或氧化铪硅。也可以使用其他材料。例如,可以使用介电常数大于7的其他材料。
在一些示例中,根据正在形成的晶体管装置的类型,可以沉积工作功能层。将这样的金属设计成金属栅极,其具有为达成理想功能的理想特性。p型工作功能金属的各种例子可以包含但不限于钨碳氮化物(WCN)、氮化钽(TaN)、氮化钛(TiN)、钛铝氮化物(TiAlN)、钨硫氮化物(TSN)、钨(W)、钴(Co)、钼(Mo)等等。n型工作功能金属的各种例子包含但不限于铝(Al)、钛铝(TiAl)、钛铝碳化物(TiAlC)、钛铝碳化硅(TiAlSiC)、钽铝碳化硅(TaAlSiC)和碳化铪(HfC)。然后,沉积栅极层。栅极层可以是一种导电材料,如金属材料。以此方式,栅极层完整地包围了每个通道106层。
图1B绘示出用于形成具有气隙的背向接触件的后段产线(Back-End-of-Line;BEOL)制程的开始。为此,对工件的背侧采用移除制程111,以移除基板102的背侧部分并露出虚设接触结构112。这个移除制程可以是,例如,湿式蚀刻制程。湿式蚀刻制程可以是有选择性的,以便在移除半导体基板102的同时,使虚设源极接触结构大抵上保持完整。
图1C绘示出形成制程113,以在虚设接触结构112周围形成第一介电层116,以及在第一介电层116上形成氧化层114。在第一介电层116和氧化层114都形成后,可以采用CMP制程,以对工件的表面进行平面化处理。第一介电层116包围虚设接触结构112。介电层可以是,例如,SiN层(ALD沉积)。介电层可以通过沉积制程形成,如原子层沉积(atomic layerdeposition;ALD),或化学气相沉积(chemical vapor deposition;CVD)。
图1D绘示出回蚀制程115,通过此制程移除虚设接触SiGe结构。此蚀刻制程是有选择性的,以便在第一介电层116和氧化层114大抵上保持完整的情况下,移除虚设结构。回蚀制程115可以是异向性的蚀刻制程,如干式蚀制程。回蚀制程留下了开口118。
图1E绘示出在开口118内将BARC(bottom anti-reflective coating)沉积,接着部分地回蚀的制程117。此蚀刻制程可以是干式蚀刻制程。BARC(底部防反射涂层)用以保护工件的其他部分,例如源侧外延生长制程。
图1F绘示出放大用于背向接触件金属间隙填充的背向接触件开口的制程119。例如,这可以通过等向性的干式蚀刻制程来完成,以通过圆化开口的顶角来移除氧化层114和第一介电层116。然后,可以使用灰化制程来移除内隔层120(eg.BARC层)。
图1G绘示出沉积制程,通过此制程将虚设材料122层沉积在工件上。虚设材料122层可以使用原子层沉积(ALD)制程沉积。虚设材料122层可以包含硅、硅锗或氧化铝。在沉积虚设材料122层后,可采用异向性的蚀刻制程,将材料从氧化层的顶表面和露出的源极/漏极结构110的顶部表面移除。在此蚀刻制程之后,虚设材料122层仍留在开口的侧壁上。
图1H绘示了制程123,通过此制程将第二介电层124沉积在虚设材料122层上。此第二介电层124可以包含氮化硅。在沉积第二介电层124之后,可采用异向性的干式蚀刻制程,以从氧化层的114的顶表面及源极/漏极110层移除介电材料。第二介电层124可以使用ALD制程形成。
图1I绘示出沉积制程125,通过此制程形成了金属栓塞126。金属栓塞126可以是使用CVD、ECP沉积的钴材料。在一些示例中,金属栓塞126可以是通过CVD沉积的钨、钌或钼。在一些示例中,在金属栓塞形成之前,可以用TiSi制程对开口118进行清洗。在金属栓塞形成后,可采用CMP制程以对芯片的背侧进行平面化处理。
图1J绘示出移除虚设材料122的制程127。这可以使用有选择性的等向性或异向性的制程来完成,以便移除虚设材料122,同时使氧化层114、第一介电层116、第二介电层124和金属栓塞126大抵上保持完整。移除虚设材料122后,在第一介电层116和第二介电层124之间留下气隙130。
图1K绘示出在工件上沉积密封层132的情况。密封层132可以包含氮化硅。密封层132可以使用ALD制程,例如等离子体辅助ALD(Plasma Enhanced ALD;PE-ALD)制程进行沉积。密封层132将顶部的气隙130关闭。此气隙提供了改进的装置性能,因为它减少了金属栓塞126和金属栅极104装置之间的寄生电容。换句话说,这改善了晶体管的性能,因为晶体管装置的接触件(栓塞126)和栅极104之间的寄生电容较少。
图2是根据本公开的一实施例,绘示出形成具有空气间隔物的背向接触件的示例性方法的流程图。根据本实施例,方法200包括用于在基板(例如102)的背侧执行第一蚀刻制程(例如111)以露出虚设接触结构(例如112)的制程202。此移除制程可以是,例如,湿式蚀刻制程。湿式蚀刻制程可以是有选择性的,以便在移除半导体基板的同时,使虚设源极接触结构大抵上保持完整。
方法200还包括用于执行第一沉积制程的制程204,以在虚设接触结构周围沉积第一介电层(例如,116)。介电层可以是例如SiN层(ALD沉积)。介电层可以使用沉积制程形成,如原子层沉积(ALD),或化学气相沉积(CVD)。
此方法200还包括用于执行第二沉积制程的制程206,以在第一介电层上沉积氧化层(例如114)。在氧化层形成之后,可以使用CMP制程来对芯片的背侧表面进行平坦化。
此方法还包括用于移除虚设接触结构的制程208,以形成沟槽(例如,118)。这可以用有选择性的蚀刻制程来完成,以便在大抵上完整的第一介电层和氧化层的情况下移除虚设结构。蚀刻制程可以是异向性的蚀刻制程,如干式蚀刻制程。
此方法还包括用以在沟槽的侧壁上沉积牺牲层(例如,122,也被称为虚设材料)的制程210。牺牲层可以使用原子层沉积(ALD)制程进行沉积。牺牲层可以包含硅、硅锗、或氧化铝。牺牲层沉积后,可采用异向性的蚀刻制程,将材料从氧化层的顶表面和露出的源极/漏极结构的顶表面移除。在此蚀刻制程之后,牺牲层仍然留在开口的侧壁上。
此方法还包括用以在牺牲层上沉积第二介电层(例如,124)的制程212。此介电层可以包含氮化硅。在沉积介电层之后,可以采用异向性的干式蚀刻制程,以移除形成氧化层和源极/漏极电层的顶表面的介电材料。介电层可以使用ALD制程形成。
此方法200还包括用于以导电材料填充沟槽的制程214。这形成了金属栓塞(例如126)。金属栓塞126可以是使用CVD、ECP沉积的钴材料。在一些示例中,金属栓塞可以是钨、钌或钼,通过CVD沉积。在一些示例中,在形成金属栓塞之前,可以用TiSi制程对开口(或沟槽)进行清洁。在金属栓塞形成后,可采用CMP制程以对晶圆的背侧进行平面化处理。
此方法200还包括用以移除牺牲层以在第一介电层和第二介电层之间形成空气间隔物(例如,130)的制程216。这可以使用具有选择性的等向性或异向性的制程来完成,以便移除牺牲层,同时使氧化层、第一介电层、第二介电层和金属栓塞大抵上保持完整。牺牲层的移除在第一介电层和第二介电层之间留下气隙。在一些示例中,在气隙形成后,可以沉积密封层(例如132)。此密封层可包含氮化硅。密封层可以使用ALD制程沉积,如等离子体辅助ALD(PE-ALD)制程。密封层将顶部的气隙关闭。此气隙提供更好的装置性能,因为它减少了金属栓塞和金属栅极装置之间的寄生电容。
在一些实施例中,公开了一种半导体结构的形成方法,包括:在基板的背侧上执行第一蚀刻制程,以露出虚设接触结构;执行第一沉积制程以在虚设接触结构周围沉积第一介电层;执行第二沉积制程以在第一介电层上沉积氧化层;移除虚设接触结构以形成沟槽;在沟槽的多个侧壁上沉积牺牲层;在牺牲层上沉积第二介电层;以导电材料填充沟槽;以及移除牺牲层以在第一介电层及第二介电层之间形成空气间隔物。
在一实施例中,第一介电层包含氮化硅。在一实施例中,第二介电层包含氮化硅。在一实施例中,牺牲层包含硅。在一实施例中,通过热沉积制程来形成牺牲层。在一实施例中,移除虚设接触结构的步骤包含干式蚀刻制程。在一实施例中,在空气间隔物上形成密封件。在一实施例中,密封件包含介电材料。在一实施例中,在填充沟槽前,植入掺杂物至在沟槽的底部露出的源极/漏极区。
在一些实施例中,公开了一种半导体结构的形成方法,包括:执行蚀刻制程,以从基板的背侧移除虚设接触结构以及在沟槽的底部露出源极/漏极区;在沟槽的多个侧壁上沉积牺牲层;在牺牲层上沉积介电层;以导电材料填充沟槽;以及移除牺牲层。
在一实施例中,在牺牲层上沉积介电层之后,执行干式蚀刻制程,以从沟槽的底部移除介电层的部分。在一实施例中,在沉积牺牲层之前,圆化沟槽的顶角。在一实施例中,在移除虚设接触结构之前,从虚设接触结构周围移除硅材料。在一实施例中,在移除虚设接触结构之前,在虚设接触结构周围形成氧化层。在一实施例中,移除牺牲层的步骤留下邻近介电层的气隙。在一实施例中,沉积密封件以关闭气隙。在一实施例中,其中通过化学气相沉积制程来形成牺牲层。
在一些实施例中,公开了一种半导体结构,包括:基板,具有前侧及背侧;晶体管,形成在基板的前侧上,晶体管包含源极/漏极区;接触件,从源极/漏极区的底部延伸至基板的背侧;以及第一介电层,沿着接触件的多个侧面设置;气隙,设置于第一介电层及第二介电层之间。
在一实施例中,在气隙的底部上形成密封结构。在一实施例中,第一介电层包含氮化硅。
以上概述数个实施例的特征,以使本发明所属技术领域中具有通常知识者可以更加理解本发明实施例的观点。本发明所属技术领域中具有通常知识者应理解,可轻易地以本发明实施例为基础,设计或修改其他制程和结构,以达到与在此介绍的实施例相同的目的及/或优势。在本发明所属技术领域中具有通常知识者也应理解,此类等效的结构并无悖离本发明的精神与范围,且可在不违背本发明的精神和范围下,做各式各样的改变、取代和替换。因此,本发明的保护范围当视后附的权利要求所界定为准。

Claims (1)

1.一种半导体结构的形成方法,包括:
在一基板的一背侧上执行一第一蚀刻制程,以露出一虚设接触结构;
执行一第一沉积制程以在该虚设接触结构周围沉积一第一介电层;
执行一第二沉积制程以在该第一介电层上沉积一氧化层;
移除该虚设接触结构以形成一沟槽;
在该沟槽的多个侧壁上沉积一牺牲层;
在该牺牲层上沉积一第二介电层;
以一导电材料填充该沟槽;以及
移除该牺牲层以在该第一介电层及该第二介电层之间形成一空气间隔物。
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