CN109427777A - 具有倾斜侧壁的切割金属栅极 - Google Patents

具有倾斜侧壁的切割金属栅极 Download PDF

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Publication number
CN109427777A
CN109427777A CN201810513503.7A CN201810513503A CN109427777A CN 109427777 A CN109427777 A CN 109427777A CN 201810513503 A CN201810513503 A CN 201810513503A CN 109427777 A CN109427777 A CN 109427777A
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fin
metal gate
side wall
sidewall
substrate
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CN109427777B (zh
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蔡雅怡
賴俊良
古淑瑗
陈嘉仁
张铭庆
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体器件包括衬底，从衬底向外突出的第一鳍和第二鳍以及分别设置在第一鳍和第二鳍上方的第一和第二高k金属栅极(HK MG)。从俯视图看，第一鳍和第二鳍沿第一方向纵向布置，第一和第二HK MG沿着垂直于第一方向的第二方向纵向布置，并且第一和第二HK MG沿着第二方向对准。在沿着第二方向切割的截面图中，第一HK MG具有从顶部至底部朝向第二HK MG倾斜的第一侧壁，并且第二HK MG具有从顶部至底部朝向第一HK MG倾斜的第二侧壁。也公开了用于生产这种半导体器件的方法。本发明实施例涉及具有倾斜侧壁的切割金属栅极。

Description

具有倾斜侧壁的切割金属栅极
技术领域
本发明实施例涉及具有倾斜侧壁的切割金属栅极。
背景技术
半导体集成电路(IC)产业经历了指数增长。IC材料和设计中的技术进步已经产生了多代IC，其中，每一代IC都比上一代IC具有更小和更复杂的电路。在IC演化过程中，功能密度(即，每芯片面积的互连器件的数量)已经普遍增大，而几何尺寸(即，可以使用制造工艺产生的最小组件或线)已经减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。这种按比例缩小也增加了处理和制造IC的复杂性。
在一些IC设计中，随着技术节点缩小，实现的一个优势为：在部件尺寸缩小的情况下，用金属栅极来替换典型的多晶硅栅极以提高器件性能。形成金属栅极的一个工艺被称为替换栅极或者“后栅极”工艺，其中，“最后”制造金属栅极，这允许降低随后工艺的数量，包括在形成栅极之后必须实施的高温处理。然后，具有实施这些IC制造工艺的挑战，特别是对于先进工艺节点中的按比例缩小的IC部件，诸如N10，N5等。一个挑战是在替换之后，如何有效地隔离金属栅极。
发明内容
根据本发明的一些实施例，提供了一种半导体器件，包括：衬底；第一鳍和第二鳍，从衬底向外突出；以及第一高k金属栅极(HK MG)和第二高k金属栅极，其中，所述第一高k金属栅极设置在所述第一鳍上方，并且所述第二高k金属栅极设置在所述第二鳍上方，其中，从俯视图看，所述第一鳍和所述第二鳍沿第一方向纵向布置，所述第一高k金属栅极和所述第二高k金属栅极沿着垂直于所述第一方向的第二方向纵向布置，并且所述第一高k金属栅极和所述第二高k金属栅极沿着所述第二方向对准，其中，在沿着所述第二方向切割的截面图中，所述第一高k金属栅极具有从顶部至底部朝向所述第二高k金属栅极倾斜的第一侧壁，并且所述第二高k金属栅极具有从顶部至底部朝向第一高k金属栅极倾斜的第二侧壁。
根据本发明的另一些实施例，还提供了一种半导体器件，包括：衬底；第一鳍和第二鳍，从所述衬底向外突出；第三鳍和第四鳍，从所述衬底向外突出；第一高k金属栅极(HKMG)，设置在所述第一鳍和所述第二鳍上方；以及第二高k金属栅极，设置在所述第三鳍和所述第四鳍上方，其中，从俯视图看，所述第一鳍、所述第二鳍、所述第三鳍和所述第四鳍沿着第一方向纵向布置，所述第一高k金属栅极和所述第二高k金属栅极沿着垂直于所述第一方向的第二方向纵向对准，其中，在沿着所述第二方向切割的截面图中，所述第一高k金属栅极具有第一侧壁，所述第二高k金属栅极具有与所述第一侧壁相对的第二侧壁，所述第一侧壁和所述第二侧壁与所述衬底的法线形成两个角度，其中，每个所述角度小于其中，AR是所述第一高k金属栅极的高度与所述第一侧壁和所述第二侧壁的各自的顶部之间的距离的比率，以及其中，所述第一侧壁和所述第二侧壁之间的空间被一种或多种介电材料完全占据。
根据本发明的又一些实施例，还提供了一种形成半导体器件的方法，包括：提供结构，所述结构具有：衬底，鳍，从所述衬底向外突出，以及隔离结构，位于所述衬底上方和相邻的鳍之间，其中，所述隔离结构低于所述鳍；在所述隔离结构和所述鳍上方形成栅极，其中，所述栅极包括高k介电层和导电层；以及对两个相邻鳍之间的栅极执行蚀刻工艺以暴露所述隔离结构，从而将所述栅极分成至少第一部分和第二部分，其中，控制蚀刻工艺以产生所述第一部分的第一侧壁和相对的所述第二部分的第二侧壁，其中，所述第一和所述第二侧壁提供宽于底部开口的顶部开口。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A示出了根据本发明的各个方面的利用切割金属栅极工艺实施的半导体结构的顶视图。
图1B和图1C示出了根据实施例的图1A中的结构的截面图。
图2A和图2B示出了根据本发明的各个方面的形成在图1A至图1C中示出的结构的方法的流程图。
图3，图4A，图4B，图5，图6A，图6B，图7A，图7B，图8，图9，图10，图11和图12示出了根据实施例的根据图2A至图2B的方法的制造工艺期间的半导体结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。此外，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
本公开通常涉及半导体器件和制造方法，并且更具体地涉及使用切割金属栅极工艺来制造半导体器件。切割金属栅极工艺是指在以金属栅极(例如，高k金属栅极或HK MG)替换伪栅极结构(例如，多晶硅栅极)之后，切割金属栅极(例如，通过蚀刻工艺)以将金属栅分成两个或更多个部分的制造工艺。每个部分用作单个晶体管的金属栅极。随后将隔离材料填充到金属栅极的相邻部分之间的沟槽中。这些沟槽在本公开中被称为切割金属栅极沟槽或CMG沟槽。随着器件继续按比例缩小，CMG沟槽的高宽比(定义为CMG沟槽的高度与CMG沟槽的宽度的比率)通常会增加。当CMG沟槽具有垂直侧壁时，这使得使用隔离材料完全填充CMG沟槽变得更加困难。如果在该隔离材料中存在间隙或空隙，则可能导致电路缺陷，例如短路。本公开的目的是设计一种切割金属栅极方法，以便产生具有锥形轮廓的CMG沟槽，其中，CMG沟槽的顶部开口比其底部开口更宽。换句话说，如此产生的CMG沟槽具有倾斜侧壁。这种锥形轮廓有助于将隔离材料填充到CMG沟槽中以消除隔离材料中的间隙或空隙。这种锥形轮廓对于具有诸如5至10的高高宽比的CMG沟槽特别有用。
图1A示出了半导体器件(或半导体结构)100的俯视图。图1B示出了沿着图1A的B-B线截取的器件100的截面图。参考图1A和1B，器件100包括衬底102，从衬底102向外突出的多个鳍104，位于衬底102上方和鳍104之间的隔离结构106以及设置在鳍104以及隔离结构106上方的多个栅极堆叠件112。每个栅极堆叠件112包括高k介电层108和位于高k介电层108上方的导电层110。导电层110包括一层或多层金属材料。因此，每个栅极堆叠件112也被称为高k金属栅极(或HK GM)112。栅极堆叠件112可以进一步包括在高k介电层108下面的界面层(未示出)。
从俯视图看，鳍104沿着X方向纵向布置，并且栅极堆叠件112沿着通常垂直于X方向的Y方向纵向布置。此外，鳍104通常彼此平行，并且栅极堆叠件112通常彼此平行。器件100还包括沿X方向纵向布置的介电层114，并且介电层114将每片栅极堆叠件112分成至少两个部分。栅极堆叠件112的每个部分与相应的鳍104接合以形成单独的FinFET晶体管。器件100还包括设置在栅极堆叠件112和介电层114上方的一个或多个介电层116。下面进一步描述器件100的组件。
在本实施例中，衬底102是硅衬底。可选地，衬底102可以包括另一种元素半导体，诸如锗；包括碳化硅，砷化镓，磷化镓，磷化铟，砷化铟和锑化铟的化合物半导体；包括硅锗，磷化镓砷，磷化铝铟，砷化铝镓，砷化镓铟，磷化镓铟和磷砷化镓铟的合金半导体；或它们的组合。
鳍104可以包括一种或多种半导体材料，诸如硅，锗，碳化硅，砷化镓，磷化镓，磷化铟，砷化铟，锑化铟，硅锗，磷化镓砷，磷化铝铟，铝砷化镓，砷化镓铟，磷化铟镓和磷砷化镓铟。在一个实施例中，鳍104可以包括两种不同半导体材料的交替堆叠层，诸如交替堆叠的硅和硅锗层。另外，鳍104可以额外地包括用于改进器件100的性能的掺杂剂。例如，鳍104可以包括诸如磷或砷的n型掺杂剂，或者诸如硼或铟的p型掺杂剂。
隔离结构106可以包括氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其它合适的绝缘材料。隔离结构106可以是浅沟槽隔离(STI)部件。诸如场氧化物、硅的局部氧化(LOCOS)的其他隔离结构，和/或其他合适的结构是可能的。隔离结构106可以包括多层结构，例如具有与鳍104相邻的一个或多个热氧化物衬垫层。
高k介电层108可以包括一种或多种高k介电材料(或一层或多层高k介电材料)，诸如氧化铪硅(HfSiO)，氧化铪(HfO2)，氧化铝(Al2O3)，氧化锆(ZrO2)，氧化镧(La2O3)，氧化钛(TiO2)，氧化钇(Y2O3)，钛酸锶(SrTiO3)或它们的组合。
导电层110包括一个或多个金属层，诸如功函金属层，导电阻挡层和金属填充层。取决于器件的类型(PFET或NFET)，功函金属层可以是p型或n型功函层。p型功函层包含具有足够大的有效功函数的金属，选自但不限于氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)或它们的组合。n型功函层包含具有足够低的有效功函数的金属，选自但不限于钛(Ti)、铝(Al)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化钽硅(TaSiN)、氮化硅钛(TiSiN)或它们的组合。金属填充层可以包括铝(Al)，钨(W)，钴(Co)和/或其他合适的材料。
介电层114可以包括一种或多种介电材料，诸如氮化硅、氧化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)，低k介电材料和/或其他合适的绝缘材料。特别地，介电层114的与栅极堆叠件112物理接触的部分包括不与栅极堆叠件112的金属材料反应的介电材料。例如，在一个实施例中，介电层114的该部分包括氮化硅。
介电层116可以包括一种或多种介电材料，诸如氮化硅、氧化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其他合适的绝缘材料。
参照图1C，进一步说明器件100。在图1C中，为了说明切割金属栅极(CMG)沟槽113的细节，省略了介电层114和116。在该截面图中，CMG沟槽113将栅极堆叠件112分离成左侧部分112L和右侧部分112R。左侧部分112L接合两个鳍104以形成晶体管，并且右侧部分112R接合两个其他鳍104以形成另一个晶体管。在各种实施例中，左侧(或右侧)部分可以接合任何数量的鳍104以形成晶体管。左侧部分112L具有侧壁SW1，该侧壁从顶部至底部朝向右侧部分112R倾斜。侧壁SW1与Z方向(衬底102的法线)形成角度θ1。右侧部分112R具有侧壁SW2，侧壁SW2从顶部至底部朝向左侧部分112L倾斜。侧壁SW2与Z方向形成角度θ2。CMG沟槽113延伸到隔离结构106中以确保栅极堆叠件112的左侧部分和右侧部分彼此完全隔离。当沿Z方向从栅极堆叠件112和隔离结构106之间的界面到栅极堆叠件112的顶面测量时，栅极堆叠件112具有的高度H1。CMG沟槽113在栅极堆叠件112的顶面处具有顶部开口，以及在栅极堆叠件112与隔离结构106之间的界面处具有底部开口。顶部开口具有宽度W1，并且底部开口具有宽度W2。CMG沟槽113的高宽比定义为H1/W1。
在一个实施例中，高度H1可以在80至140nm的范围内，并且顶部开口宽度W1可以在从16至30nm的范围内。CMG沟槽113的高宽比可以介于3至10的范围内，诸如4至8，或5至7的范围内。对于高高宽比，如果CMG沟槽113具有垂直侧壁(典型地，干蚀刻金属膜产生垂直侧壁)，则介电层114难以完全填充CMG沟槽113，因为现有沉积技术通常不能很好地沉积在深而窄的沟槽的底部。在本实施例中，CMG沟槽113被设计和加工成具有锥形轮廓，即具有W1>W2。实验表明，这种锥形轮廓改善了介电层114在CMG沟槽113内的填充。
在各种实施例中，角度θ1和θ2中的每一个大于0°(因此，“倾斜”侧壁)并且小于其中AR是CMG沟槽113的高宽比，在本实施例中等于H1/W1。如果两个角度θ1和θ2均等于则CMG沟槽113几乎不会到达隔离结构106。为了确保栅极堆叠件112的左侧部分和右侧部分之间的隔离，两个角度θ1和θ2被设计为小于在一个实施例中，CMG沟槽113被设计成使得角度θ1和θ2中的每一个在从1°至10°(或者度)的范围内，诸如从1.5°至7°或者从2°至5°的范围内。已经发现这种侧壁角度对于将介电材料114填充到具有高高宽比的CMG沟槽113中是有帮助和有效的。在实施例中，两个角度θ1和θ2可以彼此相等或不相等。
在一些实施例中，比值W2/W1被设计为从0.4到0.8，例如从0.5到0.7，以确保介电层114(图1B)完全隔离栅极堆叠件112的左侧部分和右侧部分并且确保侧壁角度θ1和θ2足够大以便于薄膜沉积。实际上，侧壁角度θ1和θ2可以从W1，W2和H1的值推导出。
图2A和图2B示出了根据实施例的用于形成半导体器件100的方法200的流程图。方法200仅仅是一个示例，并不意图将本公开限制在权利要求中明确记载的范围之外。可以在方法200之前，期间和之后提供额外的操作，并且可以替换、消除或重排所描述的一些操作以用于该方法的另外的实施例。下面结合图3至图12描述方法200。图3-12示出了根据方法200的制造步骤期间半导体器件100的各种截面图。
在操作202处，方法200(图2A)提供或被提供为具有器件结构100，如图3所示，器件结构100具有衬底102，突出于衬底102之外的鳍104以及位于衬底102上方和鳍104之间的隔离结构106。在上文中已经参照图1A-1C论述了衬底102、鳍104和隔离结构106的各种材料。
在一个实施例中，衬底102可以是晶圆，例如硅晶圆。可以通过在衬底102的整个区域上方外延生长一个或多个半导体层，然后将其图案化以形成单独的鳍104来形成鳍104。鳍104可以通过任何合适的方法来图案化。例如，可以使用一种或多种光刻工艺(包括双重图案化或多重图案化工艺)来图案化鳍104。通常，双重图案化或多重图案化工艺结合了光刻和自对准工艺，从而允许创建具有例如比使用单一直接光刻工艺可获得的间距小的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层并使用光刻工艺进行图案化。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，然后剩余的间隔件或芯轴可以用于通过蚀刻初始外延半导体层来图案化鳍104。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其他合适的工艺。例如，干蚀刻工艺可以使用含氧气体、含氟气体(例如CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如HBr和/或CHBR3)含碘气体、其他合适的气体和/或等离子体和/或它们的组合。例如，湿蚀刻工艺可以包括在稀释的氢氟酸(DHF)中蚀刻；氢氧化钾(KOH)溶液；氨；包含氢氟酸(HF)、硝酸(HNO3)和/或乙酸(CH3COOH)的溶液；或其他合适的湿蚀刻剂。
隔离结构106可以通过一种或多种沉积和蚀刻方法形成。沉积方法可以包括热氧化、化学氧化和化学气相沉积(CVD)，诸如可流动CVD(FCVD)。蚀刻方法可以包括干蚀刻、湿蚀刻和化学机械平坦化(CMP)。
在操作204处，诸如图4A和4B所示，方法200(图2A)形成接合鳍104的伪(或临时)栅极结构。图4A示出沿着图1A的1-1线切割的器件100的截面图，图4B示出了沿着图1A的B-B线切割的器件100的截面图。参照图4A和图4B，伪栅极结构包括界面层150，电极层152和两个硬掩模层154和156。操作204还在伪栅极结构的侧壁上形成栅极间隔件160。
界面层150可以包括诸如氧化硅层(例如，SiO2)或氮氧化硅(例如，SiON)的介电材料，并且可以通过化学氧化，热氧化，原子层沉积(ALD)，CVD和/或其他合适的方法形成。栅电极152可以包括多晶硅(poly-Si)，并且可以通过诸如低压化学气相沉积(LPCVD)和等离子体增强CVD(PECVD)的合适沉积工艺形成。每个硬掩模层154和156可以包括一层或多层诸如氧化硅和/或氮化硅的介电材料，并且可以通过CVD或其他合适的方法形成。可以通过光刻和蚀刻工艺来图案化各个层150、152、154和156。栅极间隔件160可以包括诸如氧化硅，氮化硅，氮氧化硅，碳化硅，其他介电材料或它们的组合的介电材料，并且可以包括一个或多个材料层。可以通过在隔离结构106，鳍104和伪栅极结构150/152/154/156上方沉积间隔材料作为毯式层来形成栅极间隔件160。然后通过各向异性蚀刻工艺蚀刻间隔件材料以暴露隔离结构106、硬掩模层156和鳍104的顶面。间隔件材料的位于伪栅极结构150/152/154/156的侧壁上的部分变成栅极间隔件160。相邻的栅极间隔件160提供了暴露器件100的S/D区中的鳍104的沟槽158。
在操作206处，方法200(图2A)形成各种部件，包括源极/漏极(或S/D)部件162、接触蚀刻停止层(CESL)164、层间介电(ILD)层166以及位于ILD层166上方的保护性介电层168，如图5所示，其是沿着图1A的1-1线的器件100的截面图。例如，操作206可以在暴露于沟槽158中的鳍104内蚀刻凹槽，并且在凹槽中外延生长半导体材料。如图5所示，半导体材料可以升高到鳍104的顶面之上。操作206可以形成分别用于NFET和PFET器件的S/D部件162。例如，操作206可以形成具有用于NFET器件的n型掺杂的硅或用于PFET器件的p型掺杂的硅锗的S/D部件162。此后，操作206可以将CESL164和ILD层166沉积在S/D部件162上方。CESL164可以包括氮化硅，氮氧化硅，具有氧(O)或碳(C)元素的氮化硅和/或其他材料；并且可以通过CVD、PVD(物理气相沉积)、ALD或其他合适的方法形成。ILD层166可以包括原硅酸四乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅，诸如硼磷硅酸盐玻璃(BPSG)，熔融石英玻璃(FSG)，磷硅酸盐玻璃(PSG)，硼掺杂的硅玻璃(BSG)和/或其他合适的介电材料。ILD层166可以通过PECVD、FCVD或其他合适的方法形成。随后，操作206可回蚀ILD层166并沉积保护性介电层168，保护性介电层168可包含诸如氮化硅的氮化物，以在随后的蚀刻工艺期间保护ILD层166。操作206执行一个或多个CMP工艺以平坦化器件100的顶面，去除硬掩模层154和156，并暴露电极层152。
在操作208处，方法200(图2A)移除伪栅极结构以形成栅极沟槽169，诸如图6A和图6B所示，图6A和图6B是沿着图1A的1-1和B-B线的器件100的截面图。栅极沟槽169暴露鳍104的表面和栅极间隔件160的侧壁表面。操作208可以包括对电极层152和界面层150中的材料具有选择性的一个或多个蚀刻工艺。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻或其他合适的蚀刻方法。
在操作210处，方法200(图2A)在栅极沟槽169中沉积高-k金属栅极112，如图7A和图7B所示，图7A和图7B分别是沿着图1A的1-1和B-B线的器件100的截面图。高k金属栅极112包括高k介电层108和导电层110。高k金属栅极112还可以包括在高k介电层108和鳍104之间的界面层(例如，SiO2)(未示出)。界面层可以使用化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)和/或其他合适的方法来形成。已经参考图1A至图1C论述了高k介电层108和导电层110的材料。高k介电层108可以包括一层或多层高k介电材料，并且可以使用CVD、ALD和/或其他合适的方法来沉积。导电层110可以包括一个或多个功函金属层和金属填充层，并且可以使用诸如CVD、PVD、镀和/或其他合适工艺的方法来沉积。
在操作212处，方法200(图2B)在器件100上方形成一个或多个硬掩模层，诸如图8所示，图8是在这一制造阶段的沿着图1A的B-B线截取的器件100的截面图。在这个实例中，示出了两个硬掩模层170和172。在一个实施例中，硬掩模层170包括氮化钛，而硬掩模层172包括氮化硅。在本实施例中，选择用于硬掩模层170的材料以具有与导电层110的良好粘附性，但不与导电层110反应。硬掩模层170和172可以使用CVD、PVD、ALD、或其他合适的方法沉积。
在操作214处，方法200(图2B)将一个或多个硬掩模层图案化以形成图案化的硬掩模，如图9中所示，图9是在该制造阶段沿着图1A的B-B线截取的器件100的截面图。参考图9，图案化(例如，蚀刻)硬掩模层170和172以提供暴露导电层110的开口113。在示例中，操作214可以通过光刻胶涂布、曝光、曝光后烘烤和显影在硬掩模层170和172上方形成图案化的光刻胶。图案化的光刻胶对应于图1A中的介电层114的图案。然后，操作214使用图案化的光刻胶作为蚀刻掩模来蚀刻硬掩模层170和172，以形成开口113。蚀刻工艺可以包括湿蚀刻、干蚀刻、反应离子蚀刻或其他合适的蚀刻方法。之后例如通过光刻胶剥离去除图案化的光刻胶。应注意的是，硬掩模层170/172处的开口113的侧壁是垂直的或几乎垂直的。
在操作216处，方法200(图2B)穿过开口113蚀刻高k金属栅极112。图案化的硬掩模层170和172保护高k金属栅极112的其余部分免受蚀刻工艺的影响。参考图10，操作216将开口113向下延伸并穿过高k金属栅极112并进入隔离结构106内。特别地，操作216控制蚀刻工艺以产生倾斜侧壁SW1和SW2，如上参考图1C论述的。蚀刻工艺可以使用一种或多种蚀刻剂或蚀刻剂的混合物蚀刻高k金属栅极112中的各层。
在示例性实施例中，导电层110包括TiSiN、TaN、TiN、W或它们的组合。为了蚀刻这样的导电层和高k介电层108，操作216可以利用具有氯、氟、溴、氧、氢、碳或它们的组合的原子的蚀刻剂来施加干蚀刻工艺。例如，蚀刻剂可以具有Cl2、O2、含碳和氟的气体、含溴和氟的气体以及含碳-氢和氟的气体的气体混合物。用这种气体混合物蚀刻高k金属栅极112倾向于在蚀刻工艺期间产生一些沉积在CMG沟槽113的侧壁上的聚合物(或聚合物材料)。这些聚合物减缓了朝向侧壁的蚀刻，由此产生了倾斜的侧壁SW1和SW2。在一个实例中，蚀刻剂包括Cl2、O2、CF4、BCl3和CHF3的气体混合物。通过调节气体混合物中的BCl3的量，操作216可以控制沉积在CMG沟槽113的侧壁上的BOxNy聚合物的量，从而控制侧壁SW1和SW2的斜率。例如，操作216可以增加气体混合物中BCl3的比率，以增加沉积的BOxNy聚合物的量。可选地或另外地，通过调节气体混合物中CHF3的量，操作216可以控制沉积在CMG沟槽113的侧壁上的TiFx和NFx聚合物的量，从而控制侧壁SW1和SW2的斜率。例如，操作216可以增加气体混合物中CHF3的比率，以增加沉积的TiFx和NFx聚合物的量。更进一步地，操作216可以调节气体混合物中碳与氟的比率，以便控制沉积在侧壁SW1和SW2上的CxFy聚合物的量。例如，操作216可以用CxFy(其中x：y大于1：4(例如，C4F6))代替CF4以便增加沉积的CxFy聚合物的量。上面讨论的蚀刻剂和蚀刻工艺可以应用于适用于导电层110和高k电介质108的各种材料，但不限于上面讨论的示例性材料TiSiN，TaN，TiN和W。
更进一步地，操作216还可以控制蚀刻偏置电压，作为控制如上所述的蚀刻剂的补充或替代。较高的蚀刻偏置电压(沿着Z方向)倾向于在CMG沟槽113中产生更垂直的侧壁，而低蚀刻偏置电压通过蚀刻剂减少向下的离子轰击，导致倾斜的侧壁。在本实施例中，操作216可以施加50至100V的范围内的蚀刻偏压。此外，在本实施例中，操作216可以在5至20毫托的压力，100至200W的能量以及75至125摄氏度的温度下执行蚀刻工艺。蚀刻偏置电压、蚀刻压力、蚀刻能量和蚀刻温度的各种其他值也是可能的。而且，为了确保栅极堆叠件112的左侧部分和右侧部分之间的隔离，操作216执行一些过蚀刻以将CMG沟槽113延伸至隔离结构106内。小心控制这种过蚀刻以不暴露衬底102。
如图11所示，在操作218，方法200(图2B)用一种或多种介电材料填充CMG沟槽113以形成介电层114。由于栅极堆叠件112的侧壁(图10的SW1和SW2)含有金属材料，因此至少介电层114的外部(其与侧壁SW1和SW2直接接触)不含诸如氧的活性化学成分。在本实施例中，介电层114的外部包含氮化硅且不含氧或氧化物。应注意的是，由于高k介电层108包括氧，因此一些氧含量可最终扩散到介电层114的一些部分内。然而，这种扩散的氧通常限于介电层114的下部。在一些实施例中，介电层114可以在其内部包括一些氧化物。可选地，介电层114可以包括一个均匀的氮化硅层并且不含氧化物。可以使用CVD、PVD、ALD或其他合适的方法来沉积介电层114。在本实施例中，使用ALD沉积介电层114以确保其完全填充CMG沟槽113。
在操作220处，方法200(图2B)执行一个或多个CMP工艺以去除多余的介电层114(位于CMG沟槽113外侧的部分)和硬掩模层172和170。在一个实施例中，当通过CMP工艺去除硬掩模层172时，硬掩模层170用作CMP停止层。在另一个实施例中，操作220可以将导电层110(以及介电层114)凹进到期望的HK MG高度。所得到的结构如图12所示。
在操作222处，方法200(图2B)执行进一步的步骤以完成器件100的制造。例如，方法200可形成电连接S/D部件162(图7A)和栅极堆叠件112的接触件和通孔，并形成连接各种晶体管的金属互连件以形成完整的IC。
尽管不打算限制，但是本公开的一个或多个实施例为半导体器件及其形成提供许多益处。例如，本公开的实施例提供了具有倾斜侧壁的切割金属栅极沟槽。倾斜的侧壁改进了介电材料在可能具有高高宽比的沟槽内的填充性。这对小尺寸器件特别有用。此外，本公开的实施例可以容易地集成到现有的半导体制造工艺中。
在一个示例性方面中，本发明涉及一种半导体器件。器件包括衬底，从衬底向外突出的第一鳍和第二鳍；以及第一高k金属栅极(HK MG)和第二HK MG，其中，第一HK MG设置在第一鳍上方，并且第二HK MG设置在第二鳍上方。从俯视图看，第一鳍和第二鳍沿第一方向纵向布置，第一和第二HK MG沿着大体上垂直于第一方向的第二方向纵向布置，并且第一和第二HK MG沿着第二方向对准。在沿着第二方向切割的截面图中，第一HK MG具有从顶部至底部朝向第二HK MG倾斜的第一侧壁，并且第二HK MG具有从顶部至底部朝向第一HK MG倾斜的第二侧壁。
在器件的实施例中，第一侧壁与衬底的法线形成第一角度，并且第一角度在1至10度的范围内。在进一步的实施例中，第一角度在2至5度的范围内。在另一实施例中，第二侧壁与衬底的法线形成第二角度，并且第二角度在1至10度的范围内。例如，第二角度在2至5度的范围内。
在实施例中，器件还包括横向地位于第一侧壁和第二侧壁之间的介电材料。在进一步的实施例中，介电材料完全填充第一侧壁和第二侧壁之间的空间。
在另一实施例中，第一距离介于第一侧壁和第二侧壁的相应顶部之间，第二距离介于第一侧壁和第二侧壁的相应底部之间，并且第二距离与第一距离的比率在从0.4到0.8的范围内。在进一步的实施例中，第二距离与第一距离的比率在从0.5至0.7的范围内。
在器件的实施例中，第一HK MG的高度与第一侧壁和第二侧壁的相应顶部之间的距离的比率在从3到10的范围内。例如，比率在从5至7的范围内。在另一实施例中，器件还包括位于第一鳍和第二鳍之间以及第一和第二HK MG下方的隔离结构。
在另一示例性方面中，本发明涉及一种半导体器件。器件包括衬底；从衬底向外突出的第一鳍和第二鳍；从衬底向外突出的第三鳍和第四鳍；设置在第一鳍和第二鳍上方的第一高k金属栅极(HK MG)；以及设置在第三鳍和第四鳍上方的第二高k金属栅极。从俯视图看，第一鳍、第二鳍、第三鳍和第四鳍沿着第一方向纵向布置，第一和第二HK MG沿着大体上垂直于第一方向的第二方向纵向对准。在沿着第二方向切割的截面图中，第一HK MG具有第一侧壁，第二HK MG具有与第一侧壁相对的第二侧壁，第一侧壁和第二侧壁与衬底的法线形成两个角度，其中，每个角度小于其中，AR是第一HK MG的高度与第一侧壁和第二侧壁的各自的顶部之间的距离的比率。第一侧壁和第二侧壁之间的空间被一种或多种介电材料完全占据。在一些实施例中，两个角度的每个介于1.5至7度的范围内。
在器件的实施例中，在截面图中，第一距离介于第一侧壁和第二侧壁的相应顶部之间，第二距离介于第一侧壁和第二侧壁的相应底部之间，并且第二距离与第一距离的比率在从0.4到0.8的范围内。在器件的另一实施例中，AR介于4至8的范围内。
在又一示例性实施例中，本发明涉及一种方法。该方法包括提供结构，结构具有：衬底，从衬底向外突出的鳍，以及位于衬底上方和相邻的鳍之间的隔离结构，其中，隔离结构低于鳍。该方法还包括：在隔离结构和鳍上方形成栅极，其中，栅极包括高k介电层和导电层；以及对两个相邻鳍之间的栅极执行蚀刻工艺以暴露隔离结构，从而将栅极分成至少第一部分和第二部分。控制蚀刻工艺以产生第一部分的第一侧壁和相对的第二部分的第二侧壁。第一和第二侧壁提供宽于底部开口的顶部开口。
在方法的实施例中，蚀刻工艺包括利用介于50V到100V范围的偏置电压的干蚀刻。在方法的实施例中，导电层包括钨(W)，并且蚀刻工艺使用含有CxFy的气体混合物，其中x：y大于1：4。
在方法的实施例中，蚀刻工艺包括利用Cl2、O2、含碳和氟的气体、含溴和氟的气体以及含碳-氢和氟的气体的气体混合物进行干蚀刻。在方法的另一实施例中，蚀刻工艺包括利用具有氯、氟、溴、氧、氢和碳的原子的蚀刻剂进行干蚀刻。
根据本发明的一些实施例，提供了一种半导体器件，包括：衬底；第一鳍和第二鳍，从衬底向外突出；以及第一高k金属栅极(HK MG)和第二高k金属栅极，其中，所述第一高k金属栅极设置在所述第一鳍上方，并且所述第二高k金属栅极设置在所述第二鳍上方，其中，从俯视图看，所述第一鳍和所述第二鳍沿第一方向纵向布置，所述第一高k金属栅极和所述第二高k金属栅极沿着垂直于所述第一方向的第二方向纵向布置，并且所述第一高k金属栅极和所述第二高k金属栅极沿着所述第二方向对准，其中，在沿着所述第二方向切割的截面图中，所述第一高k金属栅极具有从顶部至底部朝向所述第二高k金属栅极倾斜的第一侧壁，并且所述第二高k金属栅极具有从顶部至底部朝向第一高k金属栅极倾斜的第二侧壁。
在上述半导体器件中，所述第一侧壁与所述衬底的法线形成第一角度，并且所述第一角度在1至10度的范围内。
在上述半导体器件中，所述第一角度在2至5度的范围内。
在上述半导体器件中，所述第二侧壁与所述衬底的法线形成第二角度，并且所述第二角度在1至10度的范围内。
在上述半导体器件中，所述第二角度在2至5度的范围内。
在上述半导体器件中，还包括横向地位于所述第一侧壁和所述第二侧壁之间的介电材料。
在上述半导体器件中，所述介电材料完全填充所述第一侧壁和所述第二侧壁之间的空间。
在上述半导体器件中，第一距离介于所述第一侧壁和所述第二侧壁的相应顶部之间，第二距离介于所述第一侧壁和所述第二侧壁的相应底部之间，并且所述第二距离与所述第一距离的比率在从0.4到0.8的范围内。
在上述半导体器件中，所述第二距离与所述第一距离的比率在从0.5至0.7的范围内。
在上述半导体器件中，所述第一高k金属栅极的高度与所述第一侧壁和所述第二侧壁的相应顶部之间的距离的比率在从3到10的范围内。
在上述半导体器件中，所述比率在从5至7的范围内。
在上述半导体器件中，还包括：隔离结构，位于所述第一鳍和所述第二鳍之间以及所述第一高k金属栅极和所述第二高k金属栅极下方。
根据本发明的另一些实施例，还提供了一种半导体器件，包括：衬底；第一鳍和第二鳍，从所述衬底向外突出；第三鳍和第四鳍，从所述衬底向外突出；第一高k金属栅极(HKMG)，设置在所述第一鳍和所述第二鳍上方；以及第二高k金属栅极，设置在所述第三鳍和所述第四鳍上方，其中，从俯视图看，所述第一鳍、所述第二鳍、所述第三鳍和所述第四鳍沿着第一方向纵向布置，所述第一高k金属栅极和所述第二高k金属栅极沿着垂直于所述第一方向的第二方向纵向对准，其中，在沿着所述第二方向切割的截面图中，所述第一高k金属栅极具有第一侧壁，所述第二高k金属栅极具有与所述第一侧壁相对的第二侧壁，所述第一侧壁和所述第二侧壁与所述衬底的法线形成两个角度，其中，每个所述角度小于其中，AR是所述第一高k金属栅极的高度与所述第一侧壁和所述第二侧壁的各自的顶部之间的距离的比率，以及其中，所述第一侧壁和所述第二侧壁之间的空间被一种或多种介电材料完全占据。
在上述半导体器件中，在所述截面图中，第一距离介于所述第一侧壁和所述第二侧壁的相应顶部之间，第二距离介于所述第一侧壁和所述第二侧壁的相应底部之间，并且所述第二距离与所述第一距离的比率在从0.4到0.8的范围内。
在上述半导体器件中，所述AR在从4到8的范围内。
根据本发明的又一些实施例，还提供了一种形成半导体器件的方法，包括：提供结构，所述结构具有：衬底，鳍，从所述衬底向外突出，以及隔离结构，位于所述衬底上方和相邻的鳍之间，其中，所述隔离结构低于所述鳍；在所述隔离结构和所述鳍上方形成栅极，其中，所述栅极包括高k介电层和导电层；以及对两个相邻鳍之间的栅极执行蚀刻工艺以暴露所述隔离结构，从而将所述栅极分成至少第一部分和第二部分，其中，控制蚀刻工艺以产生所述第一部分的第一侧壁和相对的所述第二部分的第二侧壁，其中，所述第一和所述第二侧壁提供宽于底部开口的顶部开口。
在上述方法中，所述蚀刻工艺包括利用介于50V到100V范围内的偏置电压的干蚀刻。
在上述方法中，所述导电层包括钨(W)，并且所述蚀刻工艺使用含有CxFy的气体混合物，其中x：y大于1：4。
在上述方法中，所述蚀刻工艺包括利用Cl2、O2、含碳和氟的气体、含溴和氟的气体以及含碳-氢和氟的气体的气体混合物进行干蚀刻。
在上述方法中，所述蚀刻工艺包括利用具有氯、氟、溴、氧、氢和碳的原子的蚀刻剂进行干蚀刻。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
衬底；
第一鳍和第二鳍，从衬底向外突出；以及
第一高k金属栅极(HK MG)和第二高k金属栅极，其中，所述第一高k金属栅极设置在所述第一鳍上方，并且所述第二高k金属栅极设置在所述第二鳍上方，
其中，从俯视图看，所述第一鳍和所述第二鳍沿第一方向纵向布置，所述第一高k金属栅极和所述第二高k金属栅极沿着垂直于所述第一方向的第二方向纵向布置，并且所述第一高k金属栅极和所述第二高k金属栅极沿着所述第二方向对准，
其中，在沿着所述第二方向切割的截面图中，所述第一高k金属栅极具有从顶部至底部朝向所述第二高k金属栅极倾斜的第一侧壁，并且所述第二高k金属栅极具有从顶部至底部朝向第一高k金属栅极倾斜的第二侧壁。
2.根据权利要求1所述的半导体器件，其中，所述第一侧壁与所述衬底的法线形成第一角度，并且所述第一角度在1至10度的范围内。
3.根据权利要求2所述的半导体器件，其中，所述第一角度在2至5度的范围内。
4.根据权利要求2所述的半导体器件，其中，所述第二侧壁与所述衬底的法线形成第二角度，并且所述第二角度在1至10度的范围内。
5.根据权利要求4所述的半导体器件，其中，所述第二角度在2至5度的范围内。
6.根据权利要求1所述的半导体器件，还包括横向地位于所述第一侧壁和所述第二侧壁之间的介电材料。
7.根据权利要求6所述的半导体器件，其中，所述介电材料完全填充所述第一侧壁和所述第二侧壁之间的空间。
8.根据权利要求1所述的半导体器件，其中，第一距离介于所述第一侧壁和所述第二侧壁的相应顶部之间，第二距离介于所述第一侧壁和所述第二侧壁的相应底部之间，并且所述第二距离与所述第一距离的比率在从0.4到0.8的范围内。
9.一种半导体器件，包括：
衬底；
第一鳍和第二鳍，从所述衬底向外突出；
第三鳍和第四鳍，从所述衬底向外突出；
第一高k金属栅极(HK MG)，设置在所述第一鳍和所述第二鳍上方；以及
第二高k金属栅极，设置在所述第三鳍和所述第四鳍上方，
其中，从俯视图看，所述第一鳍、所述第二鳍、所述第三鳍和所述第四鳍沿着第一方向纵向布置，所述第一高k金属栅极和所述第二高k金属栅极沿着垂直于所述第一方向的第二方向纵向对准，
其中，在沿着所述第二方向切割的截面图中，所述第一高k金属栅极具有第一侧壁，所述第二高k金属栅极具有与所述第一侧壁相对的第二侧壁，所述第一侧壁和所述第二侧壁与所述衬底的法线形成两个角度，其中，每个所述角度小于其中，AR是所述第一高k金属栅极的高度与所述第一侧壁和所述第二侧壁的各自的顶部之间的距离的比率，以及
其中，所述第一侧壁和所述第二侧壁之间的空间被一种或多种介电材料完全占据。
10.一种形成半导体器件的方法，包括：
提供结构，所述结构具有：
衬底，
鳍，从所述衬底向外突出，以及
隔离结构，位于所述衬底上方和相邻的鳍之间，
其中，所述隔离结构低于所述鳍；
在所述隔离结构和所述鳍上方形成栅极，其中，所述栅极包括高k介电层和导电层；以及
对两个相邻鳍之间的栅极执行蚀刻工艺以暴露所述隔离结构，从而将所述栅极分成至少第一部分和第二部分，其中，控制蚀刻工艺以产生所述第一部分的第一侧壁和相对的所述第二部分的第二侧壁，其中，所述第一和所述第二侧壁提供宽于底部开口的顶部开口。
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