CN109427873A - 具有粗糙阻挡层的金属栅极的结构和方法 - Google Patents

具有粗糙阻挡层的金属栅极的结构和方法 Download PDF

Info

Publication number
CN109427873A
CN109427873A CN201711350056.XA CN201711350056A CN109427873A CN 109427873 A CN109427873 A CN 109427873A CN 201711350056 A CN201711350056 A CN 201711350056A CN 109427873 A CN109427873 A CN 109427873A
Authority
CN
China
Prior art keywords
barrier layer
layer
work function
grid groove
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201711350056.XA
Other languages
English (en)
Other versions
CN109427873B (zh
Inventor
陈彦廷
许嘉麟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109427873A publication Critical patent/CN109427873A/zh
Application granted granted Critical
Publication of CN109427873B publication Critical patent/CN109427873B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

一种形成半导体器件的方法包括：接收具有衬底、位于衬底上方的栅极沟槽以及位于衬底上方并围绕栅极沟槽的介电层的结构。该方法还包括在栅极沟槽中形成栅极介电层、在栅极沟槽中并且在栅极介电层上方形成阻挡层以及处理阻挡层以使阻挡层的外表面粗糙，得到处理的阻挡层。该方法还包括在处理的阻挡层上方形成n型功函金属层。本发明实施例涉及具有粗糙阻挡层的金属栅极的结构和方法。

Description

具有粗糙阻挡层的金属栅极的结构和方法
技术领域
本发明实施例涉及具有粗糙阻挡层的金属栅极的结构和方法。
背景技术
半导体集成电路(IC)工业经历了快速增长。IC材料和设计的技术进步产生了多代IC，其中，每一代IC都具有比前一代IC更小且更复杂的电路。在IC演进过程中，功能密度(即，单位芯片面积中的互连器件的数量)通常在增加，而几何尺寸(即，可使用制造工艺创建的最小组件(或线))却已减小。这种按比例缩小工艺通常通过增加产量效率和降低相关成本来提供很多益处。这种按比例缩小工艺也增大了加工和制造IC的复杂度。
例如，当制造诸如鳍式FET(FinFET)的场效应晶体管(FET)时，可以通过使用高k金属栅极代替通常的多晶硅栅极来改进器件性能。高k金属栅极的功函数可以通过选择高k金属栅极中的某些功函金属层的材料和厚度来调节。随着FET器件继续缩小，为了进一步加速FET器件的操作，期望栅极端子中的更低阈值电压(Vt)(与其功函数直接相关)。然而，由于考虑到栅极堆叠件工程和制造，所以难以持续降低现有高k金属栅极的功函数，特别是对于n型FET(或NFET)。例如，为了减少高k介电层与功函金属层之间的相互作用，通常在它们之间放置阻挡层。该阻挡层有时会增加金属栅极的功函数。
发明内容
根据本发明的一些实施例，提供了一种形成半导体器件的方法，包括：接收具有衬底、位于所述衬底上方的栅极沟槽和位于所述衬底上方并且围绕所述栅极沟槽的介电层的结构；在所述栅极沟槽中形成栅极介电层；在所述栅极沟槽中并且在所述栅极介电层上方形成阻挡层；处理所述阻挡层以使所述阻挡层的外表面粗糙，得到处理的阻挡层；以及在所述处理的阻挡层上方形成n型功函金属层。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：接收具有衬底、位于所述衬底上方的第一栅极沟槽和第二栅极沟槽以及位于所述衬底上方并且围绕所述第一栅极沟槽和所述第二栅极沟槽的介电层的结构；在所述第一栅极沟槽和所述第二栅极沟槽中沉积栅极介电层；在所述第一栅极沟槽和所述第二栅极沟槽中并且在所述栅极介电层上方沉积阻挡层；在所述第一栅极沟槽和所述第二栅极沟槽中并且在所述阻挡层上方沉积p型功函金属层；形成覆盖所述第二栅极沟槽的图案化的掩模；从所述第一栅极沟槽去除所述p型功函金属层，从而暴露所述第一栅极沟槽中的阻挡层；在从所述第一栅极沟槽去除所述p型功函金属层之后，去除所述图案化的掩模；处理所述第一栅极沟槽中的阻挡层以使所述阻挡层的外表面粗糙；以及在处理所述阻挡层之后，在所述第一栅极沟槽和所述第二栅极沟槽中沉积n型功函金属层。
根据本发明的又一些实施例，还提供了一种半导体结构，包括：衬底；栅极堆叠件，位于所述衬底上方；以及源极和漏极部件，邻近所述栅极堆叠件，其中，所述栅极堆叠件包括：高k介电层，阻挡层，位于所述高k介电层上方，所述阻挡层具有粗糙表面，和n型功函金属层，位于所述粗糙表面上方。
附图说明
当结合附图进行阅读时，从以下详细描述可更好地理解本发明。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出根据本发明的方面构造的高k金属栅极堆叠件。
图2A和图2B示出根据本发明的各个方面的制造半导体器件的方法的流程图。
图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14和图15是根据一些实施例的根据图2A和图2B的方法形成半导体器件的截面图。
具体实施方式
以下公开内容提供了许多不同实施例或示例，用于实现所提供主题的不同特征。以下将描述组件和布置的具体示例以简化本发明。当然，这些仅是示例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个示例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
本发明总体涉及半导体器件，并且更具体地，涉及具有高k金属栅极的半导体场效应晶体管(FET)。本发明的目的在于设计和制造高k金属栅极，以便为NFET提供低功函数。
参考图1，其中示出根据本发明的方面构造的具有设置在衬底102上方的高k金属栅极140的器件100。特别地，高k金属栅极140适用于本实施例中的NFET。在实施例中，器件100可以包括二维(或2D)晶体管，其中，高k金属栅极140设置在NFET沟道的仅一个表面上。在另一实施例中，器件100可以包括三维(或3D)晶体管(诸如FinFET或全环栅器件)，其中，高k金属栅极140设置在NFET沟道的不止一个表面上。
该实施例中的高k金属栅极140包括顺序堆叠的界面层120、栅极介电层122、覆盖层124、阻挡层126A、n型功函金属层128、阻挡层132以及金属填充层134。在一些实施例中，高k金属栅极140可以包括本文未示出的附加层。在一些其他实施例中，可以在高k金属栅极140中省略图1中所示的一些层。
界面层120可以包括诸如氧化硅(SiO2)或氮氧化硅(SiON)的介电材料并且可以使用化学氧化、热氧化、原子层沉积(ALD)、化学汽相沉积(CVD)和/或其他合适的方法来形成。
栅极介电层122可以包括一个或多个高k(例如，k>3.9)介电材料，诸如氧化硅铪(HfSiO4)、氧化铪(HfO2)、氧化铝(Al2O3)、氧化锆(ZrO2)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)或它们的组合。栅极介电层122也可以被称为高k介电层122。栅极介电层122可以使用物理汽相沉积(PVD)、CVD、ALD和/或其他合适的方法来沉积。
在一些实施例中，覆盖层124可以包括镧基氧化物层(例如，LaOx)。在一些示例中，覆盖层124可以包括其他层，诸如Al2O3层、SiO2层、Y2O3层、氮化钛(TiN)层、氮化钛硅(TiSiN)层、它们的组合或其他合适的覆盖层。覆盖层124可以通过PVD、CVD、ALD和/或其他合适的方法来形成。
在本实施例中，阻挡层126A包括金属氮化物，诸如氮化钽、氮化钛或它们的组合。阻挡层126A可以通过PVD、CVD、ALD和/或其他合适的方法来形成。在本实施例中，阻挡层126A具有与n型功函金属层128邻近的粗糙表面125。该粗糙表面125有助于降低高k金属栅极140的功函数，这将在下文详细讨论。
n型功函金属层128可以包括一层或多层导电材料。特别地，n型功函金属层128包括具有足够低的有效功函数的金属，选自但不限于钛(Ti)、铝(Al)、锆(Zr)、钽(Ta)、铌(Nb)、钛铝(TiAl)、碳化钽(TaC)、氮化碳钽(TaCN)、氮化硅钽(TaSiN)、氮化硅钛(TiSiN)、碳化钛铝(TiAlC)或它们的组合。n型功函金属层128可以通过PVD、CVD、ALD和/或其他合适的方法来形成。特别是在本实施例中，n型功函金属层128在其与阻挡层126A相交界的部分中包括铝(Al)。
实验已经表明粗糙表面125通过降低高k金属栅极140的有效功函数而对其有利。认为粗糙表面125的工作原理如下。由于铝具有非常低的功函数(约4.1eV)，所以通过在n型功函金属层128中具有铝，高k金属栅极140的功函数可以降低。然而，n型功函金属层128的铝原子与高k介电层122间隔开，通过它们之间的层，诸如覆盖层124与阻挡层126A。在本实施例中，粗糙表面125被设计为允许功函金属层128的铝原子扩散穿过阻挡层126A。这有效地缩短了铝原子与高k栅极介电层122之间的距离，有助于降低高k金属栅极140的功函数。在一些实施例中，阻挡层126A可以具有约2nm的(峰值)厚度。如果阻挡层126A具有均匀厚度而不是具有粗糙表面，则n型功函金属层128的铝原子将不能扩散穿过阻挡层126A。
在实施例中，粗糙表面125具有3至10埃的平均表面粗糙度(Ra)，其中，Ra是表面125的粗糙度分布的算术平均值。在另一实施例中，阻挡层126A的厚度可以横跨表面125从到变化。
阻挡层132可以包括氮化钛、氧化钛铝或其他合适的材料；并且可以通过PVD、CVD、ALD和/或其他合适的方法来沉积。金属填充层134可以包括铝(Al)、钨(W)、钴(Co)、铜(Cu)和/或其它合适的材料；并且可以使用诸如CVD、PVD、镀敷和/或其他合适的工艺的方法来沉积。
现在参考图2A和图2B，根据本发明的各个方面，示出形成诸如器件100的半导体器件的方法200的流程图。特别地，器件100被制造为具有带有粗糙阻挡层的高k金属栅极，诸如高k金属栅极140(图1)。方法200仅是示例，并且不旨在限制本发明，除非权利要求中明确列举的。可以在方法200之前、期间和之后提供附加的操作，并且对于方法的附加的实施例，可以代替、消除或移动描述的一些操作。下面结合图3至图13描述方法200，示出处于各个制造阶段的半导体器件100的部分。器件100可以是在IC或其部分的处理期间制造的中间器件，IC或其部分可以包括SRAM和/或其他逻辑电路；诸如电阻器、电容器和电感器的无源组件；以及有源组件，诸如p型FET(PFET)、n型FET(NFET)、FinFET、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管、其他存储单元和它们的组合。
在操作202中，方法200(图2A)接收器件结构100(或简称为器件100)，器件结构100具有其中和/或其上形成有各种结构的衬底102。参考图3，器件100包括衬底102和位于衬底102上方的隔离结构106。隔离结构106将器件100分为各个器件区域。在所示的示例中，存在用于形成NFET的n-FET器件区域100a和用于形成PFET的p-FET器件区域100b。在本实施例中，器件100包括FinFET，并且衬底102包括向上突出穿过隔离结构106的两个有源鳍104a和104b。两个鳍104a和104b分别位于器件区域100a和100b中。在进一步的实施例中，图3至图13是器件100沿相应鳍104a和104b的鳍长度方向的部分的示意性截面图，而图14是器件100沿相应鳍104a和104b的鳍宽度方向的部分的示意性截面图。在各个实施例中，器件区域100a和100b可以是连续的或不连续的，并且每个都可以被加工为具有多个晶体管。本发明不限于任何特定数量的器件或器件区域，或者任何特定的器件配置。此外，尽管FinFET被用作示例，但是器件100可以替代地或附加地包括2D晶体管(或者平面晶体管)，在这种情况下，图3至图13是2D晶体管沿其沟道长度方向的部分的示意性截面图，并且图14不适用于2D晶体管。更进一步，图15示出根据本发明构造的具有由高k金属栅极包裹环绕的纳米线沟道的器件100的实施例，在这种情况下，器件100包括全环栅晶体管。
器件100还分别在器件区域100a和100b中包括栅极结构101a和101b。栅极结构101a和101b各自包括临时(伪)栅极堆叠件110和位于临时栅极堆叠件110的侧壁上的间隔件部件(或栅极间隔件)112。临时栅极堆叠件110将在之后的制造步骤中被高k金属栅极代替。栅极结构101a和101b各自分别与有源鳍104a和104b的一部分接合。器件100还包括至少部分地嵌入在相应有源鳍104a和104b中并设置在相应栅极结构101a和101b的相对两侧上的源极/漏极(S/D)区域(或S/D部件)108a和108b。在一些实施例中，S/D部件108a和108b可以凸起在隔离结构106上面。器件100还包括围绕栅极结构101a和101b的层间介电(ILD)层114。下面将进一步描述器件100的各个上述结构。
在本实施例中，衬底102是硅衬底。替代地，衬底102可以包括：其他元素半导体，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。在又一替代方案中，衬底102是诸如具有掩埋介电层的绝缘体上半导体(SOI)。
在本实施例中，鳍104a适于形成n型FinFET，并且鳍104b适于形成p型FinFET。该配置仅用于说明目的，并不限制本发明。鳍104a和104b可以使用合适的工艺来制造，包括双重图案化或多重图案化工艺。通常，双重图案化或多重图案化工艺将光刻和自对准工艺组合在一起，从而允许将创建的图案具有例如比使用单个直接光刻工艺可获得的图案更小的间距。例如，在一个实施例中，在衬底上方形成牺牲层并且使用光刻工艺进行图案化。使用自对准工艺在图案化的牺牲层旁形成间隔件。然后去除牺牲层，然后可以通过蚀刻衬底102的初始外延半导体层，使用剩余的间隔件或芯轴来图案化鳍104a和104b。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其他适合的工艺。例如，干蚀刻工艺可以使用含氧气体、含氟气体(如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(如，Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(如，HBr和/或CHBR3)、含碘气体、其他合适的气体和/或等离子体和/或它们的组合。例如，湿蚀刻工艺可包括在以下蚀刻剂中的蚀刻：稀释的氢氟酸(DHF)；氢氧化钾(KOH)溶液；氨水；包含氢氟酸(HF)、硝酸(HNO3)和/或醋酸(CH3COOH)的溶液；或其他适当的湿蚀刻剂。
隔离结构106可以包括氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其他合适的绝缘材料。隔离结构106可以是浅沟槽隔离(STI)部件。在实施例中，隔离结构106通过在衬底102中蚀刻沟槽来形成，例如，作为鳍104a/b形成工艺的一部分形成。随后可以用隔离材料填充沟槽，接着是化学机械平坦化(CMP)工艺和/或回蚀刻工艺。诸如场氧化物、硅的局部氧化(LOCOS)和/或其他合适的结构的其他隔离结构是可能的。隔离结构106可包括多层结构，例如，具有一个或多个热氧化物衬垫层。
在本实施例中，临时栅极堆叠件110在鳍的两侧或三侧上接合鳍104a和104b。临时栅极堆叠件110可以包括一个或多个材料层，诸如氧化物层、多晶硅层、硬掩模层以及其其他合适的层。临时栅极堆叠件110中的各个层可以通过合适的沉积技术来形成。例如，氧化物层可以通过化学氧化、热氧化、ALD、CVD和/或其他合适的方法来形成。例如，多晶硅层可以通过诸如低压化学汽相沉积(LPCVD)和等离子体增强的CVD(PECVD)的合适沉积工艺来形成。在实施例中，临时栅极堆叠件110首先被沉积为毯式层。然后通过包括光刻工艺和蚀刻工艺的工艺来图案化毯式层，从而去除毯式层的一部分并且将剩余部分保留在隔离结构106和鳍104a/b上方作为临时栅极堆叠件110。
在临时栅极堆叠件110的侧壁上形成间隔件部件112。间隔件部件112包括与用于临时栅极堆叠件110的材料不同的材料。在实施例中，间隔件部件112包括诸如氮化硅或氮氧化硅的介电材料。在实例中，间隔件部件112包括多个层，诸如邻近临时栅极堆叠件110的密封层和邻近密封层的主间隔件层。在实施例中，在已经形成临时栅极堆叠件110之后，通过在器件100上方毯式沉积间隔件材料来形成一个或多个间隔件层。然后，进行各向异性蚀刻工艺去除间隔件层的一部分以形成如图3所示的间隔件部件112。
S/D部件108a和108b可以通过各种技术来形成，诸如蚀刻工艺及随后的一个或多个外延工艺。在一个示例中，进行一个或多个蚀刻工艺以去除鳍104a和104b的一部分以在其中形成凹槽。可以执行清洁工艺以用氢氟酸(HF)溶液或其他合适的溶液清洁凹槽。随后，进行一个或多个外延生长工艺以在凹槽中生成半导体部件(如，用于NFET的硅和用于PFET的硅锗)。外延生长工艺可以利用用于形成p型FinFET的p型掺杂剂或用于形成n型FinFET的n型掺杂剂来原位或非原位掺杂生长的半导体。
ILD层114形成在衬底102上方。在实施例中，器件100还包括位于ILD层114下方的接触蚀刻停止层(如，氮化硅层)。ILD层114可以包括诸如原硅酸四乙酯(TEOS)氧化物，未掺杂的硅酸盐玻璃，或掺杂的氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))，和/或其他合适的介电材料的材料。ILD层114可以通过PECVD工艺或可流动CVD(FCVD)工艺来沉积。在各个沉积工艺之后，进行化学机械平坦化(CMP)工艺以平坦化介电层114的顶面并且暴露临时栅极堆叠件110的顶面以用于随后的制造步骤。
在操作204中，方法200(图2A)去除临时栅极堆叠件110。参考图4，由此在栅极结构101a和101b中分别形成两个栅极沟槽116a和116b，由此暴露鳍104a和104b。沟槽116a和116b被以上讨论的结构(诸如间隔件部件112和ILD层114)围绕。在实施例中，操作204包括一个或多个蚀刻工艺，蚀刻工艺选择性地调节为去除临时栅极堆叠件110(图3)，而间隔件部件112和ILD层114基本保留。蚀刻工艺可包括适合的湿蚀刻、干(等离子体)蚀刻和/或其他工艺。例如，干蚀刻工艺可以使用含氯气体、含氟气体、其他蚀刻气体或它们的组合。湿蚀刻溶液可以包括NH4OH、HF(氢氟酸)或稀释的HF、去离子水、TMAH(氢氧化四甲铵)、其他合适的湿蚀刻溶液或它们的组合。
在操作206中，方法200(图2A)在沟槽116a和116b中形成界面层120。在操作208中，方法200(图2A)在沟槽116a和116b中以及在界面层120上方形成栅极介电层122。在操作210中，方法200(图2A)在沟槽116a和116b中以及在栅极介电层122上方形成覆盖层124。在操作206、208和210之后，在图5中示出所得到的器件100。界面层120可以包括SiO2、SiON或其他合适的介电材料，并且可以通过化学氧化、热氧化、ALD和/或其他合适的方法来形成。在本实施例中，栅极介电层122包含高k介电材料，诸如HfO2、Al2O3、TiO2、La2O3、HfSiO4、ZrO2、Y2O3、SrTiO3、它们的组合或其他合适的材料。栅极介电层122可以通过ALD和/或其他合适的方法来形成。覆盖层124可以包括镧基氧化物、SiO2、Y2O3、TiN、TiSiN、TaN、它们的组合或其他合适的覆盖层；并且可以通过ALD和/或其他合适的方法来形成。覆盖层124被设计为保护栅极介电层122免于可能从位于覆盖层124上面或上方的其他层扩散的金属杂质。
在操作212中，方法200(图2A)在沟槽116a和116b中以及在覆盖层124上方形成阻挡层126。参考图6，在本实施例中，阻挡层126包括金属氮化物。例如，阻挡层126可以包括氮化钽、氮化钛、氮化铌或它们的组合。各种其他材料是可能的。在实施例中，阻挡层126通过ALD、PVD、CVD或其他合适的方法来形成。在本实施例中，阻挡层126具有约10到的厚度。阻挡层126的一个目的是在用于阈值电压调节的功函金属层图案化期间保护覆盖层124免于各种蚀刻工艺。例如，可以将p型功函金属同时沉积到沟槽116a和116b中，然后将其在沟槽116a中的部分替换为n型功函金属以便在器件区域100a中形成NFET。也可以进行相反的操作，即，在两个沟槽中沉积n型功函金属，然后在沟槽116b中用p型功函金属替换n型功函金属。在任一种情况下，在没有阻挡层126的情况下，在金属图案化/去除工艺期间，覆盖层124可能被不期望地蚀刻，这部分地是由于用于图案化/去除金属层的蚀刻剂的蚀刻选择性差。如果覆盖层124受到损害，则栅极介电层122也将受到损害。因此，期望具有用于保护覆盖层124的阻挡层126。然而，具有阻挡层126也增加了栅极介电层122与要沉积在阻挡层126上方的功函金属层之间的距离，这不期望地增加了NFET的功函数。本发明旨在减少这种效应，同时仍然具有作为用于覆盖层124的蚀刻保护层的阻挡层126。
在操作214中，如图7所示，方法200(图2A)将p型功函金属层130沉积到沟槽116a和116b中。p型金属功函金属层130包括具有足够高的有效功函数的金属，选自但不限于碳化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)的组或它们的组合。p型功函金属层130可以包括一层或多层材料。p型功函金属层130可以通过CVD、PVD、ALD和/或其他合适的工艺来沉积。
在操作216中，方法200(图2B)形成覆盖PFET区域100b的图案化的掩模127。参考图8，在实施例中，图案化的掩模127包括利用光刻工艺图案化的抗蚀剂(或光刻胶)，并且还可以包括光刻胶下层，诸如底部抗反射涂层(BARC)。光刻工艺可以包括在衬底102上面形成光刻胶层、将光刻胶暴露于图案、进行曝光后烘焙工艺以及显影光刻胶以去除其位于器件区域100a上方的部分，从而形成图案化的掩模127。
在操作218中，方法200(图2B)通过诸如湿蚀刻、干蚀刻、反应离子蚀刻和/或原子层蚀刻的一个或多个蚀刻工艺从第一沟槽116a中去除p型功函金属层130。在实施例中，蚀刻工艺将具有磷酸的蚀刻剂应用于p型功函金属层130。附加地或替代地，蚀刻剂可以包括其他组分，诸如过氧化氢(H2O2)、硝酸(HNO3)、硫酸(H2SO4)、去离子水(DIW)、氢氧化铵(NH4OH)、臭氧(O3)、氢氟酸(HF)、盐酸(HCl)、其他酸性溶液和有机氧化剂或它们的组合。蚀刻工艺被设计为对p型功函金属层130是选择性的并且不(或不显著地)蚀刻阻挡层126。沟槽116a中的阻挡层126有效地保护覆盖层124免于蚀刻工艺。换句话说，沟槽116a中的p型功函金属层130的蚀刻停止在阻挡层126处。在操作218之后，如图9所示，p型功函金属层130从沟槽116a中去除，但保留在沟槽116b中。在该蚀刻工艺期间，图案化的掩模127保护PFET区域100b中的结构。
在操作220中，方法200(图2B)使用诸如光刻胶剥离或灰化的工艺从器件区域100b去除图案化的掩模127。图10中示出得到的结构。
在操作222中，方法200(图2B)处理沟槽116a中的阻挡层126以使阻挡层126的表面125变粗糙(图11)。处理的阻挡层126被称为126A以将其与PFET区域100b中的未处理的阻挡层126区分开。在实施例中，操作222向阻挡层126应用含氯气体(如，金属氯化物气体)。在一些实施例中，可以用氩气稀释含氯气体。在本实施例中，例如，阻挡层126的表面部分包括在操作212中阻挡层126沉积之后由于暴露于大气中而得到的氧化物(阻挡层126A的氧化部分)。例如，如果阻挡层126包含氮化钽(TaN)，则在阻挡层126A的表面中存在一些氧化钽(Ta2O5)。含氯气体与氧化物反应，产生粗糙表面125。在实施例中，处理在约400至500℃的温度下进行。选择该温度范围以提高反应速度，同时保持器件100的各个结构(如，S/D部件108a/b、高k栅极介电层122等)的完整性。如果温度太高，则器件100的一些现有结构可能被损坏。如果温度太低，则工艺可能会花费过长的时间。在进一步的实施例中，处理在约10至35托的压力下进行，针对表面125中期望的粗糙度调整压力。
在一个示例中，含氯气体包括氯化钛(TiCl5)、氯化钽(TaCl5)、氯化钨(WCl5)或它们的混合物。在另一示例中，含氯气体可以包括氯化钨(WClx)，诸如WCl2、WCl3、WCl4、WCl5、WCl6或它们的混合物。例如，WCl5气体可以与Ta2O5固体反应生成WOCly气体和TaClx固体。然后可以将WOCly气体从反应室中抽出。通过这种取代反应，阻挡层126A的氧化部分可以被部分地或完全地去除，得到粗糙表面125。在实施例中，阻挡层126A的厚度可以横跨整个层从5到变化，并且表面125具有3到10埃的平均表面粗糙度(Ra)，其中，Ra是表面125的粗糙度分布的算术平均值。在各种实施例中，处理工艺的温度和压力可以被调节为在表面125上获得期望的表面粗糙度。在一些实施例中，由于处理，所以阻挡层126A变得比阻挡层126薄约例如，阻挡层126厚约15至并且处理的阻挡层126A厚约5至处理的阻挡层126A的厚度与期望从n型功函金属层(如，图1的n型功函金属层128)穿过阻挡层126A扩散的金属(例如，Al扩散)的量相关。可以设计和调节阻挡层126A的厚度和粗糙度以满足器件功函数要求。
在本实施例中，操作222还在处理阻挡层126的同时处理沟槽116b中的p型功函金属层130。选择各种处理工艺和化学品以与p型功函金属层130的材料起作用，从而不会使p型功函金属层130退化。
在操作224中，诸如图12所示，方法200(图2B)将n型功函金属层128沉积到沟槽116a和116b中。特别地，n型功函金属层128被沉积在沟槽116a中的处理的阻挡层126A上方，并且沉积在沟槽116b中的p型功函金属层130上方。在本实施例中，例如，操作222和224在相同的工艺室中或在相同的集群工具中进行而不破坏其间的真空。n型功函金属层128包括适于在器件区域100a中形成NFET的一种或多种材料。例如，n型功函金属层128可以包括具有足够低的有效功函数的金属，选自但不限于Ti、Al、Zr、Ta、Nb、TiAl、TaC、TaCN、TaSiN、TiSiN、TiAlC、TiAlN的组或它们的组合。在一个示例中，功函金属层128具有约10至约的厚度。n型功函金属层128可以通过PVD、CVD、ALD和/或其他合适的方法来形成。特别地，在本实施例中，n型功函金属层128在其靠近表面125且与该表面直接接触的部分中包括Al。由于粗糙表面125，所以阻挡层126A的部分对于铝原子扩散穿过来说足够薄。
实验已经表明氧浓度(或含量)从覆盖层124到阻挡层126A并从阻挡层126A到n型功函金属层128逐渐减小。同时，铝浓度在n型功函金属层128的下部部分(最靠近阻挡层126A)最高，接着是阻挡层126A以及n型功函金属层128的上部部分(更远离阻挡层126A)，随后是阻挡层126A与覆盖层124之间的界面，然后是覆盖层124。在本实施例中，铝浓度按照上面讨论的顺序降低。铝原子在各个层128、126A和124中的分布证实了铝原子已经扩散穿过粗糙阻挡层126A。使铝原子更靠近高k介电层122有助于降低高k金属栅极101a的功函数。在各种实施例中，诸如Ti和Zr的其他类型的n型功函金属原子也可以扩散穿过粗糙阻挡层126A并且靠近高k介电层122移动，这有助于降低高k金属栅极101a的功函数。
在操作226中，方法200(图2B)对器件100进行进一步的步骤。例如，诸如图13所示，操作226可以将金属阻挡层132和金属填充层134沉积到沟槽116a和116b中。阻挡层132可以包括氮化钛、氧化钛铝或其他合适的材料；并且可以通过PVD、CVD、ALD和/或其他合适的方法来沉积。金属填充层134可以包括铝(Al)、钨(W)、钴(Co)、铜(Cu)和/或其它合适的材料；并且可以使用诸如CVD、PVD、镀敷和/或其他合适的工艺的方法来沉积。操作226可以进行化学机械平坦化(CMP)工艺以从栅极结构101a/b去除过量的材料。操作226可以进一步形成电连接源极/漏极部件108a/b和栅极结构101a/b的接触件和通孔，并且形成将FinFET连接至器件100的其他部分的金属互连件，从而形成完整的IC。
图14示出根据实施例的器件100的一部分的截面图(沿鳍宽度方向)。并非器件100的所有部件都在图14中示出。参考图14，在NFET区域100a中，器件100包括衬底102、隔离结构106、鳍104a和n型高k金属栅极堆叠件101a。在PFET区域100b中，器件100包括衬底102、隔离结构106、鳍104b和p型高k金属栅极堆叠件101b。栅极堆叠件101a和101b中的每一个都包括位于相应鳍104a/b的表面上的界面层120、覆盖层122和高k栅极介电层124。n型高k金属栅极堆叠件101a还包括位于覆盖层124上方的粗糙阻挡层126A以及位于粗糙阻挡层126A上方的n型功函金属层128。p型高k金属栅极堆叠件101b还包括位于覆盖层124上方的阻挡层126和位于阻挡层126上方的p型功函金属层130。
图15示出器件100的实施例，其中，晶体管沟道104'是纳米线而不是鳍。至少高k金属栅极堆叠件101a的层120、122、124和126A缠绕在晶体管沟道104'周围。阻挡层126A具有粗糙外表面125。n型功函金属层128设置在粗糙外表面125周围，这有助于n型功函金属层128的一些金属原子(诸如铝原子)扩散穿过阻挡层126A。
虽然不旨在限制，但是本发明的一个或多个实施例对半导体器件及其形成提供许多益处。例如，本发明的实施例提供用于NFET的新颖的高k金属栅极堆叠件，其中，高k金属栅极堆叠件包括介于n型功函金属层与高k介电层之间的粗糙阻挡层。粗糙阻挡层有助于使诸如铝原子的n型金属原子更靠近高k介电层，从而降低高k金属栅极的功函数。其形成方法可以容易地集成到现有的半导体制造工艺中。
在一个示例性方面中，本发明涉及一种形成半导体器件的方法。该方法包括接收具有衬底、位于衬底上方的栅极沟槽以及位于衬底上方并围绕栅极沟槽的介电层的结构。该方法还包括在栅极沟槽中形成栅极介电层、在栅极沟槽中并且在栅极介电层上方形成阻挡层以及处理阻挡层以使阻挡层的外表面粗糙，得到处理的阻挡层。该方法还包括在处理的阻挡层上方形成n型功函金属层。
在该方法的实施例中，n型功函金属层包括铝(Al)。在进一步的实施例中，阻挡层包括氮化钽(TaN)或氮化钛(TiN)。在进一步的实施例中，阻挡层的处理包括将含氯气体应用于阻挡层。在一个示例中，含氯气体包括氯化钨(WClx)。
在该方法的实施例中，阻挡层的外表面被粗糙化以具有3至10埃的平均表面粗糙度(Ra)。在该方法的另一实施例中，阻挡层的处理在从400到500摄氏度的范围内的温度和从10到35托的范围内的压力下进行。在又一实施例中，该方法还包括在栅极介电层与阻挡层之间形成覆盖层。
在另一示例性方面中，本发明针对一种形成半导体器件的方法。该方法包括接收具有衬底、位于衬底上方的第一和第二栅极沟槽以及位于衬底上方并且围绕第一和第二栅极沟槽的介电层的结构。该方法还包括在第一和第二栅极沟槽中形成栅极介电层以及在第一和第二栅极沟槽中并且在栅极介电层上方形成阻挡层。该方法还包括：在第一和第二栅极沟槽中并且在阻挡层上方沉积p型功函金属层；形成覆盖第二栅极沟槽的图案化的掩模；以及从第一栅极沟槽去除p型功函金属层，由此暴露第一栅极沟槽中的阻挡层。该方法还包括：在从第一栅极沟槽去除p型功函金属层之后去除图案化的掩模；以及处理第一栅极沟槽中的阻挡层以使阻挡层的外表面粗糙。该方法还包括：在处理阻挡层之后，在第一和第二栅极沟槽中沉积n型功函金属层。
在该方法的实施例中，阻挡层的处理和n型功函金属层的沉积在不破坏真空的情况下进行。在另一实施例中，该方法还包括：在形成阻挡层之前，在栅极介电层上方形成覆盖层。
在该方法的实施例中，栅极介电层包括高k介电材料，阻挡层包括金属氮化物，和n型功函金属层包括铝。
在另一实施例中，该方法还包括在第一和第二栅极沟槽中的n型功函金属层上方沉积金属阻挡层。
在该方法的实施例中，阻挡层的处理包括将金属氯化物气体应用于第一栅极沟槽中的阻挡层。在进一步的实施例中，金属氯化物气体包括氯化钨。
在另一示例性方面中，本发明涉及一种半导体结构。该半导体结构包括衬底、位于衬底上方的栅极堆叠件以及邻近栅极堆叠件的源极和漏极部件。栅极堆叠件包括高k介电层、位于高k介电层上方的阻挡层，阻挡层具有粗糙表面以及位于粗糙表面上方的n型功函金属层。
在半导体结构的实施例中，粗糙表面具有3至10埃的平均表面粗糙度。在实施例中，半导体结构还包括介于高k介电层与阻挡层之间的覆盖层。在进一步的实施例中，n型功函金属层和阻挡层中的每一个都包括铝，并且栅极堆叠件还包括介于阻挡层与覆盖层之间的铝。在半导体结构的另一实施例中，n型功函金属层包括铝和钛，阻挡层包括铝以及氮化钛和氮化钽中的一个，并且栅极堆叠件包括介于阻挡层与高k介电层之间的铝。
根据本发明的一些实施例，提供了一种形成半导体器件的方法，包括：接收具有衬底、位于所述衬底上方的栅极沟槽和位于所述衬底上方并且围绕所述栅极沟槽的介电层的结构；在所述栅极沟槽中形成栅极介电层；在所述栅极沟槽中并且在所述栅极介电层上方形成阻挡层；处理所述阻挡层以使所述阻挡层的外表面粗糙，得到处理的阻挡层；以及在所述处理的阻挡层上方形成n型功函金属层。
在上述方法中，所述n型功函金属层包括铝(Al)。
在上述方法中，所述阻挡层包括氮化钽(TaN)或氮化钛(TiN)。
在上述方法中，所述阻挡层的处理包括将含氯气体施加至所述阻挡层。
在上述方法中，所述含氯气体包括氯化钨(WClx)。
在上述方法中，所述阻挡层的外表面被粗糙化以具有3至10埃的平均表面粗糙度(Ra)。
在上述方法中，所述阻挡层的处理在从400到500摄氏度的范围内的温度和从10到35托的范围内的压力下实施。
在上述方法中，还包括：在所述栅极介电层与所述阻挡层之间形成覆盖层。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：接收具有衬底、位于所述衬底上方的第一栅极沟槽和第二栅极沟槽以及位于所述衬底上方并且围绕所述第一栅极沟槽和所述第二栅极沟槽的介电层的结构；在所述第一栅极沟槽和所述第二栅极沟槽中沉积栅极介电层；在所述第一栅极沟槽和所述第二栅极沟槽中并且在所述栅极介电层上方沉积阻挡层；在所述第一栅极沟槽和所述第二栅极沟槽中并且在所述阻挡层上方沉积p型功函金属层；形成覆盖所述第二栅极沟槽的图案化的掩模；从所述第一栅极沟槽去除所述p型功函金属层，从而暴露所述第一栅极沟槽中的阻挡层；在从所述第一栅极沟槽去除所述p型功函金属层之后，去除所述图案化的掩模；处理所述第一栅极沟槽中的阻挡层以使所述阻挡层的外表面粗糙；以及在处理所述阻挡层之后，在所述第一栅极沟槽和所述第二栅极沟槽中沉积n型功函金属层。
在上述方法中，所述阻挡层的处理和所述n型功函金属层的沉积在不破坏真空的情况下实施。
在上述方法中，还包括：在形成所述阻挡层之前，在所述栅极介电层上方形成覆盖层。
在上述方法中，所述栅极介电层包括高k介电材料，所述阻挡层包括金属氮化物，并且所述n型功函金属层包括铝。
在上述方法中，还包括：在所述第一栅极沟槽和所述第二栅极沟槽中的n型功函金属层上方沉积金属阻挡层。
在上述方法中，所述阻挡层的处理包括将金属氯化物气体施加至所述第一栅极沟槽中的阻挡层。
在上述方法中，所述金属氯化物气体包括氯化钨。
根据本发明的又一些实施例，还提供了一种半导体结构，包括：衬底；栅极堆叠件，位于所述衬底上方；以及源极和漏极部件，邻近所述栅极堆叠件，其中，所述栅极堆叠件包括：高k介电层，阻挡层，位于所述高k介电层上方，所述阻挡层具有粗糙表面，和n型功函金属层，位于所述粗糙表面上方。
在上述半导体结构中，所述粗糙表面具有3至10埃的平均表面粗糙度。
在上述半导体结构中，还包括介于所述高k介电层与所述阻挡层之间的覆盖层。
在上述半导体结构中，所述n型功函金属层和所述阻挡层中的每一个都包括铝，并且其中，所述栅极堆叠件也包括位于所述阻挡层与所述覆盖层之间的铝。
在上述半导体结构中，所述n型功函金属层包括铝和钛；并且所述阻挡层包括铝以及氮化钛和氮化钽中的一个，其中，所述栅极堆叠件还包括位于所述阻挡层与所述高k介电层之间的铝。
上面论述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
接收具有衬底、位于所述衬底上方的栅极沟槽和位于所述衬底上方并且围绕所述栅极沟槽的介电层的结构；
在所述栅极沟槽中形成栅极介电层；
在所述栅极沟槽中并且在所述栅极介电层上方形成阻挡层；
处理所述阻挡层以使所述阻挡层的外表面粗糙，得到处理的阻挡层；以及
在所述处理的阻挡层上方形成n型功函金属层。
2.根据权利要求1所述的方法，其中，所述n型功函金属层包括铝(Al)。
3.根据权利要求2所述的方法，其中，所述阻挡层包括氮化钽(TaN)或氮化钛(TiN)。
4.根据权利要求3所述的方法，其中，所述阻挡层的处理包括将含氯气体施加至所述阻挡层。
5.根据权利要求4所述的方法，其中，所述含氯气体包括氯化钨(WClx)。
6.根据权利要求1所述的方法，其中，所述阻挡层的外表面被粗糙化以具有3至10埃的平均表面粗糙度(Ra)。
7.根据权利要求1所述的方法，其中，所述阻挡层的处理在从400到500摄氏度的范围内的温度和从10到35托的范围内的压力下实施。
8.根据权利要求1所述的方法，还包括：
在所述栅极介电层与所述阻挡层之间形成覆盖层。
9.一种形成半导体器件的方法，包括：
接收具有衬底、位于所述衬底上方的第一栅极沟槽和第二栅极沟槽以及位于所述衬底上方并且围绕所述第一栅极沟槽和所述第二栅极沟槽的介电层的结构；
在所述第一栅极沟槽和所述第二栅极沟槽中沉积栅极介电层；
在所述第一栅极沟槽和所述第二栅极沟槽中并且在所述栅极介电层上方沉积阻挡层；
在所述第一栅极沟槽和所述第二栅极沟槽中并且在所述阻挡层上方沉积p型功函金属层；
形成覆盖所述第二栅极沟槽的图案化的掩模；
从所述第一栅极沟槽去除所述p型功函金属层，从而暴露所述第一栅极沟槽中的阻挡层；
在从所述第一栅极沟槽去除所述p型功函金属层之后，去除所述图案化的掩模；
处理所述第一栅极沟槽中的阻挡层以使所述阻挡层的外表面粗糙；以及
在处理所述阻挡层之后，在所述第一栅极沟槽和所述第二栅极沟槽中沉积n型功函金属层。
10.一种半导体结构，包括：
衬底；
栅极堆叠件，位于所述衬底上方；以及
源极和漏极部件，邻近所述栅极堆叠件，
其中，所述栅极堆叠件包括：
高k介电层，
阻挡层，位于所述高k介电层上方，所述阻挡层具有粗糙表面，和
n型功函金属层，位于所述粗糙表面上方。
CN201711350056.XA 2017-08-25 2017-12-15 具有粗糙阻挡层的金属栅极的结构和方法 Active CN109427873B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762550395P 2017-08-25 2017-08-25
US62/550,395 2017-08-25
US15/800,164 US10049940B1 (en) 2017-08-25 2017-11-01 Structure and method for metal gates with roughened barrier layer
US15/800,164 2017-11-01

Publications (2)

Publication Number Publication Date
CN109427873A true CN109427873A (zh) 2019-03-05
CN109427873B CN109427873B (zh) 2022-06-10

Family

ID=63078886

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711350056.XA Active CN109427873B (zh) 2017-08-25 2017-12-15 具有粗糙阻挡层的金属栅极的结构和方法

Country Status (5)

Country Link
US (3) US10049940B1 (zh)
KR (1) KR102100790B1 (zh)
CN (1) CN109427873B (zh)
DE (1) DE102017126236B3 (zh)
TW (1) TWI655680B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113380873A (zh) * 2020-05-26 2021-09-10 台湾积体电路制造股份有限公司 半导体器件及其制造方法

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10049940B1 (en) * 2017-08-25 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for metal gates with roughened barrier layer
US11114347B2 (en) * 2017-06-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Self-protective layer formed on high-k dielectric layers with different materials
KR102646467B1 (ko) * 2018-03-27 2024-03-11 에이에스엠 아이피 홀딩 비.브이. 기판 상에 전극을 형성하는 방법 및 전극을 포함하는 반도체 소자 구조
US10923393B2 (en) * 2018-09-24 2021-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts and interconnect structures in field-effect transistors
US10770563B2 (en) 2018-10-24 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure and patterning method for multiple threshold voltages
US11069534B2 (en) * 2018-10-31 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and semiconductor devices
US11158719B2 (en) * 2018-11-30 2021-10-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and semiconductor devices
US11127857B2 (en) 2019-04-12 2021-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11289578B2 (en) * 2019-04-30 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Selective etching to increase threshold voltage spread
KR20210011558A (ko) 2019-07-22 2021-02-02 삼성전자주식회사 반도체 소자
US11056395B2 (en) * 2019-08-23 2021-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor metal gate and method of manufacture
US11710667B2 (en) * 2019-08-27 2023-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same
US11183431B2 (en) 2019-09-05 2021-11-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and semiconductor devices
US11430652B2 (en) * 2019-09-16 2022-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling threshold voltages through blocking layers
US11342231B2 (en) * 2019-09-17 2022-05-24 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit device with low threshold voltage
US11393817B2 (en) * 2019-10-18 2022-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for gate-all-around metal-oxide-semiconductor devices with improved channel configurations
US11903328B2 (en) * 2020-02-07 2024-02-13 International Business Machines Corporation Self assembled monolayer formed on a quantum device
US11538926B2 (en) * 2020-04-01 2022-12-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing a semiconductor device
US11444198B2 (en) * 2020-05-29 2022-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Work function control in gate structures
US11699736B2 (en) 2020-06-25 2023-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure and method
US11508826B2 (en) * 2020-07-16 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Composite work function layer formation using same work function material
US20220208974A1 (en) * 2020-12-30 2022-06-30 Changxin Memory Technologies, Inc. Method for manufacturing semiconductor structure and semiconductor structure
US11411079B1 (en) 2021-01-21 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
KR20220127055A (ko) 2021-03-10 2022-09-19 남중송 휴대단말기에 기록된 연락처의 근거리 지인에게 단위 시간당 소정 현금 자동 이체 시스템 및 그 운용방법
US11575017B2 (en) * 2021-06-14 2023-02-07 Nanya Technology Corporation Semiconductor device with void-free contact and method for preparing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1494119A (zh) * 2002-10-04 2004-05-05 ������������ʽ���� 半导体装置的制造方法
TW200742141A (en) * 2006-02-28 2007-11-01 Pioneer Corp Organic transistor and method for manufacturing the same
CN101197286A (zh) * 2006-12-05 2008-06-11 中芯国际集成电路制造(上海)有限公司 金属氧化物半导体器件的制造方法
CN102422397A (zh) * 2009-05-08 2012-04-18 住友电气工业株式会社 半导体器件及其制造方法
KR20160063378A (ko) * 2013-09-27 2016-06-03 어플라이드 머티어리얼스, 인코포레이티드 심리스 코발트 갭-충전을 가능하게 하는 방법
US20160181163A1 (en) * 2014-12-22 2016-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and Structure for Metal Gates

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4849881B2 (ja) 2005-12-08 2012-01-11 株式会社日立ハイテクノロジーズ プラズマエッチング方法
KR101516157B1 (ko) * 2008-04-23 2015-04-30 삼성전자주식회사 게이트 구조물 및 그 형성 방법
US8860135B2 (en) * 2012-02-21 2014-10-14 United Microelectronics Corp. Semiconductor structure having aluminum layer with high reflectivity
KR102230196B1 (ko) 2015-04-23 2021-03-19 삼성전자주식회사 반도체 소자 및 그 제조방법
US9972694B2 (en) 2015-10-20 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Atomic layer deposition methods and structures thereof
US9978601B2 (en) 2015-10-20 2018-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for pre-deposition treatment of a work-function metal layer
US9799745B2 (en) 2015-10-20 2017-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Atomic layer deposition methods and structures thereof
US10049940B1 (en) * 2017-08-25 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for metal gates with roughened barrier layer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1494119A (zh) * 2002-10-04 2004-05-05 ������������ʽ���� 半导体装置的制造方法
TW200742141A (en) * 2006-02-28 2007-11-01 Pioneer Corp Organic transistor and method for manufacturing the same
CN101197286A (zh) * 2006-12-05 2008-06-11 中芯国际集成电路制造(上海)有限公司 金属氧化物半导体器件的制造方法
CN102422397A (zh) * 2009-05-08 2012-04-18 住友电气工业株式会社 半导体器件及其制造方法
KR20160063378A (ko) * 2013-09-27 2016-06-03 어플라이드 머티어리얼스, 인코포레이티드 심리스 코발트 갭-충전을 가능하게 하는 방법
US20160181163A1 (en) * 2014-12-22 2016-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and Structure for Metal Gates

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113380873A (zh) * 2020-05-26 2021-09-10 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN113380873B (zh) * 2020-05-26 2023-10-10 台湾积体电路制造股份有限公司 半导体器件及其制造方法

Also Published As

Publication number Publication date
TW201913755A (zh) 2019-04-01
US10049940B1 (en) 2018-08-14
US10978350B2 (en) 2021-04-13
TWI655680B (zh) 2019-04-01
US10497626B2 (en) 2019-12-03
KR102100790B1 (ko) 2020-04-16
US20190067117A1 (en) 2019-02-28
KR20190022280A (ko) 2019-03-06
US20200098641A1 (en) 2020-03-26
CN109427873B (zh) 2022-06-10
DE102017126236B3 (de) 2019-02-21

Similar Documents

Publication Publication Date Title
CN109427873A (zh) 具有粗糙阻挡层的金属栅极的结构和方法
US11721544B2 (en) Cut metal gate process for reducing transistor spacing
CN109427777B (zh) 具有倾斜侧壁的切割金属栅极
TWI644363B (zh) 半導體結構及其形成方法
CN106206436B (zh) 用于金属栅极的方法和结构
US11380772B2 (en) Gate structure and patterning method for multiple threshold voltages
TWI565074B (zh) 半導體結構與其製備方法
CN110176443A (zh) 用于减小接触电阻的双金属通孔
CN109585446B (zh) 半导体装置
CN113113491B (zh) 半导体器件及其形成方法
TW201926548A (zh) 半導體結構的製造方法
TW202209575A (zh) 半導體裝置及其形成方法
CN107342259B (zh) 半导体装置的形成方法
CN109427896A (zh) 半导体装置的形成方法
CN109427670A (zh) 周围包裹的外延结构和方法
US10361280B2 (en) Gate structure for semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant