TWI655680B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TWI655680B
TWI655680B TW106139891A TW106139891A TWI655680B TW I655680 B TWI655680 B TW I655680B TW 106139891 A TW106139891 A TW 106139891A TW 106139891 A TW106139891 A TW 106139891A TW I655680 B TWI655680 B TW I655680B
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Taiwan
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layer
barrier layer
gate
gate trench
work function
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TW106139891A
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TW201913755A (zh
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陳彥廷
許嘉麟
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台灣積體電路製造股份有限公司
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Abstract

半導體裝置的形成方法包含接收一結構，此結構具有基底、在基底上方的閘極溝槽以及在基底上方並圍繞閘極溝槽的介電層。此方法更包含在閘極溝槽中形成閘極介電層，在閘極溝槽中的閘極介電層上方形成阻障層，以及處理阻障層以使阻障層的外表面變粗糙，進而成為經處理的阻障層。此方法更包含在經處理的阻障層上方形成n型功函數金屬層。

Description

半導體裝置及其形成方法
本發明實施例係有關於半導體技術，且特別是有關於具有粗糙表面的阻障層的半導體裝置及其形成方法。
半導體積體電路(integrated circuit，IC)工業已經歷了快速成長。在積體電路材料和設計上的技術進步產生了數代積體電路，每一代都比前一代具有更小且更複雜的電路。在積體電路的發展史中，功能密度(即每一晶片區互連的裝置數目)增加，同時幾何尺寸(即製造過程中所產生的最小的組件(或線路))縮小。此元件尺寸微縮化的製程一般來說具有增加生產效率與降低相關費用的益處。此元件尺寸微縮化也增加了積體電路的加工和製造的複雜性。
舉例來說，當製造場效電晶體(field effect transistors，FETs)(例如鰭式場效電晶體(fin-like FETs，FinFETs))時，裝置效能可透過使用高介電常數(high-k)金屬閘極而非一般的多晶矽閘極來改善。高介電常數金屬閘極的功函數可透過選擇高介電常數金屬閘極中的特定功函數金屬層的材料和厚度來調整。隨著場效電晶體持續微縮化，為了進一步加速場效電晶體裝置的運作，期望閘極端子中具有較低的臨界 電壓(threshold voltage，Vt)(與其功函數直接相關)。然而，由於考慮到閘極堆疊工程與製造，因此難以繼續降低現有的高介電常數金屬閘極的功函數，特別是對於n型場效電晶體(NFETs)。舉例來說，為了減少高介電常數介電層與功函數金屬層之間的相互作用，一般會在高介電常數介電層與功函數金屬層之間放置阻障層。阻障層有時會增加金屬閘極的功函數。
在一些實施例中，提供一種半導體裝置的形成方法，此方法包含接收一結構，此結構具有基底、在基底上方的閘極溝槽以及在基底上方並圍繞閘極溝槽的介電層；在閘極溝槽中形成閘極介電層；在閘極溝槽中的閘極介電層上方形成阻障層；處理阻障層以使阻障層的外表面變粗糙，進而成為經處理的阻障層；以及在經處理的阻障層上方形成n型功函數金屬層。
在一些其他實施例中，提供一種半導體裝置的形成方法，此方法包含接收一結構，此結構具有基底、在基底上方的第一閘極溝槽和第二閘極溝槽以及在基底上方並圍繞第一閘極溝槽和第二閘極溝槽的介電層；在第一閘極溝槽和第二閘極溝槽中沉積閘極介電層；在第一閘極溝槽和第二閘極溝槽中的閘極介電層上方沉積阻障層；在第一閘極溝槽和第二閘極溝槽中的阻障層上方沉積p型功函數金屬層；形成覆蓋第二閘極溝槽的圖案化遮罩；移除第一閘極溝槽中的p型功函數金屬層，進而暴露出第一閘極溝槽中的阻障層；在移除第一閘極溝槽中的p型功函數金屬層之後，移除圖案化遮罩；處理第一閘 極溝槽中的阻障層以使阻障層的外表面變粗糙；以及在處理阻障層之後，在第一閘極溝槽和第二閘極溝槽中沉積n型功函數金屬層。
在另外一些實施例中，提供一種半導體裝置，半導體裝置包含基底；閘極堆疊，位於基底上方；以及源極部件和汲極部件，與閘極堆疊相鄰，其中閘極堆疊包含高介電常數介電層；阻障層，位於高介電常數介電層上方，阻障層具有粗糙表面；以及n型功函數金屬層，位於粗糙表面上方。
100‧‧‧裝置
100a‧‧‧n型場效電晶體裝置區域
100b‧‧‧p型場效電晶體裝置區域
101a、101b‧‧‧閘極結構
102‧‧‧基底
104a、104b‧‧‧鰭
104’‧‧‧電晶體通道
106‧‧‧隔離結構
108a、108b‧‧‧源極/汲極區
110‧‧‧暫時性閘極堆疊
112‧‧‧間隔物部件
114‧‧‧層間介電層
116a、116b‧‧‧閘極溝槽
120‧‧‧界面層
122‧‧‧閘極介電層
124‧‧‧覆蓋層
125‧‧‧表面
126、126A‧‧‧阻障層
127‧‧‧圖案化遮罩
128‧‧‧n型功函數金屬層
130‧‧‧p型功函數金屬層
132‧‧‧阻擋層
134‧‧‧金屬填充層
140‧‧‧高介電常數金屬閘極
200‧‧‧方法
202、204、206、208、210、212、214、216、218、220、222、224、226‧‧‧操作
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是，根據本產業的標準慣例，圖示中的各種部件(feature)並未必按照比例繪製。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。
第1圖顯示依據本發明實施例構造之高介電常數金屬閘極堆疊。
第2A和2B圖顯示依據本發明各種實施例之製造半導體裝置的方法的流程圖。
第3、4、5、6、7、8、9、10、11、12、13、14和15圖為依據一些實施例之依據第2A和2B圖的方法形成的半導體裝置的剖面示意圖。
要瞭解的是以下的揭露內容提供許多不同的實施例或範例，以實施提供之主體的不同部件。以下敘述各個構件及其排列方式的特定範例，以求簡化揭露內容的說明。當然， 這些僅為範例並非用以限定本發明。例如，以下的揭露內容敘述了將一第一部件形成於一第二部件之上或上方，即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例，亦包含了尚可將附加的部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與上述第二部件可能未直接接觸的實施例。此外，揭露內容中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語也涵蓋裝置在使用或操作中的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
本發明實施例係有關於半導體裝置，且特別為有關於具有高介電常數金屬閘極的半導體場效電晶體(FET)。本發明實施例的目的在於設計並製造高介電常數金屬閘極，以為n型場效電晶體提供低功函數。
請參照第1圖，其中顯示依據本發明實施例構造之具有設置於基底102上方的高介電常數金屬閘極140的裝置100(有時也被稱為半導體裝置或裝置結構)。特別來說，高介電常數金屬閘極140適用於本發明實施例中的n型場效電晶體。在 一實施例中，裝置100可包含二維(two-dimensional，2D)電晶體，其中高介電常數金屬閘極140僅設置於n型場效電晶體通道的一表面上。在另一實施例中，裝置100可包含三維(three-dimensional，3D)電晶體(例如鰭式場效電晶體或閘極環繞裝置)，其中高介電常數金屬閘極140設置於n型場效電晶體通道的多於一表面上。
本實施例中，高介電常數金屬閘極140包含界面層120、閘極介電層122、覆蓋層124、阻障層126A、n型功函數金屬層128、阻擋層132(有時也被稱為金屬阻擋層)以及金屬填充層134依序地一個堆疊於另一個上方。在一些實施例中，高介電常數金屬閘極140可包含此處未顯示的其他層。在一些其他實施例中，在高介電常數金屬閘極140中可省略第1圖顯示的一些層。
界面層120可包含介電材料，例如氧化矽層(SiO2)或氮氧化矽(SiON)，且可透過使用化學氧化、熱氧化、原子層沉積(atomic layer deposition，ALD)、化學氣相沉積(chemical vapor deposition，CVD)及/或其他合適的方法形成。
閘極介電層122可包含一個或多個高介電常數(例如k>3.9)介電材料，例如氧化矽鉿(HfSiO4)、氧化鉿(HfO2)、氧化鋁(Al2O3)、氧化鋯(ZrO2)、氧化鑭(La2O3)、氧化鈦(TiO2)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3)或前述之組合。閘極介電層122也可被稱為高介電常數介電層。閘極介電層122可透過使用物理氣相沉積(physical vapor deposition，PVD)、化學氣相沉積、原子層沉積及/或其他合適的方法沉積。
在一些實施例中，覆蓋層124可包含鑭基氧化層(例如LaOx)。在一些範例中，覆蓋層124可包含其他層，例如Al2O3層、SiO2層、Y2O3層、氮化鈦(TiN)層、氮化矽鈦(TiSiN)層、前述之組合或其他合適的覆蓋層。覆蓋層124可透過物理氣相沉積、化學氣相沉積、原子層沉積及/或其他合適的方法形成。
在本實施例中，阻障層126A包含金屬氮化物，例如氮化鉭、氮化鈦或前述之組合。阻障層126A可透過物理氣相沉積、化學氣相沉積、原子層沉積及/或其他合適的方法形成。在本實施例中，阻障層126A具有與n型功函數金屬層128相鄰的粗糙表面125，此粗糙表面125有助於降低高介電常數金屬閘極140的功函數，這將在下文詳細討論。
n型功函數金屬層128可包含一層或多層導電材料。特別來說，n型功函數金屬層128包括有著足夠低的有效功函數的金屬，選自鈦(Ti)、鋁(Al)、鋯(Zr)、鉭(Ta)、鈮(Nb)、鈦鋁(TiAl)、碳化鉭(TaC)、氮碳化鉭(TaCN)、氮化矽鉭(TaSiN)、氮化矽鈦(TiSiN)、碳化鋁鈦(TiAlC)或前述之組合的群組，但不限於此。n型功函數金屬層128可透過物理氣相沉積、化學氣相沉積、原子層沉積及/或其他合適的方法形成。特別在本實施例中，n型功函數金屬層128在與阻障層126A接觸的部分包含鋁(Al)。
實驗已顯示粗糙表面125透過降低高介電常數金屬閘極140的有效功函數而有利於高介電常數金屬閘極140。認為粗糙表面125的工作原理如下。由於鋁具有非常低的功函數(約4.1eV)，因此透過在n型功函數金屬層128中具有鋁，可降低 高介電常數金屬閘極140的功函數。然而，n型功函數金屬層128的鋁原子透過例如覆蓋層124和阻障層126A與閘極介電層122隔開。在本實施例中，粗糙表面125被設計為允許n型功函數金屬層128的鋁原子擴散通過阻障層126A。這有效地縮短鋁原子與閘極介電層122之間的距離，其有利於降低高介電常數金屬閘極140的功函數。在一些實施例中，阻障層126A可具有約2nm的(最大)厚度。如果阻障層126A具有均勻厚度而非具有粗糙表面，n型功函數金屬層128的鋁原子將無法擴散通過阻障層126A。
在一實施例中，粗糙表面125具有3-10Å的平均表面粗糙度(average surface roughness，Ra)，其中平均表面粗糙度為粗糙表面125的粗糙輪廓的算術平均值。在另一實施例中，阻障層126A的厚度可在整個粗糙表面125上變化5-18Å。
阻擋層132可包含氮化鈦、氧化鋁鈦或其他合適的材料，且可透過物理氣相沉積、化學氣相沉積、原子層沉積及/或其他合適的方法沉積。金屬填充層134可包含鋁(Al)、鎢(W)、鈷(Co)、銅(Cu)及/或其他合適的材料，且可透過使用化學氣相沉積、物理氣相沉積、電鍍及/或其他合適的製程沉積。
請參照第2A和2B圖，其顯示依據本發明各種實施例之形成半導體裝置(例如裝置100)的方法200的流程圖。特別來說，裝置100被製造為具有有著粗糙阻障層的高介電常數金屬閘極，例如(第1圖的)高介電常數金屬閘極140。方法200僅為一範例，且並非用以將本發明實施例限制在申請專利範圍中明確記載的範圍。在本方法的其他實施例中，可在方法200之前、 期間和之後提供額外的操作，且可取代、刪除或移動所描述的一些操作。下文結合第3-13圖描述方法100，第3-13圖顯示在各種製造階段的裝置100的一部分。裝置100可以是在加工積體電路期間的中間裝置或中間裝置的一部分，此中間裝置可包括靜態隨機存取記憶體(static random access memory，SRAM)及/或其他邏輯電路、被動組件(例如電阻、電容和電感)和主動組件(例如p型場效電晶體(PFETs)、n型場效電晶體(NFETs)、鰭式場效電晶體、金屬氧化物半導體場效電晶體(metal-oxide semiconductor field effect transistor，MOSFET)、互補式金屬氧化物半導體(complementary metal-oxide semiconductor，CMOS))電晶體、雙極性電晶體、高電壓電晶體、高頻電晶體、其他記憶體單元和前述之組合)。
在操作202中，(第2A圖的)方法200接收具有基底102的裝置100，基底102有著各種結構形成於其中及/或其上。請參照第3圖，裝置100包含基底102以及在基底102上方的隔離結構106。隔離結構106將裝置100分為各種裝置區域。在所示的範例中，存在用於形成n型場效電晶體的n型場效電晶體裝置區域100a以及用於形成p型場效電晶體的p型場效電晶體裝置區域100b。在本實施例中，裝置100包含鰭式場效電晶體，且基底102包含向上突出穿過隔離結構106的兩個鰭104a和104b(有時也被稱為主動鰭)。兩個鰭104a和104b分別在n型場效電晶體裝置區域100a和p型場效電晶體裝置區域100b中。進一步來說本實施例，第3-13圖為沿個別鰭104a和104b的鰭長度方向的裝置100的一部分的剖面示意圖，第14圖為沿個別鰭104a 和104b的鰭寬度方向的裝置100的一部分的剖面示意圖。在各種實施例中，n型場效電晶體裝置區域100a和p型場效電晶體裝置區域100b可為連續的或不連續的，且可各自被加工為具有多於一個電晶體。本發明實施例不限於任何特定數量的裝置或裝置區域或任何特定的裝置配置。再者，雖然使用鰭式場效電晶體作為範例，裝置100可替代地或另外地包含二維電晶體(平面電晶體)，這此情況下，第3-13圖為沿通道長度方向的二維電晶體的一部分的剖面示意圖，而第14圖不適用於二維電晶體。再者，第15圖顯示依據本發明實施例構造之具有透過高介電常數金屬閘極環繞的奈米線通道的裝置100的一實施例。
裝置100更包含閘極結構101a和101b，閘極結構101a和101b分別在n型場效電晶體裝置區域100a和p型場效電晶體裝置區域100b中。閘極結構101a和101b的每一者包含暫時性閘極堆疊110(有時也被稱為虛設閘極堆疊)以及在暫時性閘極堆疊110的側壁上的間隔物部件112(有時也被稱為閘極間隙壁)。在之後的製造步驟中，暫時性閘極堆疊110將被高介電常數金屬閘極取代。閘極結構101a和101b的每一者分別與鰭104a和104b的一部分接合。裝置100更包含至少部分地埋置於個別鰭104a和104b中的源極/汲極(source/drain，S/D)區108a和108b(有時也被稱為源極/汲極部件)，且源極/汲極區108a和108b設置於個別閘極結構101a和101b的兩側上。在一些實施例中，源極/汲極區108a和108b可抬升於隔離結構106上方。裝置100更包含圍繞閘極結構101a和101b的層間介電(inter-layer dielectric，ILD)層114。下文將進一步描述裝置100的各種前述 結構。
在本實施例中，基底102為矽基底。或者，基底102可包括另一元素半導體(例如鍺)、化合物半導體(包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、合金半導體(包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP或前述之組合)。或者，基底102為絕緣層上覆半導體(semiconductor-on-insulator，SOI)，例如具有埋置介電層。
在本實施例中，鰭104a適用於形成n型鰭式場效電晶體，鰭104b適用於形成p型鰭式場效電晶體。此配置僅用於顯示目的，但不用於限制本發明實施例。鰭104a和104b可透過使用合適的製程(包含雙重圖案化或多重圖案化製程)製造。一般來說，雙重圖案化或多重圖案化製程結合光微影和自對準製程，以創建具有比其他方式(例如使用單一的直接光微影製程)可獲得之更小間距的圖案。舉例來說，在一實施例中，犧牲層形成於基底上方並透過使用光微影製程圖案化。間隙壁透過使用自對準製程沿著圖案化犧牲層形成。接著，移除犧牲層，且接著透過蝕刻基底102的初始磊晶半導體層，可使用餘留的間隙壁(有時也被稱為心軸)來圖案化鰭104a和104b。此蝕刻製程可包含乾蝕刻、濕蝕刻、反應性離子蝕刻(reactive ion etching，RIE)及/或其他合適製程。舉例來說，乾蝕刻可施加含氧氣體、含氟氣體(例如CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯氣體(例如Cl2、CHCl3、CCl4及/或BCl3)、含溴氣體(例如HBr及/或CHBr3)、含碘氣體、其他合適氣體及/或電漿及/或前述之組合。舉例來說，濕蝕刻製程可包括在稀釋氫氟酸(diluted hydrofluoric acid，DHF)、氫氧化鉀(KOH)溶液、氨、包含氫氟酸(HF)、硝酸(HNO3)及/或醋酸(CH3COOH)或其他合適的濕蝕刻劑中蝕刻。
隔離結構106可包含氧化矽、氮化矽、氮氧化矽、摻氟矽玻璃(fluoride-doped silicate glass，FSG)、低介電常數介電材料及/或其他合適的絕緣材料。隔離結構106可為淺溝槽隔離(shallow trench isolation，STI)部件。在一實施例中，隔離結構106可透過在基底102中蝕刻出溝槽(例如作為鰭104a和104b形成製程的一部分)形成。接著，可以隔離材料填充溝槽，接著進行化學機械平坦化(chemical mechanical planarization，CMP)製程及/或回蝕刻製程。也可能使用其他隔離結構，例如場氧化物、矽局部氧化(Local Oxidation of Silicon，LOCOS)及/或其他合適的結構。隔離結構106可包含多層結構，例如具有一個或多個熱氧化物襯墊層。
在本實施例中，暫時性閘極堆疊110接合在鰭104a和104b的兩側或三側上。暫時性閘極堆疊110可包含一個或多個材料層，例如氧化層、多晶矽層、硬遮罩層和其他合適層。暫時性閘極堆疊110中的各種層可透過合適的沉積技術形成。舉例來說，氧化層可透過化學氧化、熱氧化、原子層沉積、化學氣相沉積及/或其他合適的方法形成。舉例來說，多晶矽層可透過合適的沉積製程(例如低壓化學氣相沉積(low-pressure CVD，LPCVD)和電漿增強化學氣相沉積(plasma-enhanced CVD，PECVD))形成。在一實施例中，暫時性閘極堆疊110首先作為毯覆層沉積。接著，毯覆層透過包含光微影製程和蝕刻 製程的製程圖案化，進而移除毯覆層的一部分，並保留一部分在隔離結構106以及鰭104a和104b上方作為暫時性閘極堆疊110。
間隔物部件112形成於暫時性閘極堆疊110的側壁上。間隔物部件112包含材料不同於暫時性閘極堆疊110的材料。在一實施例中，間隔物部件112包含介電材料，例如氮化矽或氮氧化矽。在一範例中，間隔物部件112包含多層，例如與暫時性閘極堆疊110相鄰的密封層以及與密封層相鄰的主要間隔層。在一實施例中，透過在裝置100上方毯覆式沉積間隔物材料來形成一個或多個間隔層。接著，進行非等向性蝕刻製程以移除間隔層的一部分，以形成第3圖所示的間隔物部件112。
源極/汲極區108a和108b可透過各種技術形成，例如蝕刻製程接著一個或多個磊晶製程。在一範例中，進行一個或多個蝕刻製程來移除鰭104a和104b的一部分，以在其中形成凹口。以氫氟酸(HF)溶液或其他合適溶液進行清洗凹口的清洗製程。之後，進行一個或多個磊晶成長製程，以在凹口中成長半導體部件(例如用於n型場效電晶體的矽以及用於p型場效電晶體的矽鍺)。磊晶成長製程可以用於形成p型鰭式場效電晶體的p型摻雜劑或用於形成n型鰭式場效電晶體的n型摻雜劑原位(in-situ)或非原位(ex-situ)摻雜成長半導體。
層間介電層114形成於基底102上方。在實施例中，裝置100更包含在層間介電層114下方的蝕刻停止層(例如氮化矽層)。層間介電層114可包含例如四乙氧基矽烷 (tetraethylorthosilicate，TEOS)氧化物、未摻雜矽玻璃或摻雜氧化矽(例如硼磷矽玻璃(borophosphosilicate glass，BPSG)、融熔矽石玻璃(fused silica glass，FSG)、磷矽玻璃(phosphosilicate glass，PSG)、摻雜硼的矽玻璃(boron doped silicon glass，BSG)及/或其他合適的介電材料)。層間介電層114可透過電漿增強化學氣相沉積製程或流動式化學氣相沉積(flowable CVD，FCVD)製程沉積。在各種沉積製程之後，進行化學機械平坦化(CMP)製程平坦化層間介電層114的頂表面，並暴露出暫時性閘極堆疊110的頂表面，以用於後續製造步驟。
在操作204中，(第2A圖的)方法200移除暫時性閘極堆疊110。請參照第4圖，兩個閘極溝槽116a和116b(有時也簡稱為溝槽)進而分別形成於閘極結構101a和101b中，暴露出鰭104a和104b。閘極溝槽116a和116b透過上述的結構(例如間隔物部件112和層間介電層114)圍繞。在一實施例中，操作204包含選擇性地調整以移除(第3圖的)暫時性閘極堆疊110而大致保留間隔物部件112和層間介電層114的一個或多個蝕刻製程。此蝕刻製程可包含合適的濕蝕刻、乾(電漿)蝕刻及/或其他製程。舉例來說，乾蝕刻製程可使用含氯氣體、含氟氣體、其他蝕刻氣體或前述之組合。濕蝕刻溶液可包含NH4OH、HF、稀釋HF、去離子水、氫氧化四甲基銨(tetramethylammonium hydroxide，TMAH)、其他合適的濕蝕刻溶液或前述之組合。
在操作206中，(第2A圖的)方法200在閘極溝槽116a和116b中形成界面層120。在操作208中，(第2A圖的)方法200在閘極溝槽116a和116b中的界面層120上方形成閘極介電層 122。在操作210中，(第2A圖的)方法200在閘極溝槽116a和116b中的閘極介電層122上方形成覆蓋層124。在操作206、208和210之後，所得到的裝置100顯示於第5圖中。界面層120可包含SiO2、SiON或其他合適的介電材料，且可透過化學氧化、熱氧化、原子層沉積及/或其他合適的方法形成。在本實施例中，閘極介電層122包含高介電常數介電材料，例如HfO2、Al2O3、TiO2、La2O3、HfSiO4、ZrO2、Y2O3、SrTiO3、前述之組合或其他合適的材料。閘極介電層122可透過原子層沉積及/或其他合適的方法形成。覆蓋層124可包含鑭基氧化物、SiO2、Y2O3、TiN、TiSiN、TaN、前述之組合或其他合適的覆蓋層，且可透過原子層沉積及/或其他合適的方法形成。覆蓋層124被設計為保護閘極介電層122免受從覆蓋層124上或上方的其他層擴散的金屬雜質影響。
在操作212中，(第2A圖的)方法200在閘極溝槽116a和116b中的覆蓋層124上方形成阻障層126。請參照第6圖，在本實施例中，阻障層126包含金屬氮化物。舉例來說，阻障層126可包含氮化鉭、氮化鈦、氮化鈮或前述之組合，也可能為各種其他材料。在一實施例中，阻障層126透過原子層沉積、物理氣相沉積、化學氣相沉積或其他合適的方法形成。在本實施例中，阻障層126具有約10-20Å的厚度。阻障層126的一個目的為保護覆蓋層124免受用於調整臨界電壓之功函數金屬層圖案化期間的各種蝕刻製程影響。舉例來說，p型功函數金屬可同時沉積於閘極溝槽116a和116b中，接著以n型功函數金屬取代p型功函數金屬在閘極溝槽116a的部分，以在n型場效電晶體 裝置區域100a中形成n型場效電晶體。也可完成相反的情況，即在兩個溝槽中皆沉積n型功函數金屬，接著在閘極溝槽116b中以p型功函數金屬取代n型功函數金屬。在任一情況中，如果沒有阻障層126，在金屬圖案化/移除製程期間，可能不利地蝕刻覆蓋層124，部分原因是由於用於圖案化/移除金屬層的蝕刻劑的蝕刻選擇性差。如過覆蓋層124受到損害，閘極介電層122也將受到損害。因此，期望具有阻障層126來保護覆蓋層124。然而，具有阻障層126也增加了閘極介電層122與將沉積於阻障層126上方的功函數金屬層之間的距離，這將不利地增加n型場效電晶體的功函數。本發明實施例旨在減少這種影響，而同時具有阻障層126作為覆蓋層124的蝕刻保護層。
在操作214中，(第2A圖的)方法200在閘極溝槽116a和116b中沉積p型功函數金屬層130，如第7圖所示。p型功函數金屬層130包括有著足夠大的有效功函數金屬，其選自氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、鎢(W)、鉑(Pt)或前述之組合的群組，但不限於此。p型功函數金屬層130可包含一層或多層材料。p型功函數金屬層130可透過化學氣相沉積、物理氣相沉積、原子層沉積及/或其他合適的製程沉積。
在操作216中，(第2B圖的)方法200形成覆蓋p型場效電晶體裝置區域100b的圖案化遮罩127。請參照第8圖，在一實施例中，圖案化遮罩127包含以光微影製程圖案化的阻劑(有時也被稱為光阻)，且可更包含阻劑下層(例如底部抗反射塗層(bottom anti-reflective coating，BARC))。光微影製程可包含形成覆蓋基底102的阻劑層，將阻劑暴露於圖案，進行曝光後烘 烤製程，以及將阻劑顯影以移除在n型場效電晶體裝置區域100a上方的部分，以形成圖案化遮罩127。
在操作218中，(第2B圖的)方法200透過一個或多個蝕刻製程(例如濕蝕刻、乾蝕刻、反應性離子蝕刻及/或原子層蝕刻)移除閘極溝槽116a中的p型功函數金屬層130。在一實施例中，此蝕刻製程將具有磷酸的蝕刻劑施加於p型功函數金屬層130。此外，蝕刻劑可包含其他組成成分，例如過氧化氫(H2O2)、硝酸(HNO3)、硫酸(H2SO4)、去離子水(deionized water，DIW)、氫氧化銨(NH4OH)、臭氧(O3)、氫氟酸(HF)、鹽酸(HCl)、其他酸性溶液和有機氧化劑或前述之組合。此蝕刻製程被設計為對p型功函數金屬層130有選擇性，且不(或不顯著地)蝕刻阻障層126。在閘極溝槽116a中的阻障層126有效地保護覆蓋層124免受蝕刻製程影響。換句話說，蝕刻閘極溝槽116a中的p型功函數金屬層130停止於阻障層126。在操作218之後，移除閘極溝槽116a中的p型功函數金屬層130，但保留閘極溝槽116b中的p型功函數金屬層130，如第9圖所示。在此蝕刻製程期間，圖案化遮罩127保護p型場效電晶體裝置區域100b中的結構。
在操作220中，(第2B圖的)方法200透過使用例如阻劑剝離或灰化的製程來移除p型場效電晶體裝置區域100b的圖案化遮罩127，所得到的結構顯示於第10圖中。
在操作222中，(第2B圖的)方法200處理閘極溝槽116a中的阻障層，以使(第11圖的)阻障層126的表面125變粗糙。經處理的阻障層以符號126A標示，以與在p型場效電晶體裝置區域100b中之未處理的阻障層126區隔。在一實施例中， 操作222將含氯氣體(例如金屬氯化物氣體)施加於阻障層126。在一些實施例中，可以氬氣稀釋含氯氣體。在本實施例中，例如因為在操作212沉積阻障層126之後暴露於大氣的緣故，阻障層126的表面部分包含氧化物(阻障層126A的氧化部分)。舉例來說，如果阻障層126含有氮化鉭(TaN)，則阻障層126A的表面中具有一些氧化鉭(Ta2O5)。含氯氣體與氧化物反應，導致粗糙表面125。在一實施例中，此處理在約400-500℃的溫度中進行。選擇此溫度以增加反應速度，同時保持裝置100的各種結構(例如源極/汲極區108a/108b、閘極介電層122等)的完整性。如果溫度太高，可能損壞裝置100的一些現有結構。如果溫度太低，此製程可能需要不期望的長時間。在另一實施例中，此處理在約10-35Torr的壓力下進行，此壓力為針對表面125所期望的粗糙度調整。
在一範例中，含氯氣體包含氯化鈦(TiCl5)、氯化鉭(TaCl5)、氯化鎢(WCl5)或前述之組合。在另一範例中，含氯氣體可包含氯化鎢(WClx)，例如WCl2、WCl3、WCl4、WCl5、WCl6或前述之混合物。舉例來說，WCl5氣體可與Ta2O5固體反應，以產生WOCly氣體與TaClx固體。然後，可將WOCly氣體從反應腔體抽出。透過此取代反應，可部分或完全地移除阻障層126A的氧化部分，導致粗糙表面125。在一實施例中，阻障層126A的厚度可在整層上變化5-18Å，且表面125具有3-10Å的平均表面粗糙度(Ra)，其中平均表面粗糙度為表面125的粗糙輪廓的算術平均值。在各種實施例中，可調整處理製程的溫度和壓力，以在表面125上達到所期望的表面粗糙度。在一些實施 例中，由於處理的緣故，阻障層126A變得比阻障層126薄約10Å。舉例來說，阻障層126的厚度為約15-20Å，而經處理的阻障層126A的厚度為約5-10Å。期望經處理的阻障層126A的厚度與多少從n型功函數金屬層(例如第1圖的n型功函數金屬層128)通過阻障層126A的金屬擴散(例如Al擴散)相關。可設計並調整阻障層126A的厚度和粗糙度來達到裝置功函數的要求。
在本實施例中，操作222在處理阻障層126的同時，也處理閘極溝槽116b中的p型功函數金屬層130。選擇各種處理製程和化學物來與p型功函數金屬層130的材料合作，而不會使p型功函數金屬層130退化。
在操作224中，(第2B圖的)方法200在閘極溝槽116a和116b中沉積n型功函數金屬層128，例如第12圖所示。特別來說，n型功函數金屬層128沉積於閘極溝槽116a中的經處理的阻障層126A上方，且沉積於閘極溝槽116b的p型功函數金屬層130上方。在本實施例中，例如在相同製程腔體或在相同群集工具中進行操作222和224而不破壞其間的真空。n型功函數金屬層128包含適用於在n型場效電晶體裝置區域100a中形成n型場效電晶體的一種或多種材料。舉例來說，n型功函數金屬層128可包括有著足夠低的有效功函數的金屬，其選自Ti、Al、Zr、Ta、Nb、TiAl、TaC、TaCN、TaSiN、TiSiN、TiAlC、TiAlN或前述之組合的群組，但不限於此。在一範例中，n型功函數金屬層128具有約10-50Å的厚度。n型功函數金屬層128可透過物理氣相沉積、化學氣相沉積、原子層沉積及/或其他合適的方法形成。特別在本實施例中，n型功函數金屬層128在靠近表面125 的部分包含Al並與表面125直接接觸。由於粗糙表面125的緣故，阻障層126A的一部分足夠薄以使鋁原子擴散通過。
實驗已顯示氧濃度(或含量)從覆蓋層124至阻障層126A以及從阻障層126A至n型功函數金屬層128逐漸降低。同時，鋁濃度在n型功函數金屬層128的下部(最靠近阻障層126A)處最高，其次是阻障層126A和n型功函數金屬層128的上部(較遠離阻障層126A)，接著是阻障層126A與覆蓋層124之間的界面，然後是覆蓋層124。在本實施例中，鋁濃度依上述此順序降低。鋁原子在各種層(n型功函數金屬層128、阻障層126A和覆蓋層124)中的分布證實了鋁原子已擴散通過粗糙的阻障層126A。具有靠近閘極介電層122的鋁原子有助於降低閘極結構101a的功函數。在各種實施例中，其他類型的n型功函數金屬原子(例如Ti和Zr)也可擴散通過粗糙的阻障層126A並移動靠近閘極介電層122，其有助於降低閘極結構101a的功函數。
在操作226中，(第2B圖的)方法200對裝置100進行進一步的步驟。舉例來說，操作226可在閘極溝槽116a和116b中沉積阻擋層132和金屬填充層134，如第13圖所示。阻擋層132可包含氮化鈦、氧化鋁鈦或其他合適的材料，且可透過物理氣相沉積、化學氣相沉積、原子層沉積及/或其他合適的方法沉積。金屬填充層134可包含鋁(Al)、鎢(W)、鈷(Co)、銅(Cu)及/或其他合適的材料，且可透過使用例如化學氣相沉積、物理氣相沉積、電鍍及/或其他合適的製程的方法沉積。操作226可進行化學機械平坦化(CMP)製程來從閘極結構101a/101b移除多餘材料。操作226可更形成接點和導通孔電性連接源極/汲極區 108a/108b和閘極結構101a/101b並形成金屬內連線將鰭式場效電晶體連接至裝置100的其他部分，以形成完整的積體電路。
第14圖顯示依據一實施例之裝置100的一部分(沿鰭寬度的方向)的剖面示意圖。並非裝置100的所有部件皆顯示於第14圖中。請參照第14圖，在n型場效電晶體裝置區域100a中，裝置100包含基底102、隔離結構106、鰭104a和閘極結構101a(有時也被稱為n型高介電常數金屬閘極堆疊)。在p型場效電晶體裝置區域100b中，裝置100包含基底102、隔離結構106、鰭104b和閘極結構101b(有時也被稱為p型高介電常數金屬閘極堆疊，或簡稱為閘極堆疊)。閘極結構101a和101b的每一者包含在個別鰭104a/104b上的界面層120、閘極介電層122和覆蓋層124。閘極結構101a更包含在覆蓋層124上方的粗糙的阻障層126A以及在粗糙的阻障層126A上方的n型功函數金屬層128。閘極結構101b更包含在覆蓋層124上方的阻障層126以及在阻障層126上方的p型功函數金屬層130。
第15圖顯示裝置100的一實施例，其中電晶體通道104’為奈米線而非鰭。至少閘極結構101a的界面層120、閘極介電層122、覆蓋層124和阻障層126A環繞電晶體通道104’。阻障層126A具有粗糙的外側表面125。n型功函數金屬層128設置於粗糙的外側表面125周圍，其有助於n型功函數金屬層128的一些金屬原子(例如鋁原子)擴散通過阻障層126A。
雖然不意圖限制，但是本發明的一個或多個實施例為半導體裝置及其形成提供許多益處。舉例來說，本發明的實施例為n型場效電晶體提供新穎的高介電常數金屬閘極堆 疊，其中高介電常數金屬閘極堆疊包含在n型功函數金屬層與高介電常數介電層之間的粗糙的阻障層。粗糙的阻障層有助於使n型金屬原子(例如鋁原子)更靠近高介電常數介電層，進而降低高介電常數金屬閘極的功函數。上述半導體裝置的形成方法可容易地集成至現有的半導體製造製程中。
在一例示性的方面，本發明實施例為有關於半導體裝置的形成方法。此方法包含接收一結構，此結構具有基底、在基底上方的閘極溝槽以及在基底上方並圍繞閘極溝槽的介電層。此方法更包含在閘極溝槽中形成閘極介電層，在閘極溝槽中的閘極介電層上方形成阻障層，以及處理阻障層以使阻障層的外表面變粗糙，進而成為經處理的阻障層。此方法更包含在經處理的阻障層上方形成n型功函數金屬層。
在此方法的一實施例中，n型功函數金屬層包含鋁(Al)。在另一實施例中，阻障層包含氮化鉭(TaN)或氮化鈦(TiN)。在另一實施例中，處理阻障層的步驟包含將含氯氣體施加於阻障層。在一範例中，含氯氣體包含氯化鎢(WClx)。
在此方法的一實施例中，將阻障層的外表面變粗糙至具有在3-10Å的平均表面粗糙度(Ra)。在此方法的另一實施例中，處理阻障層的步驟在400-500℃的溫度範圍以及在10-35Torr的壓力範圍中進行。在另一實施例中，此方法更包含在閘極介電層與阻障層之間形成一覆蓋層。
在另一例示性的方面，本發明實施例為有關於半導體裝置的形成方法。此方法包含接收一結構，此結構具有基底、在基底上方的第一閘極溝槽和第二閘極溝槽以及在基底上 方並圍繞第一閘極溝槽和第二閘極溝槽的介電層。此方法更包含在第一閘極溝槽和第二閘極溝槽中形成閘極介電層，以及在第一閘極溝槽和第二閘極溝槽中的閘極介電層上方形成阻障層，此方法更包含在第一閘極溝槽和第二閘極溝槽中的阻障層上方沉積p型功函數金屬層，形成覆蓋第二閘極溝槽的圖案化遮罩，以及移除第一閘極溝槽中的p型功函數金屬層，進而暴露出第一閘極溝槽中的阻障層。此方法更包含在移除第一閘極溝槽中的p型功函數金屬層之後，移除圖案化遮罩，以及處理第一閘極溝槽中的阻障層以使阻障層的外表面變粗糙。此方法更包含在處理阻障層之後，在第一閘極溝槽和第二閘極溝槽中沉積n型功函數金屬層。
在此方法的一實施例中，處理阻障層以及沉積n型功函數金屬層的步驟在不破壞真空的情況下進行。在另一實施例中，此方法更包含在形成阻障層之前，在閘極介電層上方形成覆蓋層。
在此方法的一實施例中，閘極介電層包含高介電常數介電層，阻障層包含金屬氮化物，且n型功函數金屬層包含鋁。
在另一實施例中，此方法更包含在第一閘極溝槽和第二閘極溝槽中的n型功函數金屬層上方沉積金屬阻擋層。
在此方法的一實施例中，處理阻障層的步驟包含將金屬氯化物氣體施加於第一閘極溝槽中的阻障層。在另一實施例中，金屬氯化物氣體包含氯化鎢。
在另一例示性的方面，本發明實施例為有關於半 導體裝置。此半導體裝置包含基底，閘極堆疊位於基底上方，以及源極部件和汲極部件與閘極堆疊相鄰。閘極堆疊包含高介電常數介電層，阻障層位於高介電常數介電層上方，阻障層具有粗糙表面，以及n型功函數金屬層位於粗糙表面上方。
在半導體裝置的一實施例中，粗糙表面具有3-10Å的平均表面粗糙度。在一實施例中，半導體裝置更包含覆蓋層位於高介電常數介電層與阻障層之間。在半導體裝置的另一實施例中，n型功函數金屬層包含鋁和鈦，阻障層包含鋁以及氮化鈦和氮化鉭的其中一者，且閘極堆疊在阻障層與高介電常數介電層之間更包含鋁。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下，可對本發明進行各種改變、置換或修改。

Claims (14)

  1. 一種半導體裝置的形成方法，包括：接收一結構，該結構具有一基底、在該基底上方的一閘極溝槽以及在該基底上方並圍繞該閘極溝槽的一介電層；在該閘極溝槽中形成一閘極介電層；在該閘極溝槽中的該閘極介電層上方形成一阻障層；處理該阻障層以使該阻障層的外表面變粗糙，進而成為一經處理的阻障層；以及在該經處理的阻障層上方形成一n型功函數金屬層。
  2. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中該n型功函數金屬層包含鋁(Al)。
  3. 如申請專利範圍第1或2項所述之半導體裝置的形成方法，其中該阻障層包含氮化鉭(TaN)或氮化鈦(TiN)。
  4. 如申請專利範圍第3項所述之半導體裝置的形成方法，其中處理該阻障層的步驟包含將一含氯氣體施加於該阻障層。
  5. 如申請專利範圍第1或2項所述之半導體裝置的形成方法，其中處理該阻障層的步驟在400-500℃的溫度範圍以及在10-35Torr的壓力範圍中進行。
  6. 如申請專利範圍第1或2項所述之半導體裝置的形成方法，更包括在該閘極介電層與該阻障層之間形成一覆蓋層。
  7. 一種半導體裝置的形成方法，包括：接收一結構，該結構具有一基底、在該基底上方的一第一閘極溝槽和一第二閘極溝槽以及在該基底上方並圍繞該第一閘極溝槽和該第二閘極溝槽的一介電層；在該第一閘極溝槽和該第二閘極溝槽中沉積一閘極介電層；在該第一閘極溝槽和該第二閘極溝槽中的該閘極介電層上方沉積一阻障層；在該第一閘極溝槽和該第二閘極溝槽中的該阻障層上方沉積一p型功函數金屬層；形成覆蓋該第二閘極溝槽的一圖案化遮罩；移除該第一閘極溝槽中的該p型功函數金屬層，進而暴露出該第一閘極溝槽中的該阻障層；在移除該第一閘極溝槽中的該p型功函數金屬層之後，移除該圖案化遮罩；處理該第一閘極溝槽中的該阻障層以使該阻障層的外表面變粗糙；以及在處理該阻障層之後，在該第一閘極溝槽和該第二閘極溝槽中沉積一n型功函數金屬層。
  8. 如申請專利範圍第7項所述之半導體裝置的形成方法，其中處理該阻障層以及沉積該n型功函數金屬層的步驟在不破壞真空的情況下進行。
  9. 如申請專利範圍第7或8項所述之半導體裝置的形成方法，其中該閘極介電層包含一高介電常數介電層，該阻障層包含一金屬氮化物，且該n型功函數金屬層包含鋁。
  10. 如申請專利範圍第7或8項所述之半導體裝置的形成方法，更包括在該第一閘極溝槽和該第二閘極溝槽中的該n型功函數金屬層上方沉積一金屬阻擋層。
  11. 一種半導體裝置，包括：一基底；一閘極堆疊，位於該基底上方；以及一源極部件和一汲極部件，與該閘極堆疊相鄰，其中該閘極堆疊包含：一高介電常數介電層；一阻障層，位於該高介電常數介電層上方，該阻障層具有一粗糙表面；以及一n型功函數金屬層，位於該粗糙表面上方。
  12. 如申請專利範圍第11項所述之半導體裝置，更包括一覆蓋層，位於該高介電常數介電層與該阻障層之間。
  13. 如申請專利範圍第12項所述之半導體裝置，其中該n型功函數金屬層與該阻障層的每一者包含鋁，且其中該閘極堆疊在該阻障層與該覆蓋層之間也包含鋁。
  14. 如申請專利範圍第11、12或13項所述之半導體裝置，其中該n型功函數金屬層包含鋁和鈦，且該阻障層包含鋁以及氮化鈦和氮化鉭的其中一者，其中該閘極堆疊在該阻障層與該高介電常數介電層之間更包含鋁。
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