TWI644363B - 半導體結構及其形成方法 - Google Patents
半導體結構及其形成方法 Download PDFInfo
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- TWI644363B TWI644363B TW106135777A TW106135777A TWI644363B TW I644363 B TWI644363 B TW I644363B TW 106135777 A TW106135777 A TW 106135777A TW 106135777 A TW106135777 A TW 106135777A TW I644363 B TWI644363 B TW I644363B
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- 238000000034 method Methods 0.000 title claims abstract description 171
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 46
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 46
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims description 37
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- 239000002019 doping agent Substances 0.000 claims description 29
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 23
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 238000004140 cleaning Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 13
- 238000011049 filling Methods 0.000 claims description 4
- 230000000717 retained effect Effects 0.000 claims description 2
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- 238000001312 dry etching Methods 0.000 description 15
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- 229910052757 nitrogen Inorganic materials 0.000 description 10
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 9
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
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- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 3
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- 229910000838 Al alloy Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
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- 150000004706 metal oxides Chemical group 0.000 description 2
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 2
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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- 239000010937 tungsten Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
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- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910019044 CoSix Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
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- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
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- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
- OQNXPQOQCWVVHP-UHFFFAOYSA-N [Si].O=[Ge] Chemical compound [Si].O=[Ge] OQNXPQOQCWVVHP-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
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- 229910002090 carbon oxide Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- 150000001875 compounds Chemical class 0.000 description 1
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- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
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- 238000000926 separation method Methods 0.000 description 1
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- 235000012239 silicon dioxide Nutrition 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
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- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
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Abstract
文中描述了包含主動鰭式結構、虛設鰭式結構、磊晶層、含鍺氧化層之半導體結構及其製造方法。自對準磊晶製程可藉由實行含鍺氧化層於鰭式場效電晶體元件之源極/汲極區域上之磊晶層表面而實現。藉由實行虛擬鰭式結構以及自對準蝕刻,則可使磊晶層與鄰近鰭式場效電晶體元件之金屬閘極結構皆以自對準方式被分隔開。
Description
本揭露是有關於一種鰭式場效電晶體元件結構以及其形成方法。
半導體元件之製造隨著其尺寸日漸縮減而越發困難。製造這些元件的挑戰之一為精確地用微影技術自不同層圖案化這些結構。例如,元件之間距日漸縮減使得相鄰的FinFET間之圖案化及對準結構變得更具挑戰性。例示性之挑戰包含成長磊晶層於相鄰的FinFET之源極/汲極區域而不與不同鰭上之磊晶層融合,及圖案化閘極電極於並列之相鄰的FinFET。
根據本揭露之一些實施方式,提出一種半導體元件結構,包含一基材、一第一鰭式結構、一第二鰭式結構、一第一磊晶層、一第二磊晶層、一第三鰭式結構以及一含鍺(Ge)氧化層。第一鰭式結構自基材突出且摻雜有n型摻雜物。第二鰭式結構自基材突出且上段摻雜有p型摻雜物。第一磊晶層形成於第一鰭式結構之源極/汲極區域上。第二磊晶層形成於第二鰭式結構之源極/汲極區域上。第三鰭式結構形成於第一鰭
式結構與第二鰭式結構之間以及第一磊晶層與第二磊晶層之間,其中第三鰭式結構以不同於第一鰭式結構以及第二鰭式結構之材料所形成。含鍺氧化層形成於第二磊晶層上。
根據本揭露之一些實施方式,提出一種半導體元件結構之形成方法,包含:形成複數個第一鰭式結構突出於一基材;摻雜n型摻雜物於第一鰭式結構之一第一部位;摻雜p型摻雜物於第一鰭式結構之一第二部位;形成至少一第二鰭式結構於每一第一鰭式結構之間;成長一鍺化矽(SiGe)磊晶層於第一鰭式結構之第二部位之源極/汲極區域上;形成一含鍺氧化層於鍺化矽磊晶層上;以及成長一矽(Si)磊晶層於第一鰭式結構之第一部位之源極/汲極區域上。
根據本揭露之一些實施方式,提出一種半導體元件結構,包含:一基材、複數個第一鰭式結構、複數個第二鰭式結構、一介電層、複數個虛設鰭式結構、一鍺化矽磊晶層、一含鍺氧化層以及一矽磊晶層。第一鰭式結構摻雜有n型摻雜物且突出於基材。第二鰭式結構突出於基材且平行於第一鰭式結構,其中第二鰭式結構具有摻雜有p型摻雜物之上段。介電層形成於基材上以及第一鰭式結構與第二鰭式結構中之每一者之側表面上,其中介電層之頂表面低於第一鰭式結構以及第二鰭式結構之頂表面。虛設鰭式結構平行於第一鰭式結構以及第二鰭式結構,其中虛設鰭式結構中之至少一者係形成於每一第一鰭式結構以及每一第二鰭式結構之間,且其中虛設鰭式結構之底表面低於介電質之頂表面。鍺化矽磊晶層形成於第二鰭式結構上。含鍺氧化層形成於鍺化矽磊晶層上。矽磊晶層形成於第一鰭式結構上。
102‧‧‧基材
104‧‧‧主動鰭式結構
106‧‧‧上段
108‧‧‧硬遮罩層
110‧‧‧氧化物墊層
112‧‧‧第一介電層
114‧‧‧凹槽
116‧‧‧虛設鰭式結構
118‧‧‧閘極氧化層
120‧‧‧多晶矽閘極電極
121‧‧‧虛設閘極結構
122‧‧‧氮硬遮罩
124‧‧‧氧化物硬遮罩
126‧‧‧間隔物
128‧‧‧光阻層
130‧‧‧氧化鋁層
132‧‧‧磊晶層
134‧‧‧含鍺氧化層
136‧‧‧自對準磊晶層
138‧‧‧第二介電層
140‧‧‧接觸蝕刻停止層
142‧‧‧光阻層
144、146‧‧‧開口
148‧‧‧金屬閘極電極
150‧‧‧閘極介電層
152‧‧‧源極/汲極接觸區
154‧‧‧矽化物層
1702~1732‧‧‧步驟
為讓本揭露更明顯易懂,所附圖式將於下文中詳細說明。應瞭解到,這些圖式並非繪示各元件的實際尺寸。為了清楚表達這些實施方式中各元件之間的連接關係,將於圖式中將元件尺寸增加或縮減。
第1A圖至第1C圖為根據本揭露之一些實施方式分別繪示主動鰭式結構形成後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第2A圖至第2C圖為根據本揭露之一些實施方式分別繪示介電層形成後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第3A圖至第3C圖為根據本揭露之一些實施方式分別繪示虛設鰭式結構形成後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第4A圖至第4C圖為根據本揭露之一些實施方式分別繪示使介電層凹陷後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第5A圖至第5C圖為根據本揭露之一些實施方式分別繪示閘極氧化物形成後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第6A圖至第6C圖為根據本揭露之一些實施方式分別繪示虛設閘極結構形成後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第7A圖至第7C圖為根據本揭露之一些實施方式分別繪示使虛設鰭式結構凹陷後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第8A圖至第8C圖為根據本揭露之一些實施方式分別繪示圖案化p型FinFET元件之源極/汲極區域後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第9A圖至第9C圖為根據本揭露之一些實施方式分別繪示磊晶成長於p型FinFET元件之源極/汲極區域上後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第10A圖至第10C圖為根據本揭露之一些實施方式分別繪示成長含鍺氧化層於p型FinFET元件之源極/汲極區域上之磊晶層上後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第11A圖至第11C圖為根據本揭露之一些實施方式分別繪示磊晶成長於n型FinFET元件之源極/汲極區域上後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第12A圖至第12C圖為分別繪示另一介電層形成後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第13A圖至第13C圖為根據本揭露之一些實施方式分別繪示虛設閘極結構以及虛設鰭式結構之自對準蝕刻後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第14A圖至第14C圖為根據本揭露之一些實施方式分別繪示移除虛設閘極結構後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第15A圖至第15C圖為根據本揭露之一些實施方式分別繪示形成金屬閘極結構後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第16A圖至第16C圖為根據本揭露之一些實施方式分別繪示形成源極/汲極接觸區後之部分製造的鰭式結構的等角視圖、剖面圖以及上視圖。
第17圖為根據本揭露之一些實施方式所繪示之製造鰭式結構之例示性方法的流程圖。
以下將以不同實施方式實施例揭露本揭露之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本揭露。也就是說,在本揭露部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。並且,除非有其他表示,在不同圖式中相同之元件符號可視為相對應的元件。這些圖式之繪示是為了清楚表達這些實施方式中各元件之間的連接關係,並非繪示各元件的實際尺寸。
此外,相對空間詞彙,如『下方』、『下』、『底部』、『上』、以及『頂部』等,用來描述文中在圖式中所示的一元件與另一元件之關係。相對空間詞彙用來描述裝置在圖式中所描述之外的不同方位是可以被理解的。如果圖式中的元件被轉至不同方向(旋轉90度或轉至其他另一方向),則元件將
會根據圖示以不同之相對空間詞彙描述。
此處所使用之縮寫字“FET”係指場效電晶體(field effect transistor)。場效電晶體之一例子為金屬氧化半導體場效電晶體(MOSFET)。MOSFETs可為以下例子:建立在基材之平面如半導體晶圓內以及上方之(i)平面結構或是(ii)垂直結構。
此處使用之詞彙“鰭式場效電晶體”係指形成於相對垂直於晶圓平面之鰭結構上之FET。
“S/D”係指形成FET終端的源極及/或汲極接面。
此處使用之詞彙“標稱”係指元件或製程執行中的特徵或參數之期望值或目標值。一特徵或參數的標稱可於產品或製程之設計階段制定,且可為一大於和/或小於期望數值之一數值範圍。此數值範圍可來自於製造過程之差異或公差。
此處使用之詞彙“垂直”係指標準地正交於一基板之平面。
“磊晶層”係用以表達單一晶體材料之層狀結構。同樣地,“磊晶生長”係用以表達單一晶體材料之層狀結構。磊晶生長材料可以是被摻雜的也可以是無摻雜的。
矽基電晶體之工作效能以及可擴展性已接近極限。例如,當元件尺度縮小以達到更高的封裝密度,使得縮小矽基電晶體變得更具挑戰性。FinFET元件可用來解決這些問題,因為其小外型封裝及效能之增進,例如驅動電流之增加以及臨界漏電流之縮減。
FinFET元件亦有其限制。例如,當使用多鰭的迴
路(例如,靜態隨機存取記憶體)尺寸縮小,相鄰鰭間的間隔也縮小。相鄰鰭間的間隔縮小會造成兩個問題:1)較小的保留空間可放置相鄰鰭間的源極/汲極接觸區,以及2)較小的保留空間可圖案化相鄰FinFET元件之閘極結構。關於第一個問題,雖然磊晶層可成長於鰭之源極/汲極區域使接觸區之著陸區域增大,相鄰鰭之源極/汲極區域之磊晶層增加了因磊晶層互相碰觸而產生電氣短路之風險。
關於第二個問題,圖案化閘極電極涉及沿著鰭的方向分隔閘極電極。分隔相鄰閘極電極的方法之一為利用乾蝕製程蝕刻閘極電極。當相鄰鰭間的鰭至鰭間隔縮小,蝕刻閘極電極而不蝕刻到鰭的保留空間也縮小,使得蝕刻製程變得困難。除此之外,閘極電極之蝕刻會造成閘極電極之損壞且對FinFET元件之功函數及臨界電壓偏移產生有害影響。另一個分離相鄰閘極電極的方法為,於沉積閘極電極前形成一分隔介電層。此方法可以消除蝕刻閘極電極之需求;然而,此方法亦有其挑戰性,因為閘介電質於分隔閘極側壁佔用了閘極電極的橫向空間。
本揭露描述了一種在緻密化且尺度縮減之元件上可執行圖案化及對準之方法與結構。於一些實施方式中,FinFET元件之源極/汲極區域之自對準磊晶製程可藉由含鍺氧化層執行。自對準磊晶層於源極/汲極區域之成長增加了FinFET元件在源極/汲極之著陸區域。於一些實施方式中,虛設鰭式結構被用來使相鄰鰭式場效電晶體元件之自對準磊晶層分隔。於一些實施方式中,於自對準蝕刻製程中對虛設鰭式
結構圖案化,以使相鄰鰭式場效電晶體之閘極電極分隔。利用自對準磊晶製程、虛設鰭式結構與自對準蝕刻製程以及自對準製程,可提供一些益處,例如,(i)提升製程整合;(ii)提升元件效能;以及(iii)提升尺寸調控之餘裕。
第一,自對準磊晶製程加上虛設鰭式結構除去了額外的對準製程之需求以及簡化了製程整合。例如,當形成磊晶層於p型FinFET元件以及n型FinFET元件之源極/汲極區域時,磊晶層係於個別之步驟中形成。個別的微影製程在形成不同的FinFET元件之磊晶層時是需要的。藉由利用含鍺氧化層,p型FinFET上形成的磊晶層可在接續的n型FinFET上之磊晶層成長之步驟中被保護。n型FinFET上之磊晶層成長之步驟可以自對準方式完成。因此,圖案化n型FinFET上之磊晶層時的微影與對準步驟可以被移除,且製程整合可被簡化。
第二,利用虛設鰭式結構加上自對準蝕刻製程分隔閘極電極消除了於閘極電極上執行蝕刻製程之需求。閘極電極可在不受到乾蝕刻的破壞下而被分隔,因此避免了因閘極電極損壞而造成之FinFET元件的功函數退化以及臨界電壓偏移。
第三,利用虛設鰭式結構可使閘極電極以及相鄰元件的源極/汲極皆以自對準方式被分隔,而不需執行額外的微影步驟。例如,虛設鰭式結構可避免形成於相鄰鰭上的磊晶層彼此接觸,而不須執行微影與對準步驟。再者,虛設鰭式結構加上自對準乾蝕刻製程可用來分隔閘極電極,而不需執行微影與對準步驟以圖案化閘極電極。
本揭露描述了自對準磊晶層以及虛設鰭式結構加上自對準蝕刻製程。第17圖為根據一些實施方式繪示一例示性方法1700的流程圖,其結合自對準磊晶製程以製造半導體結構。第1A圖至第16C圖為便於解釋方法1700所提供之剖面圖。
請參照第17圖,根據一些實施方式,方法1700始於操作步驟1702,於基材上形成複數個主動鰭式結構。第1A圖至第1C圖繪示了一些主動鰭式結構104形成於基材上。第1A圖為例示性結構之三維視圖。第1C圖為例示性結構之上視圖。第1B圖為第1A圖與第1C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
基材102可由矽製成,或由一些其他半導體元素,例如,鑽石或鍺;適合的半導體化合物,例如,碳化矽(SiC)、砷化銦(InAs)或是磷化銦(InP);或是適合的半導體合金,例如,矽鍺碳(SiGeC)、磷砷化鎵(GaAsP)或是磷化鎵銦(GaInP)。
於一些實施方式中,如第1B圖所示,主動鰭式結構104自基材102突出。於一些實施方式中,如第1A圖至第1C圖所示,主動鰭式結構104為互相平行並向一方向延伸。於一些實施方式中,主動鰭式結構104可以n型摻雜物摻雜,例如,磷(P)以及砷(As)或是以p型摻雜物摻雜,例如,硼(B)以及鎵(Ga)。於一些實施方式中,主動鰭式結構104可以一種摻雜物摻雜(例如,n型摻雜物),而其中一些主動鰭式結構104之上段106以另一種摻雜物摻雜(例如,p型摻雜物)。於一些實施方式中,以n型摻雜物摻雜之主動鰭式結構104係使用於n型
FinFETs(例如,NMOS元件)中,而上段106以p型摻雜物摻雜之主動鰭式結構104係使用於p型FinFETs(例如,PMOS元件)中。於一些實施方式中,主動鰭式結構104係由矽或其他合適材料所製成。於一些實施方式中,一些主動鰭式結構104之上段106係由不同於主動鰭式結構104之材料所製成,例如,鍺化矽。
於一些實施方式中,主動鰭式結構104係藉由圖案化硬遮罩層108以及非等向性蝕刻(例如,乾蝕刻)蝕刻至基材102而形成。於一些實施方式中,非等向性蝕刻係使用氟基和/或氯基化學物。硬遮罩層108所覆蓋面積於非等向性蝕刻過程中由硬遮罩層108所遮蔽,並使未被硬遮罩層108所覆蓋的面積凹陷而形成主動鰭式結構104。於一些實施方式中,硬遮罩層108係由氮所組成。於一些實施方式中,硬遮罩層108係藉由化學氣相沉積(chemical vapor deposition,CVD)製程、原子層沉積(atomic layer deposition,ALD)製程或是物理氣相沉積(physical vapor deposition,PVD)製程而形成。於一些實施方式中,額外之氧化物墊層110係置於硬遮罩層108與主動鰭式結構104間。於一些實施方式中,氧化物墊層110係由二氧化矽所製成。於一些實施方式中,氧化物墊層110以緩衝墊之作用減少來自硬遮罩層108對主動鰭式結構104以及基材102之壓力影響。
於一些實施方式中,主動鰭式結構104沿著線段B-B’方向之寬度介於約5奈米與約20奈米(例如,10奈米,或是介於5奈米與20奈米)。於一些實施方式中,主動鰭式結構
104自基材102之上表面量測起之高度介於約100奈米與約140奈米(例如,介於100奈米與140奈米)。於一些實施方式中,一些主動鰭式結構104之上段106之高度介於約50奈米與約60奈米(例如,介於50奈米與60奈米)。於一些實施方式中,無上段106之相鄰主動鰭式結構104間之距離(例如,第1B圖與第1C圖所繪示之距離)介於約25奈米與約55奈米(例如,介於25奈米與55奈米)。於一些實施方式中,具上段106之相鄰主動鰭式結構104間之距離(例如,第1B圖與第1C圖所繪示之距離)介於約25奈米與約55奈米(例如,介於25奈米與55奈米)。於一些實施方式中,無上段106之相鄰主動鰭式結構104與相鄰具上段106之相鄰主動鰭式結構104間之距離(例如,第1B圖與第1C圖所繪示之距離)介於約25奈米與約55奈米(例如,介於25奈米與55奈米)。於一些實施方式中,主動鰭式結構104以及一些主動鰭式結構104之上段106之寬度相同。於一些實施方式中,硬遮罩層108之高度介於約20奈米與約40奈米(例如,介於20奈米與40奈米)。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1704,形成第一介電層於主動鰭式結構上。第2A圖至第2C圖繪示了第一介電層112形成於主動鰭式結構104上。第2A圖為例示性結構之三維視圖。第2C圖為例示性結構之上視圖。第2B圖為第2A圖與第2C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,第一介電層112為氧化層。於一些實施方式中,第一介電層112係由原子層沉積製程沉積
而成。於一些實施方式中,原子層沉積製程係執行於介於約200℃與約400℃間之溫度(例如,介於200℃與400℃)。於一些實施方式中,第一介電層112係沉積(例如,均勻地沉積)於主動鰭式結構104、上段106、硬遮罩層108以及基材102之上。於一些實施方式中,第一介電層112之厚度介於約12奈米與約18奈米(例如,介於12奈米與18奈米)。於一些實施方式中,如第2A圖至第2C圖所繪示,沉積第一介電層112於主動鰭式結構104上之步驟於相鄰主動鰭式結構104間形成了一些凹槽114。於一些實施方式中,凹槽114之寬度介於約5奈米與約20奈米(例如,10奈米或介於5奈米與20奈米)。於一些實施方式中,凹槽114與主動鰭式結構104或是一些主動鰭式結構104之上段106之寬度相同。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1706,形成虛設鰭式結構於凹槽上。第3A圖至第3C圖繪示了一些虛設鰭式結構116形成於凹槽114上。第3A圖為例示性結構之三維視圖。第3C圖為例示性結構之上視圖。第3B圖為第3A圖與第3C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,形成虛設鰭式結構116之步驟包含以虛設鰭式材料填充於凹槽114。於一些實施方式中,填充凹槽114之步驟係藉由原子層沉積製程或是化學氣相沉積製程執行。於一些實施方式中,藉由原子層沉積製程填充虛設鰭式材料於凹槽114之步驟係執行於介於約400℃與約600℃間之溫度(例如,介於400℃與600℃)。於一些實施方式中,虛
設鰭式材料包含氮碳化矽(SiCN)、氮碳氧化矽(SiOCN)、二氧化鉿(HfO2)、二氧化鋯(ZrO2)以及三氧化二鋁(Al2O3)。於一些實施方式中,形成虛設鰭式結構116之步驟進一步包含執行平坦化步驟(例如,化學機械研磨(chemical mechanical polish,CMP)步驟)以移除第一介電層112之頂表面上多餘的虛設鰭式材料,使得第一介電層112之頂表面、硬遮罩層108之頂表面以及虛設鰭式結構116之頂表面共平面。於一些實施方式中,當虛設鰭式結構116填充於凹槽114時,虛設鰭式結構116之寬度與凹槽114之寬度相同。於一些實施方式中,虛設鰭式結構116之寬度介於約5奈米與約20奈米(例如,10奈米或介於5奈米與20奈米)。於一些實施方式中,虛設鰭式結構116之寬度與主動鰭式結構104或是一些主動鰭式結構104之上段106之寬度相同。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1708,使第一介電層凹陷。第4A圖至第4C圖繪示了凹陷至低於主動鰭式結構104之頂表面之第一介電層112。第4A圖為一例示性結構之三維視圖。第4C圖為一例示性結構之上視圖。第4B圖為第4A圖與第4C圖所繪示之一例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,使第一介電層112凹陷之步驟係利用藉由氣相化學物蝕刻氧化物之化學蝕刻製程。於一些實施方式中,化學蝕刻製程為一計時之蝕刻製程。於一些實施方式中,使第一介電層112凹陷之步驟進一步包含移除硬遮罩層108。於一些實施方式中,移除硬遮罩層108之步驟包含以
磷酸(H3PO4)執行濕化學製程以蝕刻氮。於一些實施方式中,使第一介電層112凹陷之步驟進一步包含移除氧化物墊層110。
於一些實施方式中,使第一介電層112凹陷,而使第一介電層112之頂表面低於主動鰭式結構104之頂表面。於一些實施方式中,自第一介電層112之頂表面量測至主動鰭式結構104之頂表面之主動鰭式結構104之高度介於約50奈米與約60奈米(例如,介於50奈米與60奈米)。於一些實施方式中,虛設鰭式結構116之底表面低於第一介電層112之頂表面,因此第一介電層112使虛設鰭式結構116穩定而不倒塌。於一些實施方式中,因主動鰭式結構104上之硬遮罩層108虛之移除,使得虛設鰭式結構116之高度大於主動鰭式結構104。於一些實施方式中,自第一介電層112之頂表面量測至虛設鰭式結構116之頂表面之虛設鰭式結構116之高度介於約70奈米與約100奈米(例如,介於70奈米與100奈米)。於一些實施方式中,如第4B圖所繪示,一些主動鰭式結構104之上段106具有與第一介電層112之頂表面共平面之底表面,因此上段106係曝露自第一介電層112。
請參照第17圖,方法1700進行至操作步驟1710,根據一些實施方式,形成閘極氧化層於主動鰭式結構上。第5A圖至第5C圖繪示了閘極氧化層118形成於主動鰭式結構104上、一些主動鰭式結構104之上段106上、虛設鰭式結構116上以及第一介電層112上。第5A圖為例示性結構之三維視圖。第5C圖為例示性結構之上視圖。第5B圖為第5A圖與第
5C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,形成閘極氧化層118之步驟係藉由原子層沉積製程或化學氣相沉積製程執行。於一些實施方式中,藉由原子層沉積製程形成閘極氧化層118之步驟係執行於介於約200℃與約400℃間之溫度(例如,介於200℃與400℃)。於一些實施方式中,閘極氧化層118包含矽氧化物(SiOx)或其他合適材料。於一些實施方式中,閘極氧化層118之厚度介於約2奈米與約4奈米(例如,介於2奈米與4奈米)。於一些實施方式中,閘極氧化層118係用於高電壓元件之閘介電質。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1712,形成虛設閘極結構121。第6A圖至第6C圖繪示了一些虛設閘極結構121形成於閘極氧化層118上、主動鰭式結構104上、一些主動鰭式結構104之上段106上、虛設鰭式結構116上以及第一介電層112上。第6A圖為例示性結構之三維視圖。第6C圖為例示性結構之上視圖。第6B圖為第6A圖與第6C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,如第6C圖所繪示,虛設閘極結構121係平行且沿著不同於主動鰭式結構104方向之一方向延伸形成。於一些實施方式中,虛設閘極結構121包含多晶矽閘極電極120。於一些實施方式中,虛設閘極結構121進一步包含氧化物硬遮罩124以及氮硬遮罩122。於一些實施方式中,多晶矽閘極電極120係由多晶矽組成,氧化物硬遮罩124係由矽氧化物所組成,而氮硬遮罩122係由矽氮化物(SiNx)或
是SiCN所組成。於一些實施方式中,如第6A圖與第6B圖所繪示,虛設閘極結構121係形成於主動鰭式結構104、一些主動鰭式結構104之上段106、以及虛設鰭式結構116之頂表面以及側表面上。於一些實施方式中,多晶矽閘極電極120之高度介於約100奈米與約150奈米(例如,介於100奈米與150奈米)。多晶矽閘極電極120之寬度介於約12奈米與約16奈米(例如,介於12奈米與16奈米)。於一些實施方式中,氧化物硬遮罩124之厚度介於約40奈米與約80奈米(例如,介於40奈米與80奈米),且氮硬遮罩122之厚度介於約10奈米與約30奈米(例如,介於10奈米與30奈米),於一些實施方式中,形成虛設閘極結構121之步驟包含沉積一層疊之虛設閘極材料,其中包含一閘極電極層、一氮硬遮罩層以及一氧化物硬遮罩層,利用微影技術微影圖案化層疊之虛設閘極材料,以及蝕刻層疊之虛設閘極材料以形成多晶矽閘極電極120、氮硬遮罩122以及氧化物硬遮罩124。於一些實施方式中,蝕刻層疊之虛設閘極材料之步驟停止於閘極氧化層118之表面。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1714,形成間隔物於虛設閘極結構以及使虛設鰭式結構未被虛設閘極結構以及間隔物覆蓋之面積凹陷。第7A圖至第7C圖繪示了間隔物126形成於虛設閘極結構121之側表面上。第7A圖至第7C圖亦繪示了虛設鰭式結構116於未被虛設閘極結構121或是間隔物126覆蓋之面積處凹陷。第7A圖為例示性結構之三維視圖。第7C圖為例示性結構之上視圖。第7B圖為第7A圖與第7C圖所繪示之例示性結構中沿著線
段B-B’之剖面圖。
於一些實施方式中,間隔物126為介電常數小於4.0之低介電間隔物。於一些實施方式中,間隔物126包含元素,例如,Si、O、C。於一些實施方式中,間隔物126之厚度介於約6奈米與約8奈米(例如,介於6奈米與8奈米)。於一些實施方式中,形成間隔物126之步驟包含,均勻地沉積間隔物126,接著使用非等相性蝕刻(例如,乾蝕)製程收縮間隔物126。於一些實施方式中,收縮間隔物126之步驟包含蝕刻以及移除形成於虛設閘極結構121之頂表面、主動鰭式結構104之頂表面、一些主動鰭式結構104之上段106、虛設鰭式結構116、第一介電層112之頂表面以及主動鰭式結構104、一些主動鰭式結構104之上段106以及虛設鰭式結構116之側表面上之間隔物126。於一些實施方式中,收縮間隔物126也包含蝕刻間隔物126形成於虛設閘極結構121之側表面之一部分。
於一些實施方式中,使虛設鰭式結構116凹陷之步驟係藉由非等向性乾蝕製程執行。於一些實施方式中,乾蝕製程蝕刻虛設鰭式材料之速率(例如,金屬氧化物、SiON以及SiOCN)遠大於蝕刻主動鰭式結構104材料(例如,Si以及SiGe)之速率。歸因於此蝕刻選擇性,乾蝕製程使虛設鰭式結構116垂直凹陷而不使主動鰭式結構104或是一些主動鰭式結構104之上段106凹陷。於一些實施方式中,如第7A圖與第7C圖所繪示,虛設鰭式結構116凹陷使得虛設鰭式結構116之頂表面、主動鰭式結構104之頂表面以及一些主動鰭式結構104之上段106之頂表面共平面(例如,與第7C圖中之線段B-B’對
齊)。
於一些實施方式中,乾蝕製程亦移除形成於主動鰭式結構104、一些主動鰭式結構104之上段106以及虛設鰭式結構116之頂表面以及側表面上之閘極氧化層118。於一些實施方式中,移除形成於主動鰭式結構104、一些主動鰭式結構104之上段106之頂表面以及側表面之閘極氧化層118之步驟,使得磊晶層可於接續的製程中成長於主動鰭式結構104以及上段106。於一些實施方式中,乾蝕刻製程進一步移除形成於第一介電層112之頂表面之閘極氧化層118。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1716,圖案化p型FinFET元件之源極/汲極區域。第8A圖至第8C圖繪示了光阻層128之形成與圖案化。第8A圖至第8C圖亦繪示了光阻層128覆蓋了無上段106之主動鰭式結構104,而具有上段106之主動鰭式結構104則被曝露。第8A圖為例示性結構之三維視圖。第8C圖為例示性結構之上視圖。第8B圖為第8A圖與第8C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,如操作步驟1702中所述,一些主動鰭式結構104之上段106係以p型摻雜物摻雜並使用於p型FinFET元件中。而其他無上段106之主動鰭式結構104係以n型摻雜物摻雜並使用於n型FinFET元件中。於一些實施方式中,主動鰭式結構104、一些主動鰭式結構104之上段106未被虛設閘極結構121或是間隔物126覆蓋之面積為FinFET元件之源極/汲極區域。於一些實施方式中,圖案化p型FinFET元
件之源極/汲極區域包含沉積氧化鋁(AlOx)層130於元件結構上,接著塗佈光阻層128於氧化鋁層130上。於一些實施方式中,光阻層128為正型光阻劑,其厚度介於約200奈米與約400奈米(例如,介於200奈米與400奈米)。位於以p型摻雜物摻雜且具有上段106之主動鰭式結構104之面積上的部分光阻層128係以微影製程移除。而位於此部分光阻層128下方之具有上段106之主動鰭式結構104之面積上的部分氧化鋁層130亦被曝露。接著,執行蝕刻製程以移除此部分氧化鋁層130,並使上段106之頂表面以及側表面被曝露。於一些實施方式中,移除此部分氧化鋁層130之蝕刻製程包含一濕蝕製程、乾蝕製程或是上述製程之結合。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1718,成長磊晶層於p型FinFET元件之源極/汲極區域上。第9A圖至第9C圖繪示了磊晶層132形成於操作步驟1716中被曝露之上段106上(例如,p型FinFET元件之源極/汲極區域)。第9A圖至第9C圖亦繪示了光阻層128被移除且氧化鋁層130覆蓋了n型FinFET元件之主動鰭式結構104。第9A圖為例示性結構之三維視圖。第9C圖為例示性結構之上視圖。第9B圖為第9A圖與第9C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,光阻層128於成長磊晶層132前先以光阻去除製程移除(例如,濕化學蝕刻製程)。因此,如第9A圖與第9B圖所繪示,位於光阻層128下方之氧化鋁層130被曝露。於一些實施方式中,氧化鋁層130之目的為於接續之
磊晶製程中保護n型FinFET元件之主動鰭式結構104之表面。
於一些實施方式中,成長磊晶層132於p型FinFET元件之源極/汲極區域上之步驟包含,執行預清洗製程以移除位於一些主動鰭式結構104之上段106之表面的原生氧化物,並且使上段106之表面被曝露。接著,執行一磊晶製程以成長磊晶層132於一些主動鰭式結構104之上段106之表面。於一些實施方式中,磊晶製程為SiGe磊晶製程,執行於介於約400℃與約500℃間之溫度(例如,介於400℃與500℃)。磊晶製程為選擇性製程,僅成長磊晶層132於上段106被曝露之表面(例如,p型FinFET元件之源極/汲極區域)。於一些實施方式中,磊晶層132為鍺化矽層,其鍺濃度介於約40%與約60%(例如,介於40%與60%)。於一些實施方式中,磊晶層132之厚度介於約10奈米與約20奈米(例如,介於10奈米與20奈米)。於一些實施方式中,磊晶層132之形狀為菱形。磊晶層132可依據不同因素而有不同形狀,例如,磊晶製程條件、一些主動鰭式結構104之上段106之結晶方向以及一些主動鰭式結構104之上段106之材料。於一些實施方式中,磊晶層132於磊晶製程中係以B摻雜。於一些實施方式中,磊晶層132厚得足以與虛設鰭式結構116之側表面接觸。於一些實施方式中,虛設鰭式結構116係以自對準隔離層之作用避免形成於相鄰上段106之磊晶層132互相接觸。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1720,成長含鍺氧化層134於p型FinFET元件上之磊晶層132上。第10A圖至第10C圖繪示了含鍺氧化層134
形成於磊晶層132上,其中磊晶層132形成於p型FinFET元件之源極/汲極區域上。第10A圖至第10C圖亦繪示了覆蓋了n型FinFET元件之主動鰭式結構104之氧化鋁層130被移除。第10A圖為例示性結構之三維視圖。第10C圖為例示性結構之上視圖。第10B圖為第10A圖與第10C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,成長含鍺氧化層134於磊晶層132上之步驟係藉由氧化化學物之常溫製程執行。於一些實施方式中,常溫製程使用臭氧(O3)、硫酸(H2SO4)與過氧化氫(H2O2)之混合物或是氫氧化銨(NH4OH)與H2O2之混合物。於一些實施方式中,成長含鍺氧化層134於磊晶層132上之步驟係藉由低溫濕蒸氣爐退火執行。於一些實施方式中,低溫濕蒸氣爐退火係執行於介於約300℃與約400℃間之溫度(例如,介於300℃與400℃)。使用低溫濕蒸氣爐退火之一優點為低溫濕蒸氣爐退火相較於常溫製程可成長較厚之含鍺氧化層134。
於一些實施方式中,含鍺氧化層134為矽鍺氧化物(SiGeOx)層。於一些實施方式中,含鍺氧化層134之鍺濃度介於約40%與約70%(例如,介於40%與70%)。於一些實施方式中,含鍺氧化層134之厚度介於約1奈米與約3奈米(例如,介於1奈米與3奈米)。於一些實施方式中,含鍺氧化層134完整覆蓋磊晶層132之表面。於一些實施方式中,含鍺氧化層134與虛設鰭式結構116之側表面接觸。於一些實施方式中,含鍺氧化層134於接續之磊晶製程中,以作為磊晶層132的保護層之作用使磊晶層132上無額外磊晶層成長。含鍺氧化層134抵抗
接續磊晶製程中之預清洗製程,並於預清洗製程後維持在磊晶層132上。於一些實施方式中,預清洗製程包含利用含氫以及含氟化學物之遠距電漿蝕刻製程,例如氫(H2)、氨(NH3)以及三氟化氮(NF3)。於一些實施方式中,含鍺氧化層134中之高鍺濃度(例如,介於約40%與約70%)使含鍺氧化層134於接續磊晶製程中之預清洗製程有抵抗能力。
於一些實施方式中,覆蓋了n型FinFET元件之主動鰭式結構104之氧化鋁層130於含鍺氧化層134成長於磊晶層132上後被移除。於一些實施方式中,氧化鋁層130被移除以曝露n型FinFET元件之主動鰭式結構104之表面,使自對準磊晶層136於接續磊晶製程中成長於n型FinFET元件之主動鰭式結構104上。於一些實施方式中,移除氧化鋁層130之製程包含濕蝕刻製程、乾蝕刻製程或是上述製程之結合。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1722,成長自對準磊晶層於n型FinFET元件之源極/汲極區域上。第11A圖至第11C圖繪示了自對準磊晶層136形成於n型FinFET元件之源極/汲極區域上(例如,n型FinFET元件之主動鰭式結構104未被虛設閘極結構121或間隔物126所覆蓋之表面)。第11A圖為例示性結構之三維視圖。第11C圖為例示性結構之上視圖。第11B圖為第11A圖與第11C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,成長自對準磊晶層136於n型FinFET元件之源極/汲極區域上之步驟包含,執行預清洗製程以移除n型FinFET元件之主動鰭式結構104表面之原生氧化
物,並曝露主動鰭式結構104之表面。於一些實施方式中,預清洗製程包含利用含氫以及含氟化學物之遠距電漿蝕刻製程,例如氫、氨以及三氟化氮。於一些實施方式中,含鍺氧化層134抵抗接續磊晶製程中之預清洗製程,並於預清洗製程後維持在p型FinFET元件之源極/汲極區域上之磊晶層132上。接著,執行自對準磊晶製程以成長自對準磊晶層136於主動鰭式結構104之表面,而不使磊晶層132上成長額外之磊晶層。
於一些實施方式中,預清洗製程後,p型FinFET元件之源極/汲極區域上含鍺氧化層134之存在,使得自對準磊晶製程可以自對準方式執行。尤其,因含鍺氧化層134抵抗自對準磊晶製程的預清洗製程,含鍺氧化層134以作為磊晶層132之保護層之作用使自對準磊晶製程中之磊晶層132上無額外磊晶層成長。因此,無須再執行額外的微影或圖案化步驟形成另一保護層(例如,額外的氧化鋁層130)以於n型FinFET元件之磊晶製程中保護磊晶層132。含鍺氧化層134之使用簡化了製程整合且無需額外之圖案化步驟即可使自對準磊晶層136成長。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1724,形成第二介電層。第12A圖至第12C圖繪示了第二介電層138形成於虛設閘極結構121間(例如,多晶矽閘極電極120)以及第一介電層112之上表面。第12A圖至第12C圖亦繪示了接觸蝕刻停止層(contact etch stop layer,CESL)140形成於n型FinFET元件之自對準磊晶層136以及p型FinFET元件之磊晶層132上之含鍺氧化層134上。進一步來
說,第12A圖至第12C圖繪示了虛設閘極結構121之氧化物硬遮罩124以及氮硬遮罩122被移除,且第二介電層138與多晶矽閘極電極120之上表面共平面。第12A圖為例示性結構之三維視圖。第12C圖為例示性結構之上視圖。第12B圖為第12A圖與第12C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,第二介電層138為氧化物(例如,SiOx)層。於一些實施方式中,第二介電層138係藉由化學氣相沉積製程、原子層沉積製程或是自旋塗佈而執行。於一些實施方式中,額外的退火製程係執行於介於約400℃與約600℃間之溫度(例如,介於400℃與600℃),用於處理第二介電層138以密化沉積後之介電層。於一些實施方式中,一平坦化製程(例如,化學機械研磨)於沉積第二介電層138後執行,以移除部分之形成於虛設閘極結構121之頂表面之第二介電層138,並平坦化第二介電層138之頂表面,使得第二介電層138、間隔物126以及多晶矽閘極電極120之頂表面共平面。於一些實施方式中,氧化物硬遮罩124以及氮硬遮罩122亦於平坦化製程或額外之蝕刻製程中移除,以曝露多晶矽閘極電極120之頂表面。於一些實施方式中,平坦化製程後之多晶矽閘極電極120之高度介於約80奈米與約130奈米(例如,介於80奈米與130奈米)。
於一些實施方式中,接觸蝕刻停止層140係沉積於第二介電層138之沉積步驟前。於一些實施方式中,沉積接觸蝕刻停止層140以保護自對準磊晶層136以及磊晶層132,於接續的第二介電層138之沉積及退火製程中對抗濕氣、摻雜物
以及/或氧化。於一些實施方式中,接觸蝕刻停止層140以蝕刻停止層之作用使接觸蝕刻停止,使得位於接觸蝕刻停止層140下方之磊晶層136與132不受接觸蝕刻之破壞。於一些實施方式中,接觸蝕刻停止層140為矽氮化物層。於一些實施方式中,接觸蝕刻停止層140之沉積係藉由原子層沉積製程或化學氣相沉積製程而執行。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1726,執行自對準蝕刻以使虛設閘極結構與虛設鰭式結構凹陷。第13A圖至第13C圖繪示了具有開口144之光阻層142形成於第二介電層138以及多晶矽閘極電極120上。第13C圖亦繪示了經由開口144對多晶矽閘極電極120以及虛設鰭式結構116執行自對準蝕刻。第13A圖為例示性結構之三維視圖。第13C圖為例示性結構之上視圖。第13B圖為第13A圖與第13C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,於執行自對準蝕刻前,光阻層142係塗佈於第二介電層138以及多晶矽閘極電極120之頂表面上。接著,圖案化光阻層142以形成開口144,並定義於接續自對準蝕刻中被凹陷之面積。於一些實施方式中,光阻層142為正型光阻。於一些實施方式中,光阻層142之厚度介於約50奈米與約100奈米(例如,介於50奈米與100奈米)。
於一些實施方式中,自對準蝕刻為非等向性蝕刻(例如,乾蝕刻)製程。於一些實施方式中,自對準蝕刻製程蝕刻多晶矽閘極電極120以及位於多晶矽閘極電極120下方且曝露於開口144之虛設鰭式結構116。於一些實施方式中,如第
13C圖所繪示,開口144於線段B-B’方向之寬度大於虛設鰭式結構116。於一些實施方式中,自對準蝕刻對於多晶矽閘極電極120以及虛設鰭式結構116之蝕刻速率大於(例如,大於十倍)對於間隔物126以及第二介電層138之蝕刻速率。由於蝕刻速率之不同,蝕刻製程使開口144下方之多晶矽閘極電極120以及虛設鰭式結構116凹陷,而使間隔物126以及第二介電層138最小量凹陷。蝕刻製程係朝向目標材料,即便其他材料亦曝露於微影圖案。因此,不需精確地對齊微影圖案邊界與下方結構,因而提供微影製程中的對齊與重疊需求更大的空間。換句話說,此蝕刻為自對準蝕刻。
於一些實施方式中,多晶矽閘極電極120下方之虛設鰭式結構116凹陷深度為d。深度d可介於約20奈米與約40奈米(例如,介於20奈米與40奈米)。於一些實施方式中,虛設鰭式結構116凹陷深度d大於約40奈米。於一些實施方式中,虛設鰭式結構116凹陷深度d小於約20奈米。明確的虛設鰭式結構116凹陷深度係根據實際元件設計。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1728,移除虛設閘極結構。第14A圖至第14C圖繪示了虛設閘極結構121(例如,多晶矽閘極電極120)之移除。第14A圖為例示性結構之三維視圖。第14C圖為例示性結構之上視圖。第14B圖為第14A圖與第14C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,移除虛設閘極結構121之步驟係利用乾蝕刻、濕蝕刻或是上述製程之結合而執行。於一些
實施方式中,如第14A圖所繪示,虛設閘極結構121之移除形成了開口146。於一些實施方式中,用於虛設閘極結構121之製程為選擇性製程,且第二介電層138以及間隔物126於閘極結構被移除後保留。於一些實施方式中,移除虛設閘極結構121之步驟包含移除閘極氧化層118,因此可於形成金屬閘極結構至開口146時形成新閘極介電層150。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1730,形成金屬閘極結構。第15A圖至第15C圖繪示了具有金屬閘極電極148之金屬閘極結構形成於開口146。第15A圖至第15C圖亦繪示了閘極介電層150形成於金屬閘極電極148之形成之前。第15A圖為例示性結構之三維視圖。第15C圖為例示性結構之上視圖。第15B圖為第15A圖與第15C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,形成金屬閘極結構之步驟包含於形成金屬閘極電極148之前形成閘極介電層150至開口146。於一些實施方式中,閘極介電層150包含介面層以及高介電常數之介電層。於一些實施方式中,介面層為矽氧化物層。於一些實施方式中,高介電常數之介電層包含高介電常數材料,例如,二氧化鉿、氧化鑭(La2O3)、三氧化二鋁、二氧化鋯、氮化矽以及其他合適之高介電常數材料。於一些實施方式中,高介電常數層之介電常數大於約3.9。於一些實施方式中,高介電常數層之介電常數大於約7.0。於一些實施方式中,閘極介電層150之形成係藉由原子層沉積製程或是化學氣相沉積製程執行。
於一些實施方式中,金屬閘極電極148包含金屬導體,例如,鎢(W)。於一些實施方式中,金屬閘極電極148亦包含擴散阻隔層,例如,氮化鈦(TiN)以及鈦矽氮化物(TiSiN)。於一些實施方式中,金屬閘極電極148進一步包含功函數層,例如,n型FinFET元件中之TiN與鈦鋁合金(TiAl)以及p型FinFET元件中之TaN與鈦鋁合金(TiAl)。於一些實施方式中,形成金屬閘極電極148之步驟係藉由原子層沉積或是化學氣相沉積執行。
於一些實施方式中,於形成金屬閘極結構至開口146後,執行平坦化製程(例如,化學機械研磨製程)以移除形成於第二介電層138頂表面之金屬閘極結構。於一些實施方式中,平坦化製程進一步移除部分之第二介電層138,使得第二介電層138、金屬閘極電極148以及閘極介電層150之頂表面共平面。於一些實施方式中,金屬閘極電極148之頂表面進一步與未被操作步驟1726中自對準蝕刻製程蝕刻之虛設鰭式結構116之頂表面共平面。如同操作步驟1726中所述,曝露於開口144之虛設鰭式結構116(第15C圖中以點方格強調)被凹陷,而未暴露於開口144之虛設鰭式結構116未凹陷因而高於凹陷之虛設鰭式結構116。因此,於未被自對準蝕刻凹陷之虛設鰭式結構116之位置上,金屬閘極電極148被虛設鰭式結構116分離。相反地,被自對準蝕刻凹陷之虛設鰭式結構116之位置上,虛設鰭式結構116之長度短且金屬閘極電極148維持連續並相連。
因此,利用於自對準蝕刻製程中凹陷之虛設鰭式
結構116,金屬閘極結構可以自對準方式圖案化而不需執行額外的微影以及圖案化製程。此類金屬閘極結構之自對準圖案化不僅減緩了對齊與重疊之需求,也藉由避免利用非等向性蝕刻(例如,乾蝕刻)切割金屬閘極而防止蝕刻對金屬閘極結構之破壞。進一步來說,避免蝕刻對金屬閘極結構之破壞,可防止因金屬閘極結構之損壞而造成的功函數破壞與臨界電流偏移,並增進FinFET元件效能。
請參照第17圖,根據一些實施方式,方法1700進行至操作步驟1732,形成源極/汲極接觸區。第16A圖至第16C圖繪示了源極/汲極接觸區152形成於n型FinFET元件之主動鰭式結構104上以及p型FinFET元件之上段106上。第16A圖與第16B圖亦繪示了矽化物層154形成於源極/汲極接觸區152以及磊晶層136與132間。第16C圖為例示性結構之上視圖。第16B圖為第16A圖與第16C圖所繪示之例示性結構中沿著線段B-B’之剖面圖。
於一些實施方式中,源極/汲極接觸區152由金屬所組成,例如,鈷(Co)、鎢、銅(Cu)、鎳(Ni)、釕(Ru)或是其他合適材料。於一些實施方式中,源極/汲極接觸區152進一步包含阻隔層以避免材料自源極/汲極接觸區152擴散至第二介電層138,反之亦然。於一些實施方式中,形成源極/汲極接觸區152之步驟係藉由原子層沉積製程、化學氣相沉積製程、物理氣相沉積製程或是上述製程之結合。於一些實施方式中,形成源極/汲極接觸區152之步驟進一步包含平坦化製程(例如,化學機械研磨製程)以移除形成於第二介電層138之頂表面或
是金屬閘極結構之餅表面之源極/汲極接觸區152。於一些實施方式中,於平坦化製程後,源極/汲極接觸區152之頂表面、第二介電層138之頂表面以及金屬閘極電極148之頂表面共平面。
於一些實施方式中,形成源極/汲極接觸區152之步驟進一步包含形成矽化物層154於源極/汲極接觸區152以及磊晶層136與132間。於一些實施方式中,形成矽化物層154之步驟包含移除覆蓋於及磊晶層136與132之頂表面之接觸蝕刻停止層140。於一些實施方式中,如第16B圖所繪示,於移除接觸蝕刻停止層140後,執行額外蝕刻製程以使磊晶層136與132之頂表面凹陷,以形成一平坦表面於源極/汲極接觸區152上。於一些實施方式中,於一些實施方式中,使磊晶層136與132凹陷增加了源極/汲極接觸區152與磊晶層間之接觸面積,並減少了接觸電阻。於一些實施方式中,矽化物層154之形成係藉由矽化製程執行,包含沉積金屬層,使金屬與磊晶層、主動鰭式結構104或是一些主動鰭式結構104之上段106反應,並移除未反應之金屬層。於一些實施方式中,矽化物層154包含鈷矽化物(CoSix)或是鎳矽化物(NiSix)。
自對準磊晶製程可藉由使用磊晶層上之含鍺氧化層而實現。成長於源極/汲極接觸區上之自對準磊晶層增加了FinFET元件之源極/汲極著陸區域。虛設鰭式結構之使用使得磊晶層可以自對準方式被分隔開。自對準蝕刻製程應用於使虛設鰭式結構於圖案所定義之面積處凹陷,使得金屬閘極結構可以自對準方式被分隔開。金屬閘極結構之自對準分隔也防止或
是最小化了金屬閘極結構之破壞以及增進元件效能。利用含鍺氧化層、自對準磊晶製程、虛設鰭式結構以及自對準蝕刻製程圖案化虛設鰭式結構以分隔金屬閘極,可獲得許多益處,例如(i)提升製程整合;(ii)提升元件效能以及(iii)提升尺寸調控幅度。
於一些實施方式中,FinFET元件包含基材。其結構進一步包含第一鰭式結構,自基材突出且摻雜有n型摻雜物。其結構進一步包含第二鰭式結構,自基材突出且上段摻雜有p型摻雜物。其結構進一步包含第一磊晶層,成長於第一鰭式結構之源極/汲極區域上,以及第二磊晶層成長於第二鰭式結構之源極/汲極區域上。其結構進一步包含第三鰭式結構,平行於第一鰭式結構與第二鰭式結構而形成,且形成於第一鰭式結構與第二鰭式結構之間以及第一磊晶層與第二磊晶層之間。第三鰭式結構係以不同於第一鰭式結構以及第二鰭式結構之材料所形成。其結構進一步包含形成於第二磊晶層上之含鍺氧化層。
於一些實施方式中,形成FinFET元件結構之方法包含形成複數個突出於基材之第一鰭式結構。此方法進一步包含,摻雜n型摻雜物於第一鰭式結構之第一部位,以及摻雜p型摻雜物於第一鰭式結構之第二部位。此方法進一步包含,形成複數個第二鰭式結構於每一第一鰭式結構之間。此方法進一步包含,成長鍺化矽磊晶層於第一鰭式結構之第二部位之源極/汲極區域上。此方法進一步包含,形成含鍺氧化層於鍺化矽磊晶層上以於接續之磊晶步驟中保護鍺化矽磊晶層之表面。此
方法進一步包含,成長矽磊晶層於第一鰭式結構之第一部位之源極/汲極區域上。
於一些實施方式中,半導體結構包含基材。此半導體結構進一步包含複數個第一鰭式結構,摻雜有n型摻雜物且突出於基材。此半導體結構進一步包含複數個第二鰭式結構,突出於基材且平行於第一鰭式結構,其中第二鰭式結構具有摻雜有p型摻雜物之上段。此半導體結構進一步包含第一介電層,形成於基材上以及第一鰭式結構以及第二鰭式結構中之每一者之側表面上。第一介電層之頂表面低於第一鰭式結構以及第二鰭式結構之頂表面。此半導體結構進一步包含複數個虛設鰭式結構,平行於第一鰭式結構以及第二鰭式結構。虛設鰭式結構中之至少一者係形成於每一第一鰭式結構以及每一第二鰭式結構之間,其中複數個虛設鰭式結構之底表面低於介電質之頂表面。此半導體結構進一步包含鍺化矽磊晶層,形成於第二鰭式結構上。此半導體結構進一步包含含鍺氧化層,形成於鍺化矽磊晶層上,以於接續之磊晶步驟中保護鍺化矽磊晶層。此半導體結構進一步包含矽磊晶層,形成於第一鰭式結構上。
應當被認可的是實施方式段落,其用意為闡述申請專利發明範圍。發明內容與摘要段落,依照發明人所想之揭露,可放置一或更多但非完整之例示性實施方式,因此其非用於限制本揭露以及申請專利範圍可延伸之範圍。
雖然本揭露已以實施方式揭露如上,然其並不用以限定本揭露,任何熟習此技藝者,在不脫離本揭露的精神和
範圍內,當可作各種的更動與潤飾,因此本揭露的保護範圍當視後附的申請專利範圍所界定者為準。
Claims (10)
- 一種半導體結構,包含:一基材;一第一鰭式結構,自該基材突出且摻雜有n型摻雜物;一第二鰭式結構,自該基材突出,其中該第二鰭式結構之一上段係摻雜有p型摻雜物;一第一磊晶層,形成於該第一鰭式結構之一源極/汲極區域上;一第二磊晶層,形成於該第二鰭式結構之一源極/汲極區域上;一第三鰭式結構,形成於該第一鰭式結構與該第二鰭式結構之間以及該第一磊晶層與該第二磊晶層之間,其中該第三鰭式結構係以不同於該第一鰭式結構以及該第二鰭式結構之材料所形成;以及一含鍺(Ge)氧化層,形成於該第二磊晶層上。
- 如請求項第1項所述之半導體結構,進一步包含一介電層,該介電層形成於該基材上並設置於該第一鰭式結構與該第二鰭式結構之間,其中該介電層之一頂表面係位於該第一鰭式結構以及該第二鰭式結構中之每一者之一頂表面之下。
- 如請求項第1項所述之半導體結構,其中自該第三鰭式結構至該第一鰭式結構以及該第二鰭式結構中之每一者之一距離,係大於該第一鰭式結構以及該第二鰭式結構中之每一者之一寬度。
- 一種半導體結構之形成方法,包含:形成複數個第一鰭式結構突出於一基材;摻雜n型摻雜物於該些第一鰭式結構之一第一部位;摻雜p型摻雜物於該些第一鰭式結構之一第二部位;形成至少一第二鰭式結構於每一該些第一鰭式結構之間;成長一鍺化矽(silicon germanium,SiGe)磊晶層於該些第一鰭式結構之該第二部位之源極/汲極區域上;形成一含鍺(Ge)氧化層於該鍺化矽磊晶層上;以及成長一矽(Si)磊晶層於該些第一鰭式結構之該第一部位之源極/汲極區域上。
- 如請求項第4項所述之半導體結構之形成方法,其中該成長該矽磊晶層之步驟包含:曝露該些第一鰭式結構之該第一部位之該些源極/汲極區域以及該鍺化矽磊晶層上之含鍺氧化層;執行一清洗製程以去除形成於該些第一鰭式結構之該第一部位之該些源極/汲極區域上之一原生氧化物,其中該鍺化矽磊晶層於該清洗製程之後保留;以及成長該矽磊晶層於該些第一鰭式結構之該第一部位之該些源極/汲極區域上,而不成長該矽磊晶層於該鍺化矽磊晶層上。
- 如請求項第4項所述之半導體結構之形成方法,進一步包含:形成包含一多晶矽閘極電極之複數個多晶矽閘極結構,其中該些多晶矽閘極結構係形成於該些第一鰭式結構以及該至少一第二鰭式結構之一頂表面以及一側表面上方;形成一第一介電層於該些多晶矽閘極結構之側表面上;形成一第二介電層於該些多晶矽閘極結構之該些側表面之間以及該第一介電層上;形成一圖案於該些多晶矽閘極結構以及該第二介電層上方;以及蝕刻該些多晶矽閘極結構之一部位以及該至少一第二鰭式結構之一部位,其中該蝕刻之步驟係執行於由該圖案所定義之一開放面積;其中蝕刻該些多晶矽閘極結構之該部位以及該至少一第二鰭式結構之該部位之一蝕刻速率,係大於蝕刻該第二介電層之一蝕刻速率。
- 如請求項第6項所述之半導體結構之形成方法,進一步包含:移除該些多晶矽閘極結構之該多晶矽閘極電極;沉積複數個金屬閘極結構於該第二介電層之側表面之間;以及執行一第一平坦化製程使該些金屬閘極結構之一頂表面與該至少一第二鰭式結構之該頂表面共平面;其中該些金屬閘極結構係由該第二鰭式結構所分隔。
- 如請求項第4項所述之半導體結構之形成方法,其中該形成該至少一第二鰭式結構包含:藉由沉積一第一介電層於該些第一鰭式結構之一頂表面以及一側表面上方而形成至少一凹槽;以一第二介電層填充該至少一凹槽;以及平坦化該第二介電層之一頂表面至與該第一介電層之一頂表面共平面。
- 一種半導體結構,包含:一基材;複數個第一鰭式結構,摻雜有n型摻雜物且突出於該基材;複數個第二鰭式結構,突出於該基材且平行於該些第一鰭式結構,其中該些第二鰭式結構具有摻雜有p型摻雜物之一上段;一介電層,形成於該基材上以及該些第一鰭式結構以及該些第二鰭式結構中之每一者之一側表面上,其中該介電層之一頂表面係低於該些第一鰭式結構以及該些第二鰭式結構之一頂表面;複數個虛設鰭式結構,平行於該些第一鰭式結構以及該些第二鰭式結構,其中該些虛設鰭式結構中之至少一者係形成於每一該些第一鰭式結構以及每一該些第二鰭式結構之間,且其中該些虛設鰭式結構之一底表面係低於該介電質之該頂表面;一鍺化矽(SiGe)磊晶層,形成於該些第二鰭式結構上;一含鍺(Ge)氧化層,形成於該鍺化矽磊晶層上;以及一矽(Si)磊晶層,形成於該些第一鰭式結構上。
- 如請求項第9項所述之半導體結構,進一步包含一金屬閘極結構,形成於該些第一鰭式結構以及該些第二鰭式結構中之每一者之一頂表面以及該側表面上。
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CN109427870A (zh) | 2019-03-05 |
TW201913817A (zh) | 2019-04-01 |
US20230117420A1 (en) | 2023-04-20 |
US10672892B2 (en) | 2020-06-02 |
CN109427870B (zh) | 2021-11-30 |
US20190334014A1 (en) | 2019-10-31 |
US12040386B2 (en) | 2024-07-16 |
US20190067444A1 (en) | 2019-02-28 |
US10347751B2 (en) | 2019-07-09 |
US11532735B2 (en) | 2022-12-20 |
US20200295155A1 (en) | 2020-09-17 |
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