TW201914025A - 半導體裝置與其製作方法 - Google Patents

半導體裝置與其製作方法 Download PDF

Info

Publication number
TW201914025A
TW201914025A TW107121167A TW107121167A TW201914025A TW 201914025 A TW201914025 A TW 201914025A TW 107121167 A TW107121167 A TW 107121167A TW 107121167 A TW107121167 A TW 107121167A TW 201914025 A TW201914025 A TW 201914025A
Authority
TW
Taiwan
Prior art keywords
fin
metal gate
dielectric
semiconductor device
side wall
Prior art date
Application number
TW107121167A
Other languages
English (en)
Other versions
TWI692104B (zh
Inventor
蔡雅怡
賴俊良
古淑瑗
陳嘉仁
張銘慶
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201914025A publication Critical patent/TW201914025A/zh
Application granted granted Critical
Publication of TWI692104B publication Critical patent/TWI692104B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Engineering & Computer Science (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一種半導體裝置包含基板，從基板突出的第一和第二鰭片，以及分別設置在第一和第二鰭片上的第一和第二高介電常數金屬閘極。從俯視圖看，第一和第二鰭片沿第一方向縱向佈置，第一和第二高介電常數金屬閘極沿著大致垂直於第一方向的第二方向縱向佈置，並且第一和第二高介電常數金屬閘極沿著第二方向排列。在沿著第二方向切割的橫截面視圖中，第一高介電常數金屬閘極具有從頂部到底部傾斜地朝向第二高介電常數金屬閘極的第一側壁，並且第二高介電常數金屬閘極具有從頂部到底部傾斜地朝向第一高介電常數金屬閘極的第二側壁。製造半導體裝置的方法亦在此公開。

Description

具有傾斜側壁的切割金屬閘極
半導體積體電路(integrated circuit,IC)行業經歷了指數增長。積體電路的材料和設計方面的技術進步已經產生了幾代的積體電路，其中每一代都具有比上一代更小和更複雜的電路。在積體電路演進的過程中，功能密度(即，每個晶片面積的互連裝置的數量)已經增加，而幾何尺寸(即，可以使用製造程序創建的最小元件(或線寬))已經減小。這種縮小過程通常透過提高生產效率和降低相關成本來提供益處。這種縮小也增加了積體電路的處理和製造的複雜性。
隨著技術節點的縮小，在一些積體電路設計中已使用金屬閘極代替典型的多晶矽閘極，以提高裝置性能並減小特徵尺寸。形成金屬閘極的一個過程被稱為替代閘極或「閘極最後」的製程，其中金屬閘極被「最後」製造，其允許減少一些必須在形成閘極後才能執行的後續製程，包括高溫處理。然而，實施這種積體電路的製程仍存在挑戰，特別是在先進製程節點(如N10、N5等)中縮小的積體電路的特性。現今的挑戰是如何在替換後有效地隔離金屬閘極。
100‧‧‧裝置
102‧‧‧基板
104‧‧‧鰭片
106‧‧‧隔離結構
108‧‧‧高介電常數介電層
110‧‧‧導電層
112‧‧‧閘極堆疊/高介電常數金屬閘極
112L‧‧‧左側部分
112R‧‧‧右側部分
113‧‧‧切割金屬閘極溝槽/開口
114‧‧‧介電層
116‧‧‧介電層
150‧‧‧界面層
152‧‧‧電極層
154‧‧‧硬掩模層
156‧‧‧硬掩模層
158‧‧‧溝槽
160‧‧‧閘極間隔物
162‧‧‧源極/汲極特徵
164‧‧‧接觸蝕刻停止層
166‧‧‧層間介電層
168‧‧‧保護性介電層
169‧‧‧閘極溝槽
170‧‧‧硬掩模層
172‧‧‧硬掩模層
200‧‧‧方法
202、204、206、208、210、212、214、216、218、220、222‧‧‧操作
H1‧‧‧高度
W1‧‧‧寬度
W2‧‧‧寬度
SW1‧‧‧側壁
SW2‧‧‧側壁
1-1‧‧‧線
B-B‧‧‧線
X‧‧‧方向
Y‧‧‧方向
Z‧‧‧方向
θ 1‧‧‧角度
θ 2‧‧‧角度
當結合附圖一起閱讀時，可以從以下詳細描述中最好地理解本公開。需要強調的是，根據該行業的標準慣例，各種特徵不是按比例繪製的，且僅是用於說明目的。實際上，為了清楚討論，各種特徵的尺寸可以任意增加或減小。
第1A圖繪示根據本公開的各方面中，利用切割金屬閘極製程而實現的半導體結構的俯視圖。
第1B圖和第1C圖繪示根據一個實施例中，第1A圖的結構的橫截面圖。
第2A圖和第2B圖繪示根據本公開的各方面中，用於形成第1A圖至第1C圖所示之結構的方法的流程圖。
第3圖、第4A圖、第4B圖、第5圖、第6A圖、第6B圖、第7A圖、第7B圖、第8圖、第9圖、第10圖、第11圖和第12圖繪示根據一個實施例中，第2A圖至第2B圖的方法在製程期間半導體結構的橫截面圖。
以下公開提供了用於實現所提供的主題的不同特徵的許多不同實施例或示例。以下描述元件和配置的具體實施例以簡化本公開。當然，這些僅僅是示例，並不意在限制。例如，在下面的描述中，在第二特徵之上或上方形成第一特徵可以包括其中第一特徵和第二特徵形成為直接接觸的實施例，並且還可以包括可以在第一特徵和第二特徵之間形成額外特徵的實施例，使得第一特徵和第二特徵可以不直接接觸。另外， 本公開可以在各個實施例中重複附圖符號和/或文字。這種重複是為了簡單和清楚的目的，並且本身並不指定所討論的各種實施例和/或配置之間的關係。
此外，為了便於描述，這裡可以使用諸如「在...之下」、「在...下方」、「低於」、「在...之上」、「高於」等的空間相對術語來描述一個元件或特徵與如附圖所示的另一個元件或特徵的關係。除了附圖中描繪的方向之外，空間相對術語旨在涵蓋使用或操作中的裝置的不同方位。此裝置可以以其他方式定向(旋轉90度或在其他方位)並且同樣可以相應地解釋這裡使用的空間相關描述符。
本公開涉及半導體裝置與其製造方法，並且更具體地涉及使用切割金屬閘極製程來製造半導體裝置。切割金屬閘極製程是指在金屬閘極(例如，高介電常數金屬閘極(high-k metal gate,HK MG))替換虛設閘極結構(例如，多晶矽閘極)之後，金屬閘極被切割(例如，通過蝕刻製程)以將金屬閘極分成兩個或更多個部分。每個部分用作單個電晶體的金屬閘極。隨後將隔離材料填充到金屬閘極相鄰部分之間的溝槽中。這些溝槽在本公開中被稱為切割金屬閘極溝槽(cut metal gate trench,CMG trench)。隨著裝置繼續縮小，切割金屬閘極溝槽的深寬比(定義為切割金屬閘極溝槽的高度與切割金屬閘極溝槽的寬度的比例)通常會增加。當切割金屬閘極溝槽具有垂直的側壁時，這將使得將隔離材料完全地填充切割金屬閘極溝槽變得更加困難。如果在此隔離材料中存在間隙或空隙，可能會導致短路等電路缺陷。本公開的目的是設計一種切 割金屬閘極的方法，以便產生具有錐形輪廓的切割金屬閘極溝槽，其頂部開口比其底部開口更寬。換句話說，如此生產的切割金屬閘極溝槽具有傾斜的側壁。這種錐形輪廓有助於將隔離材料填充到切割金屬閘極溝槽中，以消除隔離材料中的間隙或空隙。這種錐形輪廓對於具有高深寬比例(例如，5至10)的切割金屬閘極溝槽特別有用。
第1A圖繪示半導體裝置(或半導體結構)100的俯視圖。第1B圖繪示沿著第1A圖的B-B線的裝置100的橫截面圖。如第1A圖和第1B圖所示，裝置100包括基板102，從基板102突出的複數個鰭片104，在基板102上方和鰭片104之間的隔離結構106，以及設置在鰭片104和隔離結構106上方的複數個閘極堆疊112。每個閘極堆疊112包括高介電常數介電層108和在高介電常數介電層108上的導電層110。導電層110包括一層或多層金屬材料。因此，每個閘極堆疊112也被稱為高介電常數金屬閘極(或high-k metal gate,HK GM)112。閘極堆疊112可以進一步包括在高介電常數介電層108下方的界面層(未繪示)。
從頂視圖看，鰭片104沿X方向縱向排列，並且閘極堆疊112沿著大致上垂直於X方向的Y方向縱向排列。此外，鰭片104通常彼此平行，並且閘極堆疊112大致上彼此平行。裝置100還包括沿X方向縱向配置並且將每個閘極堆疊112分成至少兩個部分的介電層114。閘極堆疊112的每個部分接合相應的鰭片104以形成單獨的鰭狀場效應電晶體(FinFET)。裝置100還包括設置在閘極堆疊112和介電層114上的一個或 多個介電層116。下面將進一步描述裝置100的元件。
在本實施例中，基板102是矽基板。或者，基板102可以包括另一種元素半導體，例如鍺；化合物半導體，例如包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和銻化銦；合金半導體，例如包括矽鍺、磷化鎵砷、磷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦和鎵銦砷磷化物；或其組合。
鰭片104可以包括一種或多種半導體材料，例如矽、鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、矽鍺、磷化鎵砷、磷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦和鎵銦砷磷化物。在一個實施例中，鰭片104可以包括交替堆疊的兩種不同半導體材料的層，例如矽和矽鍺交替堆疊的層。鰭片104可另外包括用於改善裝置100性能的摻雜劑。例如，鰭片104可包括n型摻雜劑(例如磷或砷)或p型摻雜劑(例如硼或銦)。
隔離結構106可以包括氧化矽、氮化矽、氮氧化矽、氟摻雜矽酸鹽玻璃(fluoride-doped silicate glass,FSG)、低介電常數介電材料和/或其它合適的絕緣材料。隔離結構106可以是淺溝槽隔離(shallow trench isolation,STI)特徵。其他隔離結構可能是例如場氧化物、矽的局部氧化(local oxidation of silicon,LOCOS)、和/或其他合適的結構。隔離結構106可以包括例如與鰭片104相鄰且具有一個或多個熱氧化物襯墊層的多層結構。
高介電常數介電層108可以包括一種或多種高介電常數介電材料(或一層或多層高介電常數介電材料)，例如 氧化鉿矽(HfSiO)、氧化鉿(HfO2)、氧化鋁(Al2O3)、氧化鋯(ZrO2)、氧化鑭(La2O3)、氧化鈦(TiO2)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3)或它們的組合。
導電層110包括一個或多個金屬層，例如功函數金屬層、導電阻擋層和金屬填充層。取決於裝置的類型(P型場效應電晶體(PFET)或N型場效應電晶體(NFET))，功函數金屬層可以是P型或N型功函數層。P型功函數層包含具有足夠大的有效功函數的金屬，其選自但不限於氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、鎢(W)、鉑(Pt)或其組合。N型功函數層包含具有足夠小的有效功函數的金屬，其選自但不限於鈦(Ti)、鋁(Al)、碳化鉭(TaC)、碳氮化鉭(TaCN)、鉭氮化矽(TaSiN)、氮化鈦矽(TiSiN)或其組合。金屬填充層可以包括鋁(Al)、鎢(W)、鈷(Co)和/或其他合適的材料。
介電層114可以包括一種或多種介電質材料，諸如氮化矽、氧化矽、氮氧化矽、氟化物摻雜矽酸鹽玻璃、低介電常數介電質材料和/或其他合適的絕緣材料。特別地，介電層114的與閘極堆疊112物理接觸的部分包括不與閘極堆疊112的金屬材料反應的介電材料。例如，在一實施例中，介電層114的此部分包括氮化矽。
介電層116可以包括一種或多種介電質材料，諸如氮化矽、氧化矽、氮氧化矽、氟化物摻雜矽酸鹽玻璃、低介電常數介電質材料和/或其他合適的絕緣材料。
請參照第1C圖，其進一步說明裝置100。在第1C 圖中，為了說明切割金屬閘極(cut metal gate,CMG)溝槽113的細節，省略了介電層114和介電層116。在此橫截面圖中，切割金屬閘極溝槽113將閘極堆疊112分離成左側部分112L和右側部分112R。左側部分112L接合兩個鰭片104以形成電晶體，右側部分112R接合另兩個鰭片104以形成另一個電晶體。在各種實施例中，左側(或右側)部分可以接合任何數量的鰭片104以形成電晶體。左側部分112L具有從頂部至底部傾斜地朝向右側部分112R側壁SW1。側壁SW1與基板102的法線Z方向形成角度θ 1。右側部分112R具有從頂部至底部傾斜地朝向左側部分112L側壁SW2。側壁SW2與Z方向形成角度θ 2。切割金屬閘極溝槽113延伸到隔離結構106中，以確保閘極堆疊112的左側部分和右側部分彼此完全隔離。從閘極堆疊112和隔離結構106之間的界面到閘極堆疊112的頂表面測量，閘極堆疊112具有沿著Z方向的高度H1。切割金屬閘極溝槽113在閘極堆疊112的頂表面處具有頂部開口，以及在閘極堆疊112和隔離結構106之間的界面處的底部開口。頂部開口具有寬度W1，並且底部開口具有寬度W2。切割金屬閘極溝槽113的深寬比定義為高度H1/寬度W1(H1/W1)。
在一個實施例中，高度H1可以在80奈米(nm)至140奈米的範圍內，並且頂部開口的寬度W1可以在16奈米至30奈米的範圍內。切割金屬閘極溝槽113的深寬比可以在3至10，例如4至8或5至7的範圍內。對於高深寬比，如果切割金屬閘極溝槽113具有垂直的側壁(典型地，金屬膜的乾式蝕刻會產生垂直的側壁)，介電層114將會難以完全地填充切割 金屬閘極溝槽113，因為現有的沉積技術通常不能很好地沉積在深而窄的溝槽底部。在本實施例中，切割金屬閘極溝槽113被設計和繪製成具有錐形輪廓，即具有W1>W2。實驗證明，這種錐形輪廓改善了介電層114在切割金屬閘極溝槽113內的填充。
在不同實施例中，角度θ 1和角度θ 2中的每一個皆大於0°(因此，「傾斜的」側壁)並且小於tan-1(1/(2×AR))，其中AR是切割金屬閘極溝槽的深寬比，其在本實施例中等於H1/W1。如果兩個角度θ 1、θ 2皆等於tan-1(1/(2×AR))，則切割金屬閘極溝槽113幾乎不會到達隔離結構106。為了確保閘極堆疊112的左側部分和右側部分之間的隔離，角度θ 1和角度θ 2皆被設計為小於tan-1(1/(2×AR))。在一個實施例中，切割金屬閘極溝槽113被設計成使得角度θ 1和角度θ 2中的每一個皆在1°至10°(或者1度至10度)的範圍內，諸如從1.5°至7°或者從2°至5°。已經發現這種側壁的角度對於將介電材料114填充到高深寬比的切割金屬閘極溝槽113中是有幫助且有效的。在實施例中，兩個角度θ 1、θ 2可以彼此相等或不相等。
在一些實施例中，比值W2/W1被設計為從0.4到0.8，例如從0.5到0.7，以確保介電層114(第1B圖)完全地隔離閘極堆疊112的左側部分和右側部分，並且確保側壁的角度θ 1和角度θ 2足夠大以便於薄膜的沉積。實際上，側壁的角度θ 1和角度θ 2可以從寬度W1、寬度W2和高度H1的值推導出。
第2A圖和第2B圖示繪出根據實施例中，用於形 成半導體裝置100的方法200的流程圖。方法200僅僅是一個示例，並不意圖將本公開限制在請求項中明確記載的範圍之外。可以在方法200之前、期間和之後提供額外的操作，並且可以替換、消除或移動所描述的一些操作，以用於此方法之另外的實施例。下面結合第3圖至第12圖描述方法200，第3圖至第12圖繪示根據方法200的製造步驟期間，半導體裝置100的各種橫截面圖。
在操作202，方法200(第2A圖)提供或被提供裝置100，其具有基板102、突出於基板102的鰭片104、以及位於基板102之上和位於鰭片104之間的隔離結構106，例如第3圖所示。基板102、鰭片104和隔離結構106的各種材料已經於第1A圖和第1C圖中討論了。
在一個實施例中，基板102可以是晶片，例如矽晶片。可以透過在基板102的整個區域上磊晶生長一個或多個半導體層來形成鰭片104並且隨後將其圖案化以形成單獨的鰭片104。鰭片104可以透過任何合適的方法來圖案化。例如，可以使用一種或多種光刻製程(包括雙圖案化或多圖案化製程)來圖案化鰭片104。通常，雙重圖案化或多重圖案化製程結合了光刻和自對準製程，從而允許創建具有例如比使用單一、直接光刻製程可獲得的間距更小的間距的圖案。例如，在一個實施例中，在基板上方形成犧牲層並使用光刻製程進行圖案化。使用自對準製程沿著圖案化的犧牲層形成間隔物。接著移除犧牲層，然後透過刻蝕初始磊晶半導體層使用剩餘的間隔物或心軸來圖案化鰭片104。蝕刻製程可以包括乾式蝕刻、濕 式蝕刻、反應離子蝕刻(reactive ion etching,RIE)和/或其他合適的製程。例如，乾式蝕刻製程可以執行含氧氣體、含氟氣體(例如四氟化碳(CF4)、六氟化硫(SF6)、二氟甲烷(CH2F2)、三氟甲烷(CHF3)和/或六氟乙烷(C2F6))、含氯氣體(例如氯氣(Cl2)、三氯甲烷(CHCl3)、四氯化碳(CCl4)、和/或三氯化硼(BCl3))、含溴氣體(例如溴化氫(HBr)和/或三溴甲烷(CHBR3))、含碘氣體、其他合適的氣體和/或等離子體，和/或其組合。例如，濕式蝕刻製程可以包括在稀釋的氫氟酸(diluted hydrofluoric acid,DHF)中蝕刻；氫氧化鉀(KOH)溶液；氨；包含氫氟酸(HF)、硝酸(HNO3)和/或乙酸(CH3COOH)的溶液；或其他合適的濕式蝕刻劑。
隔離結構106可以透過一種或多種沉積和蝕刻方法形成。沉積方法可以包括熱氧化、化學氧化和化學氣相沉積(chemical vapor deposition,CVD)，例如可流動化學氣相沉積(flowable chemical vapor deposition,FCVD)。蝕刻方法可以包括乾式蝕刻、濕式蝕刻和化學機械平坦化(chemical mechanical planarization,CMP)。
在操作204處，方法200(第2A圖)形成接合鰭片104的虛設(或臨時)閘極結構，如第4A圖和第4B圖所示。第4A圖繪示沿著第1A圖的1-1線切割的裝置100的橫截面圖。第4B圖繪示沿著第1A圖的B-B線切割的裝置100的橫截面圖。參照第4A圖和第4B圖，虛設閘極結構包括界面層150、電極層152和兩個硬掩模層154、156。操作204更在虛設閘極 結構的側壁上形成閘極間隔物160。
界面層150可以包括諸如氧化矽層(例如，SiO2)或氮氧化矽(例如，SiON)的介電質材料，並且可以透過化學氧化、熱氧化、原子層沉積(atomic layer deposition,ALD)、化學氣相沉積和/或其他合適的方法形成。電極層152可以包括多晶矽(poly-crystalline silicon,poly-Si)並且可以透過諸如低壓化學氣相沉積(low-pressure chemical vapor deposition,LPCVD)和電漿增強化學氣相沉積(plasma-enhanced CVD,PECVD)的合適沉積製程形成。每個硬掩模層154、156可以包括一層或多層介電質材料，例如氧化矽和/或氮化矽，並且可以透過化學氣相沉積或其他合適的方法形成。可以透過光刻和蝕刻製程來圖案化各個層150、152、154和156。閘極間隔物160可以包括諸如氧化矽、氮化矽、氮氧化矽、碳化矽、其它介電質材料或其組合的介電質材料，並且可以包括一個或多個材料層。可以透過在隔離結構106、鰭片104和虛設閘極結構(包含層150、152、154、156)上方沉積間隔材料作為覆蓋層來形成閘極間隔物160。然後透過非等向性蝕刻製程蝕刻間隔材料以暴露隔離結構106、硬掩模層156和鰭片104的頂表面。虛設閘極結構(包含層150、152、154、156)的側壁上的部分間隔物變成閘極間隔物160。相鄰閘極間隔物160提供溝槽158，其暴露裝置100的源極/汲極區域中的鰭片104。
在操作206處，方法200(第2A圖)形成各種特徵，包括源極/汲極(或S/D)特徵162、接觸蝕刻停止層(contact etch stop layer,CESL)164、層間介電(interlayer dielectric,ILD)層166，以及層間介電層166上的保護性介電層168，如第5圖所示，第5圖是沿著第1A圖的1-1線的裝置100的橫截面圖。例如，操作206可以蝕刻凹槽以進入暴露於溝槽158中的鰭片104，並且在凹槽中磊晶生長半導體材料。如第5圖所示，半導體材料可以升高到鰭片104的頂部表面上方。操作206可以分別地為N型場效應電晶體(NFET)和P型場效應電晶體(PFET)裝置形成源極/汲極特徵162。例如，操作206可以形成具有用於N型場效應電晶體裝置的n型摻雜矽或用於P型場效應電晶體裝置的p型摻雜矽鍺的源極/汲極特徵162。此後，操作206可以將接觸蝕刻停止層164和層間介電層166沉積在源極/汲極特徵162上。接觸蝕刻停止層164可以包括氮化矽、氮氧化矽、具有氧(O)或碳(C)元素的氮化矽和/或其他材料；並且可以通過化學氣相沉積、物理氣相沉積(physical vapor deposition,PVD)、原子層沉積或其他合適的方法形成。層間介電層166可以包括原矽酸四乙酯(tetraethylorthosilicate,TEOS)氧化物、未摻雜矽酸鹽玻璃或摻雜矽氧化物如硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)、熔凝矽石玻璃(fused silica glass,FSG)、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼摻雜矽玻璃(boron doped silicon glass,BSG)和/或其他合適的介電材料。層間介電層166可以通過電漿增強化學氣相沉積、可流動化學氣相沉積或其他合適的方法形成。隨後，操作206可回蝕層間介電層166並沉積保護性介電層168，保護性介電層168 可包含氮化物，例如氮化矽，以在隨後的蝕刻製程期間保護層間介電層166。操作206執行一個或多個化學機械平坦化製程以平坦化裝置100的頂表面、去除硬掩模層154和硬掩模層156，並暴露電極層152。
在操作208處，方法200(第2A圖)去除虛設閘極結構以形成閘極溝槽169，如第6A圖和第6B圖所示。第6A圖和第6B圖分別是沿著第1A圖裝置100的1-1線和B-B線的橫截面圖。閘極溝槽169暴露鰭片104的表面和閘極隔離物160的側壁表面。操作208可以包括對電極層152和界面層150中的材料具有選擇性的一個或多個蝕刻製程。蝕刻製程可以包括乾式蝕刻、濕式蝕刻、反應離子蝕刻或其他合適的蝕刻方法。
在操作210處，方法200(第2A圖)將高介電常數金屬閘極112沉積在閘極溝槽169中，如第7A圖和第7B圖所示。第7A圖和第7B圖分別是沿著第1A圖中裝置100的1-1線和B-B線的截面圖。高介電常數金屬閘極112包括高介電常數介電層108和導電層110。高介電常數金屬閘極112可以進一步包括在高介電常數介電層108和鰭片104之間的界面層(例如，SiO2)(未繪示)。界面層可以使用化學氧化、熱氧化、原子層沉積、化學氣相沉積和/或其他合適的方法來形成。請參考以上第1A圖至第1C圖對高介電常數介電層108和導電層110的材料的討論。高介電常數介電層108可以包括一層或多層高介電常數介電質材料，並且可以使用化學氣相沉積、原子層沉積和/或其他合適的方法來沉積。導電層110可以包括一個或多個功函數金屬層和金屬填充層，並且可以使用諸如化學氣相沉 積、物理氣相沉積、電鍍和/或其他合適製程的方法來沉積。
在操作212處，方法200(第2B圖)在裝置100上方形成一個或多個硬掩模層，如第8圖所示。第8圖是在這個製造階段中沿著第1A圖中裝置100的B-B線的橫截面圖。在這個例子中繪示了兩個硬掩模層170、172。在一個實施例中，硬掩模層170包括氮化鈦，而硬掩模層172包括氮化矽。在本實施例中，用於硬掩模層170的材料被選擇為與導電層110具有良好的粘附性，但卻不與導電層110反應。硬掩模層170、172可以使用化學氣相沉積、物理氣相沉積、原子層沉積、或其他合適的方法形成。
在操作214處，方法200(第2B圖)圖案化一個或一個以上硬掩模層以形成圖案化硬掩模，如第9圖中所示。第9圖是在這個製造階段中，沿著第1A圖的裝置100的B-B線的橫截面圖。在第9圖中，硬掩模層170、172被圖案化(例如，蝕刻)以提供暴露導電層110的開口113。在一個實施例中，操作214可以透過光致抗蝕劑的塗層、曝光、曝光後烘烤和顯影而在硬掩模層170、172上形成圖案化的光致抗蝕劑。圖案化的光致抗蝕劑對應於第1A圖的介電層114的圖案。接著，操作214使用圖案化的光致抗蝕劑作為蝕刻掩模來蝕刻硬掩模層170、172，以形成開口113。蝕刻製程可以包括濕式蝕刻、乾式蝕刻、反應離子蝕刻或其他合適的蝕刻方法。之後例如透過抗蝕劑剝離去除圖案化的光致抗蝕劑。應注意的是，硬掩模層170、172處的開口113的側壁是垂直的或幾乎垂直的。
在操作216處，方法200(第2B圖)透過開口113 蝕刻高介電常數金屬閘極112。圖案化的硬掩模層170、172保護高介電常數金屬閘極112的其餘部分免受蝕刻處理。參考第10圖，操作216將開口113向下延伸並穿過高介電常數金屬閘極112並進入隔離結構106。特別地，操作216控制蝕刻過程以產生傾斜的側壁SW1和側壁SW2，請參考如上第1C圖所討論的。蝕刻製程可以使用蝕刻高介電常數金屬閘極112中的各層的一種或多種蝕刻劑或蝕刻劑的混合物。
在示例性實施例中，導電層110包括氮化矽鈦(TiSiN)、氮化鉭(TaN)、氮化鈦(TiN)和鎢(W)或其組合。為了蝕刻這樣的導電層和高介電常數介電層108，操作216可以利用具有氯、氟、溴、氧、氫、碳或其組合的原子的蝕刻劑來施加乾式蝕刻製程。例如，蝕刻劑可以具有氯氣(Cl2)、氧氣(O2)、含碳和氟的氣體、含溴和氟的氣體以及含碳氫和氟的氣體的氣體混合物。用這種氣體混合物蝕刻高介電常數金屬閘極112往往會在蝕刻過程中產生沉積在切割金屬閘極溝槽113的側壁上的一些聚合物(或聚合物材料)。這些聚合物減緩了向側壁的蝕刻，由此產生了傾斜的側壁SW1和側壁SW2。在一個實施例中，蝕刻劑包括氯氣(Cl2)、氧氣(O2)、四氟化碳(CF4)、三氯化硼(BCl3)和三氟甲烷(CHF3)的氣體混合物。透過調節氣體混合物中三氯化硼(BCl3)的量，操作216可以控制沉積在切割金屬閘極溝槽113的側壁上的BOxNy聚合物的量，由此控制側壁SW1和側壁SW2的斜率。例如，操作216可以增加氣體混合物中三氯化硼(BCl3)的比例以增加沉積的BOxNy聚合物的量。可選地或另 外地，透過調節氣體混合物中三氟甲烷(CHF3)的量，操作216可以控制沉積在切割金屬閘極溝槽113的側壁上的TiFx和NFx聚合物的量，由此控制側壁SW1和側壁SW2的斜率。例如，操作216可以增加氣體混合物中三氟甲烷(CHF3)的比例，以增加沉積的TiFx和NFx聚合物的量。更進一步地，操作216可以調節氣體混合物中碳與氟的比例，以控制沉積在側壁SW1和側壁SW2上的CxFy聚合物的量。例如，操作216可以用CxFy代替四氟化碳(CF4)，其中x：y大於1：4(例如，六氟丁二烯(C4F6))，以便增加沉積的CxFy聚合物的量。上面討論的蝕刻劑和蝕刻製程可以應用於適用於導電層110和高介電常數介電層108的各種材料，但不限於上面討論的示例性材料氮化矽鈦(TiSiN)、氮化鉭(TaN)、氮化鈦(TiN)和鎢(W)。
更進一步地，操作216還可以控制蝕刻偏置電壓，以額外或替代地控制如上所述之蝕刻劑。較高的蝕刻偏壓(沿著Z方向)傾向於在切割金屬閘極溝槽113中產生更垂直的側壁，而較低的蝕刻偏壓降低蝕刻劑向下的離子轟擊，導致傾斜的側壁。在本實施例中，操作216可以施加在50V至100V範圍內的蝕刻偏壓。此外，在本實施例中，操作216可以在5mTorr至20mTorr的壓力，在100W至200W的能量，並在75度攝氏至125度攝氏的溫度下執行蝕刻過程。各種其他值的蝕刻偏壓、蝕刻壓力、蝕刻能量和蝕刻溫度皆是可能的。而且，為了確保閘極堆疊112的左側部分和右側部分之間的隔離，操作216執行一些過蝕刻以將切割金屬閘極溝槽113延伸到隔離結構106中。仔細控制這種過蝕刻，以不暴露基板102。
在操作218，方法200(第2B圖)用一種或多種介電質材料填充切割金屬閘極溝槽113以形成如第11圖所示的介電層114。由於閘極堆疊112的側壁(第10圖的側壁SW1和側壁SW2)包含金屬材料，因此至少介電層114的外側部分(其與側壁SW1和側壁SW2直接接觸)沒有活性化學成分如氧氣。在本實施例中，介電層114的外側部分包含氮化矽且不含氧或氧化物。要注意的是，由於高介電常數介電層108包括氧，所以一些氧含量可能最終會擴散到介電層114的一些部分中。然而，這種擴散氧通常被限制於介電層114的下部分。在一些實施例中，介電層114可以在其內部包括一些氧化物。或者，介電層114可以包括一個均勻的氮化矽層並且不含氧化物。介電層114可以使用化學氣相沉積、物理氣相沉積、原子層沉積或其他合適的方法來沉積。在本實施例中，使用原子層沉積法沉積介電層114，以確保其完全地填充切割金屬閘極溝槽113。
在操作220處，方法200(第2B圖)執行一個或多個化學機械平坦化製程以去除多餘的介電層114(切割金屬閘極溝槽113外部的部分)和硬掩模層172、170。在一個實施例中，當利用化學機械平坦化製程去除硬掩模層172時，硬掩模層170作為化學機械平坦化停止層。在另一個實施例中，操作220可以將導電層110(以及介電層114)凹陷到期望的高介電常數金屬閘極的高度。最終的結構如第12圖所示。
在操作222處，方法200(第2B圖)執行進一步的步驟以完成裝置100的製造。例如，方法200可形成接觸和 通孔，以將源極/汲極特徵162(第7A圖)和閘極堆疊112電連接並形成連接各種電晶體的金屬互連，以形成完整的積體電路。
儘管不意圖進行限制，但是本公開的一個或多個實施例為半導體裝置及其形成提供許多益處。例如，本公開的實施例提供了具有傾斜的側壁的切割金屬閘極溝槽。傾斜的側壁改善了在可能具有高深寬比的溝槽中介電材料的填充。這對小型裝置特別有用。此外，本公開的實施例可以容易地整合到現有的半導體製造製程中。
在一個示例性方面中，本公開涉及一種半導體裝置。此裝置包括基板；從基板突出的第一鰭片和第二鰭片；以及第一高介電常數金屬閘極和第二高介電常數金屬閘極，其中第一高介電常數金屬閘極設置在第一鰭片上，並且第二高介電常數金屬閘極設置在第二鰭片上。從頂視圖看，第一鰭片和第二鰭片沿第一方向縱向佈置，第一高介電常數金屬閘極和第二高介電常數金屬閘極沿著大致上垂直於第一方向的第二方向縱向佈置，並且第一高介電常數金屬閘極和第二高介電常數金屬閘極沿著第二方向排列。在沿著第二方向切割的橫截面圖中，第一高介電常數金屬閘極具有第一側壁，第一側壁從頂部到底部傾斜地朝向第二高介電常數金屬閘極，並且第二高介電常數金屬閘極具有第二側壁，第二側壁從頂部到底部傾斜地朝向第一高介電常數金屬閘極。
在此裝置的一個實施例中，第一側壁與基板的法線形成第一角度，並且第一角度在1度至10度的範圍內。在另 一個實施例中，第一角度在2度至5度的範圍內。在另一個實施例中，第二側壁與基板的法線形成第二角度，並且第二角度在1度至10度的範圍內。例如，第二角度在2度至5度的範圍內。
在一個實施例中，此裝置還包括橫向位於第一側壁和第二側壁之間的介電質材料。在另一個實施例中，介電質材料完全地填充第一側壁和第二側壁之間的空間。
在另一個實施例中，第一距離位於第一側壁和第二側壁之各自的頂部之間，第二距離位於第一側壁和第二側壁之各自的底部之間，並且第二距離與第一距離的比例在0.4至0.8的範圍內。在另一個實施例中，第二距離與第一距離的比例在0.5至0.7的範圍內。
在此裝置的一個實施例中，第一高介電常數金屬閘極的高度與第一側壁和第二側壁之各自的頂部之間的距離的比例在3至10的範圍內。例如，此比例在5至7的範圍內。在另一個實施例中，此裝置還包括在第一鰭片和第二鰭片之間以及在第一高介電常數金屬閘極和第二高介電常數金屬閘極之下的隔離結構。
在另一個示例性方面中，本公開涉及一種半導體裝置。此裝置包括基板；從基板突出的第一鰭片和第二鰭片；從基板突出的第三鰭片和第四鰭片；設置在第一鰭片和第二鰭片之上的第一高介電常數金屬閘極以及設置在第三鰭片和第四鰭片上的第二高介電常數金屬閘極。從頂視圖看，第一鰭片、第二鰭片、第三鰭片和第四鰭片沿著第一方向縱向佈置，第一高介電常數金屬閘極和第二高介電常數金屬閘極沿著大 致垂直於第一方向的第二方向縱向對齊。在沿著第二方向切割的截面圖中，第一高介電常數金屬閘極具有第一側壁，第二高介電常數金屬閘極具有與第一側壁相對的第二側壁，並且第一側壁和第二側壁與基板的法線形成兩個角度，其中每個角度小於tan-1(1/(2×AR))，其中AR是第一高介電常數金屬閘極的高度與第一側壁和第二側壁各自的頂部之間的距離之比例。第一側壁和第二側壁之間的空間完全被一種或多種介電材料佔據。在一些實施例中，兩個角度中的每一個都在1.5度至7度的範圍內。
在此裝置的一個實施例中，在橫截面圖中，第一距離位於第一側壁和第二側壁各自的頂部之間，第二距離位於第一側壁和第二側壁各自的底部之間，第二距離到第一距離的比例在0.4到0.8的範圍內。在此設備的另一個實施例中，AR的範圍從4到8。
在又一個示例性方面中，本公開涉及一種方法。此方法包括提供具有基板，從基板突出的鰭片，和在基板上以及在相鄰鰭片之間的隔離結構，其中隔離結構低於鰭片。此方法還包括在隔離結構和鰭片上方形成閘極，其中閘極包括高介電常數介電層和導電層；以及對位於兩個相鄰鰭片之間的閘極執行蝕刻製程以暴露隔離結構，由此將閘極分成至少第一部分和第二部分。蝕刻製程被控制以產生第一部分的第一側壁和相對的第二部分的第二側壁，其中第一側壁和第二側壁提供比底部開口更寬的頂部開口。
在此方法的一個實施例中，此蝕刻製程包括具有 範圍從50V到100V的偏壓的乾式蝕刻。在此方法的一個實施例中，導電層包括鎢(W)，並且蝕刻製程使用的氣體含有CxFy的混合物，其中x：y大於1：4。
在本方法的一個實施例中，蝕刻製程包括使用氯氣、氧氣、含碳氟氣體、含溴和氟的氣體以及碳氫和氟的氣體混合物進行乾式蝕刻。在此方法的又一個實施例中，蝕刻製程包括用具有氯、氟、溴、氧、氫和碳原子的蝕刻劑進行乾式蝕刻。
以上概述了幾個實施例的特徵，以便本領域的普通技術人員可以更好地理解本公開的各方面。本領域的普通技術人員應該認識到，他們可以容易地使用本公開作為用於設計或修改用於執行相同目的和/或實現本文中介紹的實施例的相同優點的其他過程和結構的基礎。本領域的普通技術人員還應該認識到，這樣的等同構造不脫離本公開的精神和範圍，並且他們可以在不脫離本公開的精神和範圍的情況下進行各種改變、替換和修改。

Claims (20)

  1. 一種半導體裝置，包含：一基板；一第一鰭片和一第二鰭片，該第一鰭片和該第二鰭片從該基板突出；以及一第一高介電常數金屬閘極和一第二高介電常數金屬閘極，其中，該第一高介電常數金屬閘極設置在該第一鰭片上，該第二高介電常數金屬閘極設置在該第二鰭片上，其中，從一俯視圖看，該第一鰭片和該第二鰭片沿一第一方向縱向佈置，該第一高介電常數金屬閘極和該第二高介電常數金屬閘極沿著大致垂直於該第一方向的一第二方向縱向佈置，並且該第一高介電常數金屬閘極和該第二高介電常數金屬閘極沿著該第二個方向排列，其中，在沿著該第二方向切割的一橫截面視圖中，該第一高介電常數金屬閘極具有從一頂部到一底部傾斜地朝向該第二高介電常數金屬閘極之一第一側壁，並且該第二高介電常數金屬閘極具有從一頂部到一底部傾斜地朝向該第一高介電常數金屬閘極之一第二側壁。
  2. 如請求項1所述之半導體裝置，其中該第一側壁與該基板的一法線形成一第一角度，並且該第一角度在1度至10度的範圍內。
  3. 如請求項2所述之半導體裝置，其中該第一角度在2度至5度的範圍內。
  4. 如請求項2所述之半導體裝置，其中該第二側壁與該基板的該法線形成一第二角度，並且該第二角度在1度至10度的範圍內。
  5. 如請求項4所述之半導體裝置，其中該第二角度在2度至5度的範圍內。
  6. 如請求項1所述之半導體裝置，更包含橫向地位於該第一側壁和該第二側壁之間的一介電材料。
  7. 如請求項6所述之半導體裝置，其中該介電材料完全地填充該第一側壁和該第二側壁之間的一空間。
  8. 如請求項1所述之半導體裝置，其中一第一距離在該第一側壁和該第二側壁各自的該頂部之間，一第二距離在該第一側壁和該第二側壁各自的該底部之間，並且該第二距離與該第一距離之一比例在0.4到0.8的範圍內。
  9. 如請求項8所述之半導體裝置，其中該第二距離與該第一距離的該比例在0.5至0.7的範圍內。
  10. 如請求項1所述之半導體裝置，其中該第一高介電常數金屬閘極的一高度與該第一側壁和該第二側壁各自的該頂部之間的一距離的一比例在3到10的範圍內。
  11. 如請求項10所述之半導體裝置，其中該比例在5至7的範圍內。
  12. 如請求項1所述之半導體裝置，更包含在該第一鰭片和該第二鰭片之間以及在該第一高介電常數金屬閘極和該第二高介電常數金屬閘極之下的一隔離結構。
  13. 一種半導體裝置，包含：一基板；一第一鰭片和一第二鰭片，該第一鰭片與該第二鰭片從該基板突出；一第三鰭片和一第四鰭片，該第三鰭片和該第四鰭片從該基板突出；一第一高介電常數金屬閘極，設置在該第一鰭片和該第二鰭片之上；以及一第二高介電常數金屬閘極，設置在該第三鰭片和該第四鰭片之上，其中從一俯視圖看，該第一鰭片、該第二鰭片、該第三鰭片和該第四鰭片沿著一第一方向縱向佈置，該第一高介電常數金屬閘極和該第二高介電常數金屬閘極沿大致垂直於該第一方向的一第二方向縱向對齊，其中，沿該第二方向切割的一橫截面圖中，該第一高介電常數金屬閘極具有一第一側壁，該第二高介電常數金屬閘極具有與該第一側壁相對的一第二側壁，該第一側壁和該第 二側壁與該基板的一法線形成兩個角度，其中每個該角度小於tan -1(1/(2×AR))，其中AR是該第一高介電常數金屬閘極的一高度與該第一側壁和該第二側壁各自的一頂部之間的一距離的一比例，以及其中該第一側壁和該第二側壁之間的一空間完全被一種或多種介電材料填滿。
  14. 如請求項13所述之半導體裝置，其中在該橫截面圖中，一第一距離在該第一側壁和該第二側壁各自的該頂部之間，一第二距離在該第一側壁和該第二側壁各自的一底部之間，該第二距離與該第一距離的一比例在0.4至0.8的範圍內。
  15. 如請求項13所述之半導體裝置，其中該AR的範圍從4到8。
  16. 一種方法，包含：提供一結構，其包含：一基板；複數個鰭片，該些鰭片從該基板中突出，以及一隔離結構，該隔離結構位於該基板之上和相鄰的該些鰭片之間，其中該隔離結構低於該些鰭片；形成一閘極於該隔離結構和該些鰭片之上，其中該閘極包含一高介電常數介電層和一導電層；以及執行一蝕刻製程於兩個相鄰的該些鰭片之間的該閘極以 暴露該隔離結構，由此將該閘極分成至少為一第一部分和一第二部分，其中該蝕刻製程被控制以產生該第一部分的一第一側壁，以及相對的該第二部分的一第二側壁，其中該第一側壁和該第二側壁提供比一底部開口更寬的一頂部開口。
  17. 如請求項16所述之方法，其中該蝕刻製程包含利用範圍從50V到100V的一偏置電壓的乾式蝕刻。
  18. 如請求項16所述之方法，其中該導電層包含鎢(W)，並且該蝕刻製程使用含有C xF y的一氣體混合物，其中x：y大於1：4。
  19. 如請求項16所述之方法，其中該蝕刻製程包含使用氯氣、氧氣、含碳和氟的氣體、含溴和氟的氣體以及含碳氫和氟的氣體的一氣體混合物進行乾式蝕刻。
  20. 如請求項16所述之方法，其中該蝕刻製程包含用具有氯、氟、溴、氧、氫和碳的原子的一蝕刻劑進行乾式蝕刻。
TW107121167A 2017-08-30 2018-06-20 半導體裝置與其製作方法 TWI692104B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762551903P 2017-08-30 2017-08-30
US62/551,903 2017-08-30
US15/904,835 2018-02-26
US15/904,835 US10535654B2 (en) 2017-08-30 2018-02-26 Cut metal gate with slanted sidewalls

Publications (2)

Publication Number Publication Date
TW201914025A true TW201914025A (zh) 2019-04-01
TWI692104B TWI692104B (zh) 2020-04-21

Family

ID=65437569

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107121167A TWI692104B (zh) 2017-08-30 2018-06-20 半導體裝置與其製作方法

Country Status (4)

Country Link
US (2) US10535654B2 (zh)
KR (1) KR102169642B1 (zh)
CN (1) CN109427777B (zh)
TW (1) TWI692104B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11482421B2 (en) 2019-10-29 2022-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a semiconductor device by a replacement gate process

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109585293B (zh) * 2017-09-29 2021-12-24 台湾积体电路制造股份有限公司 切割金属工艺中的基脚去除
US10483369B2 (en) * 2017-10-30 2019-11-19 Globalfoundries Inc. Methods of forming replacement gate structures on transistor devices
US10629492B2 (en) 2018-04-27 2020-04-21 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure having a dielectric gate and methods thereof
US10854603B2 (en) 2018-06-29 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11398477B2 (en) 2019-05-29 2022-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
CN111341847B (zh) 2018-12-19 2023-03-28 联华电子股份有限公司 半导体结构及其制作方法
US11164866B2 (en) * 2019-02-20 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method for manufacturing the same
US11043595B2 (en) 2019-06-14 2021-06-22 Taiwan Semiconductor Manufacturing Co., Ltd. Cut metal gate in memory macro edge and middle strap
US11211116B2 (en) 2019-09-27 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded SRAM write assist circuit
CN110752152B (zh) * 2019-10-17 2021-10-15 上海华力集成电路制造有限公司 鳍式晶体管的多晶硅栅截断的工艺方法
US12002715B2 (en) 2019-10-29 2024-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US12009266B2 (en) * 2019-12-18 2024-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Structure for fringing capacitance control
US11508847B2 (en) * 2020-03-09 2022-11-22 Intel Corporation Transistor arrangements with metal gate cuts and recessed power rails
US11121138B1 (en) 2020-04-24 2021-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Low resistance pickup cells for SRAM
US11374088B2 (en) 2020-08-14 2022-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage reduction in gate-all-around devices
US12094822B2 (en) 2020-11-17 2024-09-17 Intel Corporation Buried power rails with self-aligned vias to trench contacts
US11670681B2 (en) 2021-01-14 2023-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming fully strained channels
US11482518B2 (en) 2021-03-26 2022-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structures having wells with protruding sections for pickup cells
US20240105453A1 (en) * 2022-09-27 2024-03-28 Intel Corporation High aspect ratio metal gate cuts
US20240222447A1 (en) * 2022-12-28 2024-07-04 Intel Corporation Gate cut, and source and drain contacts

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0023429B1 (en) 1979-07-31 1985-12-18 Fujitsu Limited Dry etching of metal film
JPH0622218B2 (ja) 1988-08-06 1994-03-23 富士通株式会社 エッチング方法
CN102347227B (zh) * 2010-07-30 2013-08-14 中芯国际集成电路制造(上海)有限公司 一种金属栅极的形成方法
CN102487039A (zh) * 2010-12-03 2012-06-06 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
KR20120089513A (ko) * 2010-12-13 2012-08-13 삼성전자주식회사 비휘발성 기억 소자 및 그 제조 방법
US8598675B2 (en) * 2011-02-10 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure profile for gap filling
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
CN103117213B (zh) * 2011-11-16 2015-10-07 中芯国际集成电路制造(上海)有限公司 金属栅极形成方法
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
CN104347477B (zh) * 2013-07-24 2018-06-01 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9331074B1 (en) * 2015-01-30 2016-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
TWI652824B (zh) * 2015-04-13 2019-03-01 聯華電子股份有限公司 半導體結構及製程
US9553090B2 (en) * 2015-05-29 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of semiconductor device structure
CN105244320A (zh) * 2015-08-28 2016-01-13 西安电子科技大学 基于SOI的应变Ge沟道倒梯形栅CMOS集成器件及制备方法
US9659930B1 (en) * 2015-11-04 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9520482B1 (en) * 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9773912B2 (en) * 2016-01-28 2017-09-26 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and manufacturing method thereof
US9627379B1 (en) * 2016-03-07 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET devices and methods of forming the same
US10032632B2 (en) * 2016-10-04 2018-07-24 International Business Machines Corporation Selective gas etching for self-aligned pattern transfer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11482421B2 (en) 2019-10-29 2022-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a semiconductor device by a replacement gate process
TWI794665B (zh) * 2019-10-29 2023-03-01 台灣積體電路製造股份有限公司 半導體裝置及其形成方法

Also Published As

Publication number Publication date
US20190067277A1 (en) 2019-02-28
KR102169642B1 (ko) 2020-10-23
US10535654B2 (en) 2020-01-14
US11616061B2 (en) 2023-03-28
CN109427777B (zh) 2021-08-24
CN109427777A (zh) 2019-03-05
TWI692104B (zh) 2020-04-21
KR20190024626A (ko) 2019-03-08
US20190088650A1 (en) 2019-03-21

Similar Documents

Publication Publication Date Title
TWI692104B (zh) 半導體裝置與其製作方法
US11721544B2 (en) Cut metal gate process for reducing transistor spacing
US11694931B2 (en) Metal gate structure cutting process
TWI732102B (zh) 半導體元件及其製造方法
TWI671903B (zh) 半導體裝置結構及其製造方法
TW201913755A (zh) 半導體裝置及其形成方法
TW201946121A (zh) 半導體裝置的形成方法
TWI814854B (zh) 對接接觸結構及半導體的製造方法
TW202017189A (zh) 半導體裝置
US11495494B2 (en) Methods for reducing contact depth variation in semiconductor fabrication
TW202002301A (zh) 半導體結構形成方法
US20230352345A1 (en) Metal gate structure cutting process
TW202005087A (zh) 半導體結構及半導體製程方法
TW201919119A (zh) 製造半導體結構之方法
US20220367482A1 (en) Source/Drain Feature Separation Structure
TWI824500B (zh) 半導體結構及其形成方法
TW202322398A (zh) 半導體結構及其製造方法