TWI732102B - 半導體元件及其製造方法 - Google Patents
半導體元件及其製造方法 Download PDFInfo
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- TWI732102B TWI732102B TW107105349A TW107105349A TWI732102B TW I732102 B TWI732102 B TW I732102B TW 107105349 A TW107105349 A TW 107105349A TW 107105349 A TW107105349 A TW 107105349A TW I732102 B TWI732102 B TW I732102B
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- 238000000034 method Methods 0.000 title claims description 120
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- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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Abstract
一種半導體元件包含:基板;半導體鰭片,自基板延伸;隔離結構,在基板上且橫向地介於半導體鰭片之間;襯層,介於半導體鰭片的側壁及隔離結構之間;以及蝕刻停止層,介於基板及隔離結構之間且橫向地介於半導體鰭片之間,蝕刻停止層包含一材料異於隔離結構及襯層。
Description
本發明實施方式係關於一種半導體元件及其製造方法,特別是關於一種具有蝕刻停止層介於基板與隔離結構之間的半導體元件及其製造方法。
半導體積體電路(integrated circuit,IC)產業已歷經指數型的成長。電路材料及設計上的技術進展已生產數種積體電路其每一世代都比前一世代具有較小且更複雜的電路。在積體電路的演化進程中,功能密度(即,每一晶片區域的互連元件數量)已普遍獲得提升,同時幾何尺寸(即,利用製造製程可被製造的最小部件(或線))亦已減小。這種縮小製程普遍藉由增加生產效率及降低相關費用提供了許多益處。此縮小製程亦會增加處理及製造積體電路的複雜度。
在一些積體電路的設計及製造的進展中,多晶矽閘極普遍被置換為金屬閘極以改善帶有
縮減尺寸特徵的元件表現。形成金屬閘極的其中一製程稱為閘極置換或「後閘極」製程,其金屬閘極為最後製造使得後續的製程次數得以減少,如高溫處理,其必須在形成閘極之後執行。然而,實施此種積體電路製造製程有許多挑戰。在一實施例中,在金屬閘極置換多晶矽閘極之後,對獨立的電晶體的金屬閘極進行蝕刻(或切割)。此蝕刻製程有時會蝕刻進基板中而將缺陷導入元件。據此,在這方面的改善為當前需求。
本揭露一實施態樣為一種半導體元件包含基板、半導體鰭片、隔離結構、襯層以及蝕刻停止層。半導體鰭片自基板延伸。隔離結構在基板上且橫向地介於半導體鰭片之間。襯層介於半導體鰭片的側壁與隔離結構之間。蝕刻停止層介於基板與隔離結構之間且橫向地介於半導體鰭片之間,此蝕刻停止層包含一材料異於隔離結構及襯層。
本揭露一實施態樣為一種半導體元件的製造方法包含提供結構,此結構具有半導體基板及自半導體基板突出的複數個半導體鰭片;形成介電襯層於此些半導體鰭片的至少複數個側壁上;形成蝕刻停止層與半導體基板接觸且介於相鄰的半導體鰭片之間;以及形成隔離結構於蝕刻停止層及介電
襯層上且介於相鄰的半導體鰭片之間。
本揭露一實施態樣為一種半導體元件的製造方法包含提供基板;形成圖案化遮罩於基板上;透過圖案化遮罩對基板進行蝕刻,藉此形成鰭片突出基板;形成襯層於基板及鰭片的側壁上,襯層包含氮化矽;非等向性蝕刻襯層以暴露基板,使得襯層的剩餘部分在鰭片的側壁上;在非等向性蝕刻襯層之後,形成一層矽化合物於基板上且介於鰭片之間;以及形成隔離結構於此層矽化合物上且介於鰭片之間。
100:元件、半導體元件、半導體結構、元件結構
101:圖案化遮罩
102:基板
102':頂面
103:襯層、介電襯層
104:鰭片
105:蝕刻停止層
106:隔離結構
108:高介電常數介電層
110:導電層
112:閘極堆疊、閘極結構、高介電常數金屬閘極
113:開口、切割金屬閘極溝槽
114:介電層、介電特徵
116:介電層
160:閘極間隔件
162:源極/汲極(源/汲極)特徵
164:接觸蝕刻停止層
166:層間介電層
168:保護層、保護性介電層
170:硬遮罩層
200:方法
202-226:操作
當結合附圖閱讀以下詳細描述時將更好地理解本揭露內容之態樣。但須注意依照本產業的標準做法,各種特徵未按照比例繪製。事實上,各種特徵的尺寸為了清楚的討論而可被任意放大或縮小。
第1A圖係根據本揭露各種態樣,顯示實施切割金屬閘極製程的半導體結構的頂視圖。
第1B圖係根據一實施方式,顯示第1A圖中半導體結構的剖視圖。
第2A圖及第2B圖係根據本揭露各種態樣,顯示用於形成第1A圖至第1B圖中之半導體結構的方法流程圖。
第3圖、第4圖、第5圖、第6圖、第7圖、第8圖、第9圖、第10A圖、第10B圖、第11圖、第12圖及第13圖係根據一實施方式,繪示在第2A圖至第2B圖中之方法的製造製程期間,半導體結構的剖視圖。
本揭露接下來將會提供許多不同的實施方式或實施方式以實施本揭露中不同的特徵。各特定實施方式中的組成及配置將會在以下作描述以簡化本揭露。這些為實施方式僅作為式範並非用於限定本揭露。例如,一第一元件形成於一第二元件「上方」或「之上」可包含實施方式中的第一元件與第二元件直接接觸,亦可包含第一元件與第二元件之間更有其他額外元件使第一元件與第二元件無直接接觸。此外,在本揭露各種不同的範例中,將重複地使用元件符號及/或字母。此重複乃為了簡化與清晰的目的,而其本身並不決定各種實施方式及/或結構配置之間的關係。
進一步來說,像是「之下」、「下面」、「較低」、「上面」、「較高」、以及其他類似之相對空間關係的用語,可用於此處以便描述圖式中一元件或特徵與另一元件或特徵之間的關係。該等相對空間關係的用語乃為了涵蓋除了圖式所描述的方向以外,裝置於使用或操作中之各種不同的方向。上述裝置
可另有其他導向方式(旋轉90度或朝其他方向),此時的空間相對關係也可依上述方式解讀。更進一步而言,除非文中另有特別指出,否則當數值或數值的範圍是以「大約」、「近似」及類似用語來描述時,意在表明包含此數值誤差百分之十(+/- 10%)所描述之範圍。舉例來說,用語「約5奈米」包含自4.5奈米至5.5奈米的範圍。
本揭露大致上係與半導體元件及製造方法有關,特別是利用金屬閘極切割製程來製造鰭式場效電晶體。金屬閘極切割製程指的是製造製程在金屬閘極(例如:高介電常數(high-k)金屬閘極)取代虛設閘極結構(例如:多晶矽閘極)之後,金屬閘極被蝕刻製程切割且分離為兩個或多個部分。各部分用於做為各獨立之鰭式場效電晶體的金屬閘極。為了確保前述兩個或多個部分完全分離,蝕刻製程常會過度蝕刻使得不僅金屬閘極會因蝕刻所穿透,在金屬閘極下方的隔離結構亦受到蝕刻。在一些例子中,過度蝕刻可能會意外地蝕穿隔離結構並進一步蝕刻至隔離結構下方的半導體基板中。此現象可能會導致電路的缺陷。本揭露之目的係藉由在半導體基板與隔離結構之間提供蝕刻停止層,以防止前述過度蝕刻蝕刻至半導體基板中。
第1A圖繪示半導體元件(或半導體結構)100的頂視圖。第1B圖繪示元件100沿第1A圖中
BB線的剖視圖。將第1A圖及第1B圖一併參照,元件100包含基板102、複數個鰭片104自基板102突出、隔離結構106在基板102上且介於此些鰭片之間,以及複數個閘極堆疊(或閘極結構)112配置於此些鰭片104及隔離結構106上。各閘極堆疊112包含高介電常數介電層108及導電層110於高介電常數介電層上。導電層110包含一或多層金屬材料。因此,各閘極堆疊112亦稱為高介電常數金屬閘極112。閘極堆疊112可進一步包含介面層(未繪示)於高介電常數介電層108之下。元件100進一步包含介電襯層103在鰭片104的側壁上,以及蝕刻停止層105配置於基板102的頂面且在隔離結構106的下方。蝕刻停止層105包含與隔離結構106不同的材料。
從頂視圖來看(第1A圖),鰭片104沿X方向縱長地進行排列,閘極堆疊112沿Y方向縱長地進行排列,其大致上與X方向垂直。進一步來說,鰭片104彼此大致上互相平行,以及閘極堆疊112彼此大致上互相平行。元件100進一步包含介電層114沿X方向縱長地進行排列並將各條閘極堆疊112分隔為至少兩個部分。閘極堆疊112的各部分嚙合各鰭片104以形成複數個獨立的鰭式場效電晶體。在本揭露實施方式中,介電層114延伸穿過隔離結構106並且實體接觸蝕刻停止層105。在另一實施方式中,介電層114並非完全延伸穿過隔離結構106亦無實體接觸
蝕刻停止層105。元件100進一步包含一或多個介電層116配置於閘極堆疊112及介電層114上。元件100的組件進一步描述於下方。
在本揭露實施方式中,基板102為矽基板。可供選擇的是,基板102可包含其他的基本半導體,例如鍺;複合半導體包含碳化矽、氮化鎵、砷化鎵、磷化鎵、磷化銦、砷化銦及銻化銦;合金半導體包含矽鍺、砷磷化鎵、磷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦及砷磷化鎵銦;或其組合。在另一實施方式中,基板102包含氧化銦錫(indium tin oxide,ITO)玻璃。
鰭片104可包含一或多種半導體材料,例如矽、鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、矽鍺、砷磷化鎵、磷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦及砷磷化鎵銦。在一實施方式中,鰭片104可包含兩種不同半導體材料交替堆疊的層體,例如矽和矽鍺交替堆疊的層體。鰭片104可額外包含用於改善元件100的表現的多種摻雜。舉例來說,鰭片104可包含一或多種n型摻雜劑(例如:磷或砷),或一或多種p型摻雜劑(例如:硼或銦)。
襯層103可包含氮化矽(例如:Si3N4),且可利用化學氣相沉積(chemical vapor deposition,CVD),例如低壓化學氣相沉積(low-pressure CVD,
LPCVD)或電漿增強化學氣相沉積(plasma-enhanced CVD,PECVD)、原子層沉積(atomic layer deposition,ALD)或其他適合的方法進行沉積。襯層103可具有厚度為約1奈米至約5奈米且實質上共形於鰭片104的側壁上。
在一實施方式中,蝕刻停止層105包含與隔離結構106不同的介電材料。舉例來說,蝕刻停止層105可包含氧化鋁(Al2O3)、碳化鎢(WC)或釔氧化矽(YSiOx)。進一步在此實施方式中,蝕刻停止層105可利用物理氣相沉積(physical vapor deposition,PVD)、化學氣相沉積、原子層沉積或其他適合的方法來進行沉積,且可具有厚度為約1奈米至約5奈米。在一特定的例子中,蝕刻停止層105包含共形地原子層沉積之Al2O3。
在另一實施方式中,蝕刻停止層105包含矽及下列群組中之一者:碳、鍺、III族元素及V族元素。舉例而言,蝕刻停止層105可包含碳、鍺、砷及磷中之一者及矽。在一實施方式中,蝕刻停止層105包含矽、碳化物、矽鍺、砷化矽、磷化矽或其組合。進一步在此實施方式中,蝕刻停止層105可利用物理氣相沉積、化學氣相沉積或磊晶成長製程來形成。在另一實施方式中,蝕刻停止層105包含以磷進行佈植的矽。尚有另一實施方式,蝕刻停止層105包含III-V族複合化合物,例如砷化鎵、磷化鎵、氮
化鎵及砷化銦。蝕刻停止層105的選擇可取決於用來蝕刻高介電常數金屬閘極112的蝕刻化合物,其將於後續進行討論。蝕刻停止層105可具有厚度為約1奈米至約5奈米。
隔離結構106可包含氧化矽、氮化矽、氮氧化矽、氟摻雜矽玻璃(fluoride-doped silicate glass,FSG)、低介電常數(low-k)介電材料及/或其他適合的絕緣材料。隔離結構106可為淺溝槽隔離(shallow trench isolation,STI)特徵。隔離結構106可利用化學氣相沉積,例如流動式化學氣相沉積或其他適合的方法來進行沉積。
高介電常數介電層108可包含一或多種高介電常數介電材料(或一或多層高介電常數介電材料),例如氧化鉿矽(HfSiO)、氧化鉿(HfO2)、氧化鋁(Al2O3)、氧化鍺(ZrO2)、氧化鑭(La2O3)、氧化鈦(TiO2)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3)或其組合。高介電常數介電層108可利用化學氣相沉積、原子層沉積及/或其他適合的方法來進行沉積。
導電層110包含一或多個金屬層,例如(複數個)功函數金屬層、(複數個)導電阻障層及(複數個)金屬填充層。取決於元件的類型(P型場效電晶體或N型場效電晶體),功函數金屬層可為p型或n型功函數金屬層。p型功函數金屬層包含金屬帶有夠大的有效功函數,例如選自但不限於由氮化鈦(TiN)、氮
化鉭(TaN)、釕(Ru)、鉬(Mo)、鎢(W)、鉑(Pt)或其組合所組成的群組。n型功函數金屬層包含金屬帶有夠小的有效功函數,例如選自但不限於鈦(Ti)、鋁(Al)、碳化鉭(TaC)、碳化鉭氮化物(TaCN)、氮化鉭矽(TaSiN)、氮化矽鈦(TiSiN)或其組合所組成的群組。金屬填充層可包含鋁(Al)、鎢(W)、鈷(Co)及/或其他適合的材料。導電層110可利用方法如物理氣相沉積、化學氣相沉積、電鍍及/或其他適合的製程來進行沉積。
介電層114可包含一或多種介電材料,例如氮化矽、氧化矽、氮氧化矽、氟摻雜矽玻璃、低介電常數(low-k)介電材料及/或其他適合的絕緣材料。尤其,與閘極堆疊112實體接觸的介電層114的部分包含一介電材料不會與閘極堆疊112的金屬材料產生反應。舉例而言,在一實施方式中,介電層114的此部分包含氮化矽。介電層114可利用化學氣相沉積、物理氣相沉積、原子層沉積或其他適合的方法來進行沉積。
介電層116可包含一或多種介電材料,例如氮化矽、氧化矽、氮氧化矽、氟摻雜矽玻璃、低介電常數(low-k)介電材料及/或其他適合的絕緣材料。介電層116可利用化學氣相沉積、物理氣相沉積或其他適合的方法來進行沉積。
第2A圖及第2B圖係根據一實施方式,繪
示用於形成半導體元件100的方法200流程圖。方法200僅做為範例,並非用以將本揭露限制於請求項所明確主張的範圍之外。額外的操作可用於方法200之前、期間及之後,且一些所述的操作可被取代、刪除或者因應此方法的額外實施方式而進行更動。方法200係結合第3圖至第13圖來做描述,其係根據方法200,繪示半導體元件100於製造步驟期間的各種剖視圖。
如第3圖所示,在操作202,方法200(第2A圖)提供,或被提供元件結構100具有基板102。基板102可用的各種材料已於上述參照第1A圖至第1B圖時所討論過。在一實施方式中,基板102可為晶圓,例如矽晶圓,且可包含一或多個磊晶成長的半導體層在其頂部。
如第3圖所示,在操作204,方法200(第2A圖)形成圖案化遮罩101於基板102上。圖案化遮罩101可利用一或多個光微影製程來形成,例如雙圖案或多圖案製程。大體而言,雙圖案或多圖案製程結合自我校準製程,使得所欲製作的圖案可具有例如小於利用單一、直接的光微影製程所能達成的線寬。舉例來說,在一實施方式中,犧性層形成於基板102上且藉由光微影製程而被圖案化。藉由自我校準製程,間隔件沿著圖案化的犧牲層而形成。接著,犧牲層被移除,故殘留的間隔件或心棒則成為圖案
化遮罩101。在各種實施方式中,圖案化遮罩101可包含氧化矽、氮化矽、光阻或其他適合的材料。
如第4圖所示,在操作206,方法200(第2A圖)以圖案化遮罩101做為蝕刻遮罩來蝕刻基板102,藉此形成鰭片104。圖案化遮罩101隨後被移除。蝕刻製程可包含乾式蝕刻、濕式蝕刻、反應性離子蝕刻(reactive ion etching,RIE)及/或其他適合的製程。舉例來說,乾式蝕刻製程可採用含氧氣體、含氟氣體(例如:CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯氣體(例如:Cl2、CHCl3、CCl4及/或BCl3)、含溴氣體(例如:HBr及/或CHBR3)、含碘氣體、其他適合的氣體及/或電漿,及/或其組合。舉例來說,濕式蝕刻製程可包含在稀氫氟酸(diluted hydrofluoric acid,DHF);氫氧化鉀(KOH)溶液;氨;含氫氟酸(HF)溶液、硝酸(HNO3)及/或醋酸(CH3COOH);或其他適合的濕式蝕刻劑中進行蝕刻。
在操作208,方法200(第2A圖)形成襯層103於鰭片104的側壁上。在本實施方式中,如第5圖所示,襯層103沉積於鰭片104的頂部及側壁上,並在基板102的頂面上。進一步在本實施方式中,襯層103包含氮化矽(例如:Si3N4),並且可利用低壓化學氣相沉積、電漿增強化學氣相沉積、原子層沉積或其他適合的方法來進行沉積。襯層103可沉積至厚度為1至5奈米,例如3奈米。
在操作210,方法200(第2A圖)對襯層103採用非等向性蝕刻製程。非等向性蝕刻製程設定為選擇性蝕刻襯層103但不會蝕刻基板102。參照第6圖,操作210自基板102的頂面102'移除部分襯層103,藉此暴露出頂面102'。由於高度定向蝕刻的關係,部分襯層103在鰭片104的側壁上實質上未受到蝕刻。進一步而言,鰭片104的頂面可能也可能不會藉由此非等向性蝕刻製程而暴露出來。在一實施方式中,襯層103包含氮化矽,操作210可採用遠距式O2/N2放電搭配含氟氣體例如CF4、NF3或SF6,並可額外包含氫(H2)或CH4。各種其他選擇性的方法都可用於蝕刻襯層103。
在操作212,方法200(第2A圖)形成蝕刻停止層105於基板102上。參照第7圖,蝕刻停止層105配置於基板102上並且橫向地介於鰭片104之間。在一實施方式中,蝕刻停止層105包含介電材料,例如Al2O3、WC或YSiOx,並且利用化學氣相沉積、物理氣相沉積、原子層沉積或其他適合的方法被沉積為共形層。進一步在此實施方式中,蝕刻停止層105可被沉積至厚度為約1奈米至約5奈米。若厚度比約1奈米還薄,蝕刻停止層105可能沒辦法提供足夠的蝕刻停止功用。若厚度比約5奈米還厚,蝕刻停止層105可能會有井至井隔離(well to well isolation)及接面漏電的疑慮。
在另一實施方式中,蝕刻停止層105包含矽鍺,並且可藉由磊晶成長矽鍺於基板102的頂面102'上來形成(第6圖)。磊晶成長製程可為循環沉積及蝕刻(cyclic deposition and etching,CDE)製程、共流式(co-flow)磊晶沉積製程、低壓化學氣相沉積製程(low pressure chemical vapor deposition,LPCVD)、選擇性磊晶成長製程(selective epitaxy growth,SEG)或其他適合的製程。舉例來說,具有矽鍺的蝕刻停止層105可藉由循環沉積及蝕刻(CDE)之磊晶成長製程來形成,其是利用HCl做為蝕刻氣體,而具有H2、含矽化合物(例如SiH4)及含鍺化合物(GeH4)的前驅物則是做為沉積氣體。進一步在此實施方式中,蝕刻停止層105可沉積至厚度為約1奈米至約5奈米。若厚度比約1奈米還薄,蝕刻停止層105可能沒辦法提供足夠的蝕刻停止功用。若厚度比約5奈米還厚,蝕刻停止層105可能會有井至井隔離及接面漏電的疑慮。
在另一實施方式中,蝕刻停止層105包含砷化矽或磷化矽,並且可藉由適合的磊晶成長製程來形成。尚有另一實施方式,蝕刻停止層105包含磊晶成長的矽帶有磷或硼離子佈植。舉例來說,蝕刻停止層105可具有磷濃度為約1E15cm-3至約1E21cm-3,或硼濃度為約1E15cm-3至約1E21cm-3。在各種實施方式中,蝕刻停止層105可包含如前述參照第
1B圖所討論的其他材料。
如第8圖所示,在操作214,方法200(第2A圖)形成隔離結構106於蝕刻停止層105上並填充鰭片104之間的間隔。操作214可包含多種製程,例如沉積(例如:流動式化學氣相沉積)、退火、化學機械平坦化(chemical mechanical planarization,CMP)及回蝕。舉例來說,操作214可沉積具流動性的介電材料於基板102上並填充鰭片104之間的間隙。在一些實施方式中,沉積具流動性的介電材料包含導入含矽化合物及含氧化合物進行反應形成具流動性的介電材料,藉此填充間隙。隔離結構106所用的材料可包含未摻雜矽玻璃(undoped silicate glass,USG)、氟摻雜矽玻璃(fluoride-doped silicate glass,FSG)、磷矽玻璃(phosphosilicate glass,PSG)、硼磷矽玻璃(borophosphosilicate glass,BPSG)或其他適合的絕緣材料。接著,操作214對具流動性的材料執行一些退火製程使得具流動性的介電材料轉變為固體介電材料。退火製程可包含乾式退火或濕式退火,而溫度為約400至約550℃。隨後,操作214執行一或多個化學機械平坦化製程及/或回蝕製程以凹陷隔離結構106。
如第9圖所示,在操作216,方法200(第2B圖)凹陷隔離結構106及襯層103以暴露鰭片104的頂部。在多種實施方式中,操作216可採用一或多個濕
式蝕刻、乾式蝕刻、反應性離子蝕刻及/或其他適合的製程。
如第10A圖及第10B圖所示,在操作218,方法200(第2B圖)形成多種特徵在鰭片104之中或之上,包含閘極間隔件160、源極/汲極(源/汲極)特徵162、接觸蝕刻停止層164、層間介電層166、保護層168及具有高介電常數閘極介電層108及導電層110的高介電常數金屬閘極堆疊112。第10A圖為元件100沿鰭片104的長(第1A圖的1-1線)的剖視圖,以及第10B圖為元件100沿鰭片104的寬(第1A圖的B-B線)的剖視圖。操作218包含多種製程。在一特定的實施方式中,操作218包含閘極置換製程,其將於下文討論。
在閘極置換製程中,操作218先形成暫時性的閘極結構(未繪示)於隔離結構106上並嚙合於鰭片104。暫時性的閘極結構可包含具有氧化矽或氮化矽的虛設介面層,以及具有多晶矽的虛設電極。暫時性的閘極結構可藉由沉積及蝕刻製程來形成。
隨後,操作218形成閘極間隔件160於暫時性的閘極結構的側壁上。閘極間隔件160可包含介電材料,例如氧化矽、氮化矽、氮氧化矽、碳化矽、其他介電材料或其組合,而且可包含一或多層材料。閘極間隔件160可藉由沉積間隔件材料毯覆於隔離結構106、鰭片104及虛設閘極結構(未繪示)上來形成。接著,透過非等向性蝕刻製程蝕刻間隔件材
料。部分間隔件材料殘留於虛設閘極結構的側壁上,故形成閘極間隔件160。
接著,如第10A圖所示,操作218形成源/汲極特徵162於鰭片104上、接觸蝕刻停止層164於源/汲極特徵162上、層間介電層166於接觸蝕刻停止層164上以及保護性介電層168於層間介電層166上。舉例來說,操作218可蝕刻以製造凹陷至相鄰於閘極間隔件160的鰭片140之中,並磊晶成長半導體材料於此凹陷。半導體材料可抬起至鰭片104的頂面之上。操作218可分別形成用於N型場效電晶體(NFET)及P型場效電晶體(PFET)元件的源/汲極特徵162。舉例來說,操作218可形成帶有n型矽摻雜的源/汲極特徵162以用於N型場效電晶體,或是帶有p型矽鍺摻雜的源/汲極特徵162以用於P型場效電晶體。隨後,操作218可沉積接觸蝕刻停止層164及層間介電層166於源/汲極特徵162上。接觸蝕刻停止層164可包含氮化矽、氮氧化矽、氮化矽帶有氧(O)或碳(C)元素,及/或其他材料;且可藉由化學氣相沉積、物理氣相沉積、原子層沉積或其他適合的方法來形成。層間介電層166可包含四乙氧基矽烷(TEOS)氧化物、未摻雜矽玻璃或摻雜矽氧化物例如硼磷矽玻璃(BPSG)、融熔石英玻璃(fused silica glass,FSG)、磷矽玻璃(PSG)、硼摻雜矽玻璃(boron doped silicon glass,BSG)及/或其他適合的介電材料。層間介電層166可
利用電漿增強化學氣相沉積、流動式化學氣相沉積或其他適合的方法來進行沉積。接著,操作218可回蝕層間介電層166並沉積保護性介電層168,其可包含氮化物,例如在後續蝕刻製程期間用於保護介電層166的氮化矽。操作218執行一或多個化學機械平坦化製程以平坦化元件100的頂面。
接著,操作218移除虛設閘極結構以形成閘極溝槽(未繪示)於閘極間隔件160之間,並沉積高介電常數金屬閘極堆疊112於閘極溝槽中。高介電常數金屬閘極堆疊112包含高介電常數介電層108及導電層110。高介電常數金屬閘極堆疊112可進一步包含介面層(例如:二氧化矽或氮氧化矽)(未繪示)於高介電常數介電層108與鰭片104之間。介面層可利用化學氧化、熱氧化、原子層沉積、化學氣相沉積及/或其他適合的方法來形成。參照第1A圖至第1B圖,高介電常數介電層108及導電層110的材料已於前述討論過。高介電常數介電層108可包含一或多層高介電常數介電材料,並且可利用化學氣相沉積、原子層沉積及/或其他適合的方法來進行沉積。導電層110可包含一或多個功函數金屬層及金屬填充層,並且可利用化學氣相沉積、物理氣相沉積、電鍍及/或其他適合的製程來進行沉積。
在操作220時,方法200(第2B圖)形成硬遮罩層170於元件100上並對硬遮罩層170進行圖案化
以提供開口113。如第11圖所示,為元件100在第1圖沿B-B線在此階段時的剖視圖。硬遮罩層170包含氮化鈦、氮化矽、非晶矽、其組合或其他適合的材料。開口113暴露高介電常數金屬閘極堆疊112的一部分。從第1A圖中的頂視圖來看,開口113對應至介電特徵114的形狀。硬遮罩層170可利用化學氣相沉積、物理氣相沉積、原子層沉積或其他適合的方法來進行沉積。操作220可利用光微影及蝕刻製程以圖案化硬遮罩層170。舉例來說,藉由光阻塗佈、曝光、曝光後烘烤及顯影,操作220可形成圖案化光阻於硬遮罩170上。接著,操作220以圖案化光阻做為蝕刻遮罩對硬遮罩170進行蝕刻以形成開口113。蝕刻製程可包含濕式蝕刻、乾式蝕刻、反應性離子蝕刻或其他適合的蝕刻方法。藉由例如光阻剝離,圖案化光阻隨後被移除。
在操作222,方法200(第2B圖)透過開口113蝕刻高介電常數金屬閘極堆疊112。如第12圖所示,為了確保高介電常數金屬閘極堆疊112有被完全穿蝕,操作222執行過度蝕刻,藉此延伸開口113至隔離結構106中。由於開口113為一藉由切割高介電常數金屬閘極堆疊而形成的溝槽,故在本揭露中亦稱為切割金屬閘極(cut-metal-gate,CMG)溝槽。圖案化硬遮罩層170可保護其餘的高介電常數金屬閘極堆疊112免於受蝕刻製程影響。
蝕刻製程可利用一或多種蝕刻劑或蝕刻劑的混合物其可蝕刻高介電常數金屬閘極堆疊112中的多種層體。在一例示性的實施方式中,導電層110包含氮化矽鈦(TiSiN)、氮化鉭(TaN)、氮化鈦(TiN)、鎢(W)或其組合。為了要蝕刻此導電層110及高介電常數介電層108,操作222可採用乾式蝕刻製程具有氯、氟、溴、氧、氫、碳或其組合的原子的蝕刻劑。舉例來說,蝕刻劑可具有Cl2、O2、含碳氟氣體、含溴氟氣體及含碳氫氟氣體的氣體混合物。在一實施方式中,蝕刻劑包含Cl2、O2、CF4、BCl3及CHF3。這些蝕刻劑的類型典型來說在高介電常數金屬閘極堆疊112與隔離結構106之間並不具有良好的蝕刻選擇性。因此,蝕刻製程中可能會有穿透隔離結構106的風險。在未提供蝕刻停止層105的製造方法中,若隔離結構106被蝕穿時,基板102將會受到蝕刻而導入電路缺陷於此之中。
在本實施方式中,蝕刻停止層105可抵抗操作222的蝕刻製程。所以,即便隔離結構106被穿透(如第12圖所示),蝕刻製程不會穿透蝕刻停止層105,故不會蝕刻到基板102。在多種實施方式中,蝕刻停止層105所選用的材料係考量到操作222所用的蝕刻化合物。舉例來說,蝕刻劑具有CF4、Cl2、BCl3、O2及/或N2係無法有效蝕刻矽鍺(SiGe)、砷化矽(SiAs)或磷化矽(SiP)。因此,這些材料(SiGe、
SiAs或SiP)可用於蝕刻停止層105。除此之外,這些材料便於成長在矽基板102之上,使得製程整合更加容易。
如第13圖所示,在操作224,方法200(第2B圖)填充一或多種介電材料至切割金屬閘極溝槽113以形成介電層114。由於切割金屬閘極溝槽113的側壁含有金屬材料,介電層114至少有外部部分是直接接觸高介電常數金屬閘極堆疊112而未有活性化學成分(例如:氧)。舉例來說,介電層114的外部部分可包含氮化矽而未有氧或氧化物。在一些實施方式中,介電層114可包含一些氧化物在其內部部分。可供選擇地,介電層114可包含單一均勻層體的氮化矽而未有氧化物。介電層114可利用物理氣相沉積、化學氣相沉積、原子層沉積或其他適合的方法來進行沉積。接著,操作224執行一或多個化學機械平坦化製程以移除在切割金屬閘極溝槽113外過多的介電層114。進一步地,操作224可凹陷導電層110(以及介電層114)以達到理想的高介電常數金屬閘極堆疊高度。所產生的結構如第13圖所示。雖然第13圖繪示介電層114直接接觸蝕刻停止層105,在多種實施方式中,介電層114可能也可能不會直接接觸蝕刻停止層105。舉例來說,在未繪示於此的一些實施方式中,介電層114可藉由隔離結構106與蝕刻停止層105分隔開來。
在操作226,方法200(第2B圖)執行進一步的步驟以完成元件100的製造。舉例來說,方法200可形成接觸及導孔電性連接源/汲極特徵162(第10A圖)及閘極堆疊112並形成金屬互連體連接多種電晶體以形成一完整的積體電路(IC)。
儘管非用以限定,本揭露的一或多個實施方式可提供多種益處於半導體元件及其形成。舉例來說,本揭露的實施方式提供蝕刻停止層直接在半導體基板的上方且橫向地在半導體鰭片之間,以及提供隔離結構在蝕刻停止層上。此蝕刻停止層保護半導體基板免於受蝕刻製程影響,其會蝕刻高介電常數金屬閘極結構並且對高介電常數金屬閘極結構及隔離結構具有較差的蝕刻選擇性。有了蝕刻停止層,蝕刻製程的時間可被延長以確保高介電常數金屬閘極結構有被蝕穿從而不會有意外蝕刻至半導體基板的風險。更進一步來說,此蝕刻停止層的形成可輕易地整合至現有的半導體製造製程中。
在一例示性的態樣中,本揭露指出元件包含基板;半導體鰭片自基板延伸;隔離結構在基板上且橫向地介於半導體鰭片之間;襯層介於半導體鰭片的側壁及隔離結構之間;以及蝕刻停止層介於基板及隔離結構之間且橫向地介於半導體鰭片之間。蝕刻停止層包含材料異於隔離結構及襯層。
在元件的一實施方式中,蝕刻停止層包
含矽及下列群組中之一者:碳、鍺、III族元素及V族元素。在元件的另一實施方式中,蝕刻停止層包含氧化鋁(Al2O3)、碳化鎢(WC)、釔氧化矽(YSiOx)或III-V族化合物。
在一實施方式中,元件進一步包含高介電常數介電層在隔離結構上且在半導體鰭片的頂部及側壁上。在一進一步的實施方式中,元件進一步包含金屬閘極在高介電常數介電層上。
在一實施方式中,元件進一步包含介電特徵在蝕刻停止層上且介電特徵至少有側壁被隔離結構所圍繞。在一進一步的實施方式中,介電特徵實體接觸蝕刻停止層。
在元件的一實施方式中,基板包含矽;蝕刻停止層包含矽鍺;以及蝕刻停止層實體接觸基板。在元件的另一實施方式中,蝕刻停止層具有厚度為約1奈米至約5奈米。
在另一例示性的態樣中,本揭露指出方法包含提供結構具有半導體基板及半導體鰭片自半導體基板突出;形成介電襯層於半導體鰭片的至少複數個側壁上;形成蝕刻停止層與半導體基板接觸且介於相鄰的半導體鰭片之間;以及形成隔離結構於蝕刻停止層及介電襯層上且介於相鄰的半導體鰭片之間。
在一實施方式中,方法進一步包含形成
高介電常數/金屬閘極堆疊於隔離結構上且嚙合半導體鰭片;以及蝕刻高介電常數/金屬閘極堆疊以暴露隔離結構,藉此形成溝槽。在一進一步的實施方式中,溝槽暴露蝕刻停止層。方法可進一步包含以一介電材料填充溝槽。
在方法的一實施方式中,半導體基板包含矽;介電襯層包含氮化矽;隔離結構包含氧化矽;以及蝕刻停止層包含矽鍺。在方法的另一實施方式中,其中在形成介電襯層於半導體鰭片的至少此些側壁上的步驟中,此方法進一步包含:執行非等向性蝕刻製程於介電襯層以藉此暴露半導體基板。
在方法的一實施方式中,蝕刻停止層的形成包含磊晶成長製程。在方法的另一實施方式中,蝕刻停止層的形成包含沉積層體包含碳、鍺、砷及磷中之一者及矽。
尚有另一例示性的態樣,本揭露指出一種方法。方法包含提供基板;形成圖案化遮罩於基板上;透過圖案化遮罩對基板進行蝕刻,藉此形成鰭片突出基板;形成襯層於基板及鰭片的側壁上,襯層包含氮化矽;非等向性蝕刻襯層以暴露基板,使得襯層的剩餘部分在鰭片的側壁上;在非等向性蝕刻襯層之後,形成一層矽化合物於基板上且介於鰭片之間;以及形成隔離結構於此層矽化合物上且介於鰭片之間。
在方法的一實施方式中,此層矽化合物的形成包含磊晶成長碳化矽、矽鍺、砷化矽以及磷化矽中之一者。在方法的另一實施方式中,此層矽化合物的形成包含將磷或硼植入基板。
前文概述數個實施方式之特徵以使得熟習該項技術者可更好地理解本揭露之態樣。熟習該項技術者應瞭解,可容易地將本揭露內容用作設計或修改用於實現相同目的及/或達成本文引入之實施方式的相同優點之其他製程及結構之基礎。熟習該項技術者亦應認識到,此類等效物構造不違背本揭露內容之精神及範疇,且可在不違背本揭露內容之精神及範疇之情況下於此作出各種變化、替代以及變更。
100:元件、半導體元件、半導體結構、元件結
構
102:基板
103:襯層、介電襯層
104:鰭片
105:蝕刻停止層
106:隔離結構
108:高介電常數介電層
110:導電層
112:閘極堆疊、閘極結構、高介電常數金屬閘極
114:介電層、介電特徵
116:介電層
Claims (10)
- 一種半導體元件,包含:一基板;複數個半導體鰭片,自該基板延伸出;一隔離結構,在該基板上且橫向地介於該些半導體鰭片之間;一襯層,介於該些半導體鰭片的複數個側壁與該隔離結構之間;一蝕刻停止層,配置於該基板的一頂面,且介於該基板與該隔離結構之間並橫向地介於該些半導體鰭片之間,該蝕刻停止層包含一材料異於該隔離結構及該襯層,且該蝕刻停止層的一厚度為1奈米至5奈米;以及一介電特徵,在該蝕刻停止層上且該介電特徵至少有複數個側壁被該隔離結構所圍繞。
- 如申請專利範圍第1項所述之半導體元件,進一步包含一高介電常數介電層在該隔離結構上且在該些半導體鰭片的頂部及複數個側壁上。
- 如申請專利範圍第1項所述之半導體元件,進一步包含一閘極堆疊在該些半導體鰭片和該隔離結構上,其中該介電特徵的一部份實體接 觸該閘極堆疊。
- 如申請專利範圍第1項所述之半導體元件,其中該介電特徵實體接觸該蝕刻停止層。
- 一種半導體元件的製造方法,包含:提供一結構,該結構具有一半導體基板及自該半導體基板突出的複數個半導體鰭片;形成一介電襯層於該些半導體鰭片的至少複數個側壁上;形成一蝕刻停止層與該半導體基板接觸且介於相鄰的半導體鰭片之間;形成一隔離結構於該蝕刻停止層及該介電襯層上且介於相鄰的半導體鰭片之間;形成一高介電常數/金屬閘極堆疊於該隔離結構上且嚙合該些半導體鰭片;以及蝕刻該高介電常數/金屬閘極堆疊以暴露該隔離結構,藉此形成一溝槽。
- 如申請專利範圍第5項所述之半導體元件的製造方法,其中該形成該蝕刻停止層包含沉積一層體包含碳、鍺、砷及磷中之一者及矽。
- 如申請專利範圍第5項所述之半導 體元件的製造方法,其中該溝槽暴露該蝕刻停止層。
- 如申請專利範圍第5項所述之半導體元件的製造方法,其中該介電襯層形成於該些半導體鰭片的至少該些側壁上,進一步包含:執行一非等向性蝕刻製程於該介電襯層以藉此暴露該半導體基板。
- 一種半導體元件的製造方法,包含:提供一基板;形成一圖案化遮罩於該基板上;透過該圖案化遮罩對該基板進行蝕刻,藉此形成複數個鰭片突出該基板;形成一襯層於該基板及該些鰭片的複數個側壁上,該襯層包含氮化矽;非等向性蝕刻該襯層以暴露該基板,使得該襯層的剩餘部分在該些鰭片的該些側壁上;在該非等向性蝕刻該襯層之後,形成一層矽化合物於該基板上且介於該些鰭片之間;以及形成一隔離結構於該層矽化合物上且介於該些鰭片之間。
- 如申請專利範圍第9項所述之半 導體元件的製造方法,其中該層矽化合物的形成包含將磷或硼植入該基板。
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