CN110176443B - 用于减小接触电阻的双金属通孔 - Google Patents

用于减小接触电阻的双金属通孔 Download PDF

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CN110176443B
CN110176443B CN201810937686.5A CN201810937686A CN110176443B CN 110176443 B CN110176443 B CN 110176443B CN 201810937686 A CN201810937686 A CN 201810937686A CN 110176443 B CN110176443 B CN 110176443B
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barrier layer
cobalt
over
semiconductor device
layer
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CN110176443A (zh
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程仲良
陈彦羽
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

半导体器件包括位于衬底上方的有源区域；设置在有源区域上方的第一含钴部件；设置在第一含钴部件上方并且与第一含钴部件物理接触的导电帽；以及设置在导电帽上方并且与导电帽物理接触的第二含钴部件。本发明的实施例还涉及用于减小接触电阻的双金属通孔。

Description

用于减小接触电阻的双金属通孔
技术领域
本发明的实施例涉及用于减小接触电阻的双金属通孔。
背景技术
半导体集成电路(IC)工业已经经历了指数增长。IC材料和设计中的技术进步已经产生了多代IC，其中，每一代都比上一代具有更小和更复杂的电路。在IC演化过程中，功能密度(即，每芯片面积的互连器件的数量)已经普遍增大，而几何尺寸(即，可以使用制造工艺产生的最小组件(或线))已经减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。但是，这种按比例缩小已经增加了处理和制造IC的复杂性。
例如，具有钛(Ti)和氮化钛(TiN)阻挡层的钨(W)插塞通常用作金属互连中的通孔插塞。随着持续按比例缩小，通孔插塞也变得越来越小，并且这种W插塞显示出增加的电阻并且在某些情况下变得不适合。需要这些领域的改进。
发明内容
本发明的实施例提供了一种半导体器件，包括：有源区域，位于衬底上方；第一含钴部件，设置在所述有源区域上方；导电帽，设置在所述第一含钴部件上方并且与所述第一含钴部件物理接触；以及第二含钴部件，设置在所述导电帽上方并且与所述导电帽物理接触。
本发明的另一实施例提供了一种半导体器件，包括：第一含钴插塞，设置在衬底上方；导电帽，设置在所述第一含钴插塞上方并且与所述第一含钴插塞物理接触；第二含钴插塞，设置在所述导电帽上方并且与所述导电帽物理接触；第一阻挡层，位于所述第二含钴插塞和所述导电帽的侧壁上方；第二阻挡层，位于所述第一阻挡层的侧壁上方；以及一个或多个介电层，围绕所述第二阻挡层。
本发明的又一实施例提供了一种形成半导体器件的方法，包括：提供一种结构，所述结构具有衬底、位于所述衬底上方的一个或多个第一介电层、嵌入在所述一个或多个第一介电层内的第一含钴插塞以及位于所述一个或多个第一介电层和所述第一含钴插塞上方的一个或多个第二介电层；在所述一个或多个第二介电层中蚀刻导通孔以暴露所述第一含钴插塞；在所述导通孔中沉积具有氮化硅的第一阻挡层；在所述导通孔中和所述第一阻挡层上方沉积具有氮化钛或氮化钽的第二阻挡层；蚀刻所述导通孔中的所述第一阻挡层和所述第二阻挡层以暴露所述第一含钴插塞；在暴露在所述导通孔中的所述第一含钴插塞上方形成导电帽；以及在所述导电帽上方选择性地生长钴。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据本发明的各个方面构建的半导体结构的截面图。
图2A和图2B示出了根据本发明的各个方面的用于形成图1所示的半导体结构的方法的流程图。
图3、图4、图5、图6、图7、图8、图9、图10、图11和图12示出了根据一些实施例的根据图2A至图2B的方法的各个制造步骤期间的半导体结构的截面图。
图13示出了根据本发明的各个方面构建的半导体结构的一部分的元素分析。
图14示出了根据一些实施例的根据图2A至图2B的方法的可以用于实施一些制造步骤的原位集群工具。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。更进一步地，当利用“约”、“近似”等描述数值或数值范围时，除非另有说明，否则该术语旨在包括在所描述的数值的+/-10％内的数值。例如，术语“约5nm”包括4.5nm至5.5nm的范围的尺寸。
本发明通常涉及半导体器件和制造方法，并且更具体地涉及用于互连集成电路(IC)的不同层之间的导电部件的插塞。插塞有时称为通孔插塞或接触插塞。本发明的目的是提供比传统W插塞具有更低的电阻的插塞。在本发明的一些实施例中，一些新的插塞包括作为主插塞部件的钴(Co)，并且还包括具有氮化钛(TiN)和氮化硅(Si3N4)的双阻挡层，双阻挡层将Co插塞部件与附近的介电层(例如，氧化硅层)绝缘。额外地或可选地，一些新的通孔插塞包括作为主插塞部件的钌(Ru)，并且还包括作为阻挡层的TiN或氮化钽(TaN)。Co插塞和Ru插塞都比传统的W插塞提供更低的电阻。在下文中，术语“Co插塞”、“含Co插塞”、“含钴插塞”等是指包括或包含钴(Co)的插塞；并且术语“Ru插塞”、“含Ru插塞”、“含钌插塞”等是指包括或包含钌(Ru)的插塞。
图1示出了根据本发明的各个方面构建的半导体器件(或半导体结构)100的截面图。参照图1，器件100包括衬底102、有源区域104(示出一个)以及将有源区域104彼此隔离的隔离结构106。在有源区域104中或上建立各个有源和无源器件，诸如p型场效应晶体管(PFET)、n型FET(NFET)、多栅极FET(诸如FinFET)、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管、静态随机存取存储器(SRAM)单元、其它存储器单元、电阻器、电容器和电感器。
器件100还包括晶体管源极/漏极(S/D)部件108(示出一个)；包括116a和116b的晶体管栅极部件(或栅极结构或栅极堆叠件)116；栅极间隔件112和114；介电层(或层间介电层)110、120和130；含Co插塞124(包括124a和124b)和138(包括138a和138b)；含钌插塞142(示出一个)；通孔阻挡层122、132、134和140；硅化物部件118(示出一个)、导电帽136(包括136a和136b)；接触蚀刻停止层(CESL)128和导电部件126。器件100可以包括图1中未示出的各个其它部件。下面进一步描述器件100的组件。
在本实施例中，衬底102是硅衬底(例如，硅晶圆)。可选地，衬底102可以包括另一元素半导体，诸如锗；化合物半导体，包括碳化硅、氮化镓、砷化镓、磷化镓、磷化铟、砷化铟和锑化铟；合金半导体，包括硅锗，磷砷化镓、磷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟和磷砷化镓铟；或它们的组合。在实施例中，衬底102可以包括氧化铟锡(ITO)玻璃、包括绝缘体上硅(SOI)衬底(应变的和/或应力的以用于性能增强)、包括外延区域、包括掺杂区域和/或包括其它合适的部件和层。
有源区域104可以包括一个或多个半导体材料层(半导体材料诸如硅或硅锗)，并且可以掺杂有适当的掺杂剂以形成有源或无源器件。在实施例中，有源区域104包括彼此交替堆叠的多个半导体材料层，例如，具有交替堆叠的多个硅层和多个硅锗层。有源区域104可以是平面结构，例如用于形成平面晶体管(或2D晶体管)。可选地或额外地，有源区域104可以包括诸如鳍的三维(3D)结构，例如，用于形成诸如FinFET的多栅极晶体管(或3D晶体管)。可以通过任何合适的方法图案化有源区域104。例如，可以使用包括双重图案化或多重图案化工艺的一种或多种光刻工艺来图案化有源区域104。通常，双重图案化或多重图案化工艺结合光刻和自对准工艺，允许创建具有例如比使用单一直接光刻工艺可获得的间距更小的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层并且使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。之后，去除牺牲层，并且之后可以使用剩余的间隔件或芯轴作为用于图案化有源区域104的掩模元件。例如，掩模元件可以用于在衬底102上方或中的半导体层内蚀刻凹槽，而在衬底102上留下有源区域104。该蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其它合适的工艺。例如，干蚀刻工艺可以实施含氧气体、含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如，HBr和/或CHBR3)、含碘气体、其它合适的气体和/或等离子体和/或它们的组合。例如，湿蚀刻工艺可以包括在稀释的氢氟酸(DHF)；氢氧化钾(KOH)溶液；氨；包含氢氟酸(HF)、硝酸(HNO3)和/或乙酸(CH3COOH)的溶液；或其它合适的湿蚀刻剂中的蚀刻。形成有源区域104的方法的许多其它实施例可以是合适的。
隔离结构106可以包括氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其它合适的绝缘材料。在实施例中，通过在衬底102中或上方蚀刻沟槽(例如，作为形成有源区域104的工艺的一部分)，用绝缘材料填充沟槽并且对绝缘材料实施化学机械平坦化(CMP)工艺和/或回蚀刻工艺，留下剩余的绝缘材料作为隔离结构106来形成隔离结构106。诸如场氧化物和硅的局部氧化物(LOCOS)的其它类型的隔离结构也可以是合适的。隔离结构106可以包括多层结构，例如，具有位于衬底102和有源区域104的表面上的一个或多个衬垫层以及位于一个或多个衬垫层上方的主隔离层。
S/D部件108可以包括用于NFET的n型掺杂硅、用于PFET的p型掺杂硅锗或其它合适的材料。可以通过在邻近于栅极间隔件112和114的有缘区域104中蚀刻凹槽，并且在凹槽中外延生长半导体材料来形成S/D部件108。外延生长的半导体材料可以原位或非原位掺杂适当的掺杂剂。S/D部件108可以具有任何合适的形状并且可以部分地嵌入在有源区域104内，诸如图1所示。
栅极间隔件112可以包括介电材料，诸如氧化硅或氮氧化硅。栅极间隔件114可以包括介电材料，诸如氧化硅、氮化硅、氮氧化硅、碳化硅、其它介电材料或它们的组合。可以通过沉积(例如，化学汽相沉积(CVD)或物理汽相沉积(PVD))和蚀刻工艺来形成栅极间隔件112和114。
每个栅极堆叠件116(例如，116a或116b)均可以包括栅极介电层和栅电极层，并且还可以包括位于栅极介电层下方的界面层。界面层可以包括诸如SiO2或SiON的介电材料，并且可以通过化学氧化、热氧化、原子层沉积(ALD)、CVD和/或其它合适的方法来形成。栅极介电层可以包括SiO2或高k介电材料，高k介电材料诸如氧化铪硅(HfSiO)、氧化铪(HfO2)、氧化铝(Al2O3)、氧化锆(ZrO2)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)或它们的组合。可以使用CVD、PVD、ALD和/或其它合适的方法来沉积栅极介电层。栅电极层可以包括多晶硅和/或一个或多个含金属层。例如，栅电极层可以包括功函金属层、导电阻挡层和金属填充层。取决于器件的类型(PFET或NFET)，功函金属层可以是p型或n型功函层。p型功函层包括选自但不限于氮化钛铝(TiAlN)、氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)或它们的组合的组的金属。n型功函层包括选自但不限于钛(Ti)、铝(Al)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化钽硅(TaSiN)、氮化钛铝(TiAlN)、氮化钛硅(TiSiN)或它们的组合的组的金属。金属填充层可以包括铝(Al)、钨(W)、钴(Co)和/或其它合适的材料。可以使用诸如CVD、PVD、镀和/或其它合适的工艺的方法来沉积栅电极层。可以通过包括先栅极工艺和后栅极工艺的任何合适的工艺形成栅极堆叠件116。在示例性先栅极工艺中，在形成晶体管源极/漏极部件108之前，沉积并且图案化各个材料层以成为栅极堆叠件116。在示例性后栅极工艺(也称为栅极替换工艺)中，先形成临时栅极结构。之后，在形成晶体管源极/漏极部件108之后，去除并且用栅极堆叠件116替换临时栅极结构。在本实施例中，栅极堆叠件116a设置在晶体管的沟道区域上方并且用作栅极端子。器件100还可以包括设置在栅极堆叠件116a上方的含Co插塞，但是未在该截面图中示出。
介电层110、120和130也称为层间介电(ILD)层。ILD层110、120和130的每个均可以包括正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其它合适的介电材料。每个ILD层均可以通过等离子体增强CVD(PECVD)、可流动CVD(FCVD)或其它合适的方法形成。ILD层110、120和130可以具有相同或不同的材料。
在本实施例中，阻挡层122包括双阻挡层，该双阻挡层包括位于含Co插塞124(例如，124a和124b)的侧壁上的第一阻挡层以及位于第一阻挡层的侧壁上方(例如，位于第一阻挡层和ILD层120之间)的第二阻挡层。在实施例中，第一阻挡层包括氮化钛(TiN)或氮化钽(TaN)。在实施例中，第二阻挡层包括氮化硅(Si3N4)。可以通过CVD、ALD或其它合适的方法形成阻挡层122。
在实施例中，阻挡层122的厚度设计为足够大，使得来自含Co插塞124的钴元素不能扩散至附近的含氧介电层(诸如ILD层120)内。同时，阻挡层122的厚度设计为尽可能小，以为插塞124留下空间。插塞124的尺寸越大，插塞124提供的电阻越小。本发明的发明人已经发现钴元素可以在阻挡层122内扩散约1nm至约1.5nm。在示例性实施例中，阻挡层122设计为约2nm至约3nm。在进一步实施例中，阻挡层122中的两层设计为具有大致相同的厚度。
含Co插塞124a设置在S/D部件108上方并且与S/D部件108电接触。在本实施例中，插塞124a通过硅化物部件118连接至S/D部件108。在可选实施例中，插塞124a直接连接至S/D部件108而没有硅化物部件118。硅化物部件118可以通过以下工艺形成，该工艺包括：沉积金属层；退火金属层，从而使得金属层与S/D部件108中的半导体材料反应以形成硅化物，并且之后去除未反应的金属层。硅化物部件118可以包括硅化镍、硅化钛、硅化钴或其它适合的硅化物或锗硅化物。
含Co插塞124b设置在栅极堆叠件116b上方并且与栅极堆叠件116b电接触(直接或间接)。可以通过CVD、PVD、镀或其它合适的方法形成含Co插塞124(包括124a和124b)。在实施例中，插塞124和阻挡层122通过以下过程形成，该过程包括：在ILD层120中蚀刻接触孔，在接触孔中沉积阻挡层122，部分地去除阻挡层122以暴露栅极堆叠件116a和116b，可选地形成硅化物部件118，并且在接触孔内沉积含Co插塞124。
CESL 128可以包括氮化硅、氮氧化硅、具有氧(O)或碳(C)元素的氮化硅和/或其它材料；并且可以通过CVD、PVD、ALD或其它合适的方法形成。CESL 128可以包括多个层(例如，在不同时间沉积的多个介电层)。
导电部件126可以包括任何合适的导电材料。在实施例中，导电部件126提供高电阻(或低电导率)，例如作为电阻器的一部分。为了进一步该实施例，导电部件126可以包括氮化钛或其它合适的材料。在实施例中，导电部件126通过以下过程形成，该过程包括：在CESL 128的多个层的一个上方沉积导电层(例如，TiN)，在导电层上方形成介电硬掩模层，图案化介电硬掩模层和导电层，并且沉积CESL 128的另一层，从而将导电部件126(可选地图案化的硬掩模层)嵌入在CESL 128内。
在本实施例中，阻挡层132包括氮化硅(Si3N4)，阻挡层134包括氮化钛(TiN)或氮化钽(TaN)，并且导电帽136包括钨或硅化钴(CoSix，诸如CoSi、CoSi2和/或Co2Si)。可以通过ALD、CVD或其它合适的方法形成部件132、134、136和138。
在实施例中，阻挡层132和134的总厚度设计为足够大，使得来自含Co插塞138的钴元素不能扩散至附近的含氧介电层(诸如具有SiO2的ILD层130)内。同时，阻挡层132和134的总厚度设计为尽可能小，以为插塞138留下空间。插塞138的尺寸越大，它们提供的电阻越小。本发明的发明人已经发现钴元素可以在阻挡层132和134内扩散约1nm至约1.5nm。在实施例中，阻挡层132和134设计为具有大致相同的厚度，并且阻挡层132和134的总厚度为约2nm至约3nm。
在本实施例中，含Co插塞124和138中的钴晶粒被适当地设计为适合于小的导通孔并且提供低电阻。在实施例中，插塞124和138的每个中的大于60％的钴晶粒均具有约11nm至约13nm的晶粒尺寸，并且其中，其余的钴晶粒均具有小于10nm的晶粒尺寸。这种晶粒尺寸即使在小的导通孔中也能提供低电阻。含Co插塞138和124比传统的W插塞提供更低的电阻。这使得能够创建更小的电路和/或降低由器件100实现的功耗。
阻挡层140可以包括氮化钛或氮化钽，并且可以通过ALD或其它合适的方法形成。可以通过CVD或其它合适的方法形成含Ru插塞142。在本实施例中，含Ru插塞142设置在导电部件126上方并且与导电部件126电接触。例如，含Ru插塞142可以用作包括导电部件126的电阻器的一个端子。含Ru插塞142比传统W插塞提供更低的电阻。这为器件100提供了一些益处。例如，插塞142仅对包括导电部件126的电路路径的总电阻产生可忽略的电阻。因此，可以更精确地设计和制造电路路径。
在本实施例中，插塞138和142具有梯形截面轮廓，其中，它们的底部宽度小于它们相应的顶部宽度。在实施例中，它们的底部宽度大于它们相应的顶部宽度的50％，但不超过90％。这种几何设计允许插塞138和142完全填充相应的导通孔。
图2A和图2B示出了根据一些实施例的用于形成半导体器件100的方法200的流程图。方法200仅仅是实例，并且除了权利要求中的明确表述之外，方法200不旨在限制本发明。可以在方法200之前、期间和之后提供额外的操作，并且对于方法的额外的实施例，可以替换、消除或移动所描述的一些操作。下面结合图3至图12描述方法200，图3至图12示出了根据方法200的制造步骤期间的半导体器件100的各个截面图。
在操作202中，方法200(图2A)提供或提供有器件结构(工件)100，诸如图3所示。器件结构100包括衬底102；有源区域104；隔离结构106；S/D部件108；硅化物部件118；栅极堆叠件116；栅极间隔件112和114；ILD层110、120和130；含Co插塞124；阻挡层122；导电部件126；和CESL 128。以上已经参照图1描述了这些各个部件。
在操作204中，方法200(图2A)蚀刻ILD层130和CESL 128以形成导通孔127，导通孔127包括导通孔127a、127b和127c。参照图4，导通孔127a和127b分别蚀刻在含Co插塞124a和124b之上，并且至少部分地暴露含Co插塞124a和124b的相应的顶面。导通孔127c蚀刻在导电部件126之上，并且暴露导电部件126的顶面的部分。在实施例中，操作204包括光刻工艺和一次或多次蚀刻工艺。例如，操作204可以通过光刻胶涂布、曝光、曝光后烘烤和显影在器件100上方形成图案化的光刻胶。之后，操作204使用图案化的光刻胶或衍生物作为蚀刻掩模来蚀刻层128和130，以形成导通孔127。蚀刻工艺可以包括湿蚀刻、干蚀刻、反应离子蚀刻或其它合适的蚀刻方法。之后例如通过光刻胶剥离去除图案化的光刻胶。在本实施例中，控制蚀刻工艺以在导通孔127中产生梯形轮廓。具体地，每个导通孔127的底部开口宽度W1是相应的顶部开口宽度W2(沿着X方向)的至少50％，但不超过90％。这允许材料层(例如，层132、134、140、138和142)在随后的步骤中适当地填充导通孔127。如果导通孔127太直立(例如，W1大于W2的90％)，则导通孔127的下拐角可能不会被适当地填充，从而在其中留下空隙缺陷。如果导通孔127太倾斜(例如，W1小于W2的50％)，则插塞138和142中的电阻可能太高。
在操作206中，方法200(图2A)在导通孔127中沉积阻挡层132。参照图5，在本实施例中，阻挡层132沉积为覆盖导通孔127的底部和侧壁表面的基本共形层。在实施例中，阻挡层132沉积为具有约1nm至1.5nm的厚度。在本实施例中，阻挡层132包括氮化硅(Si3N4)。操作206可以使用ALD或CVD方法来沉积阻挡层132。
在操作208中，方法200(图2A)在导通孔127中沉积阻挡层134。参照图6，在本实施例中，阻挡层134沉积为位于阻挡层132上方的基本共形层。在实施例中，阻挡层134沉积为具有约1nm至1.5nm的厚度。在本实施例中，阻挡层134包括氮化钛。在可选实施例中，阻挡层134包括氮化钽。操作208可以使用ALD或CVD方法来沉积阻挡层134。在实施例中，方法200破坏操作206和208之间的真空。
在操作210中，方法200(图2A)蚀刻阻挡层134和132以去除导通孔127中的它们的底部部分。参照图7，阻挡层132和134保留在导通孔127的侧壁上，并且从导通孔127的底部去除，以暴露含Co插塞124和导电部件126。在本实施例中，操作210使用一次或多次干蚀刻工艺来蚀刻阻挡层134和132。此外，操作210可以应用湿清洁工艺，诸如SC1(标准清洁1)或SC2(标准清洁2)工艺以从插塞124和导电部件126的顶面去除任何残留物。由于导通孔127的倾斜轮廓，导通孔127的侧壁上的阻挡层134也可以从蚀刻和清洁工艺经历一些损失。在操作208中考虑了这种损失。换句话说，阻挡层134沉积(通过操作208)为具有足够的厚度，从而使得在操作210之后，阻挡层134与本实施例中的阻挡层132具有大致相同的厚度。
在一些实施例中，在操作210之后，可以轻微地氧化(来自环境空气)含Co插塞124的顶面，以包括诸如CoO、Co3O4和Co2O3的一些氧化钴化合物(CoOx)。在操作212中，方法200(图2A)对器件100实施预清洁工艺。具体地，预清洁工艺清洁插塞124的顶面并且去除其上的任何氧化。在实施例中，操作212例如在图14示出的原位集群工具300中的预清洁室304中将氢(H2)等离子体施加至器件100。例如，可以利用功率约800W至约900W功率的2MHz射频源(RF2)、功率范围在从约100W至150W的偏压的13.56MHz射频源(RF1)、利用约20sccm(标准立方厘米每分钟)至约100sccm的流率的纯H2气体和约3mtorr至约6mtorr的总压力来产生H2等离子体。在实施例中，H2气体可以与诸如氩气的一些惰性气体混合。H2等离子体有助于从含Co插塞124的表面去除任何氧化。
在操作214中，方法200(图2B)实施选择性沉积工艺以在含Co插塞124上方(而不在不含钴的导电部件126上方)沉积导电帽136。参照图8，导电帽136a和136b分别沉积在含Co插塞124a和124b上方并且分别与含Co插塞124a和124b直接接触，而导电部件126的顶面保持通过导通孔127c暴露。在实施例中，操作214可以在原位集群工具300(图14)中的沉积室316中实施，而不会在操作212之后破坏真空。在实施例中，操作214选择性地沉积钨(W)以作为导电帽136。例如，可以在约250℃至约300℃的温度、约5torr至约15torr的总压力下，并且使用WF6和H2作为反应气体来实施选择性W沉积。这种低温和低压对于操作214是期望的，因为高温和/或高压可能导致非选择性W沉积。可以将导电帽136沉积至约至约/>厚。它们的厚度可以由工艺定时器控制。在另一实施例中，操作214选择性地沉积硅化钴(CoSix)作为导电帽136。例如，操作214可以在约250℃至约500℃的温度、约5torr至约55torr的总压力下，并且使用SiH4作为反应气体来沉积硅化钴。
在操作216中，方法200(图2B)在导电帽136上(而不在导电部件126上)选择性地生长钴(Co)。参照图9，含Co插塞138a和138b分别生长在导电帽136a和136b上方，并且完全填充导通孔127a和127b。导通孔127c保持开放，其中，导电部件126的顶面通过导通孔127c暴露。在实施例中，操作216可以在原位集群工具300(图14)中的沉积室308中实施，而不会在操作214之后破坏真空。例如，可以在约150℃至约300℃的温度、约5torr至约15torr的总压力下，并且使用C5H5Co(CO)2(二羰基环戊二烯基钴)和H2作为反应气体来实施选择性Co沉积。这种低温和低压对于操作216是期望的，因为高温和/或高压可能导致非选择性Co沉积。可以将含Co插塞138沉积至约至约/>厚。它们的厚度可以由工艺定时器控制。
在操作218中，方法200(图2B)在器件100上方沉积阻挡层140。参照图10，阻挡层140在器件100的表面上(具体在导通孔127c的底部和侧壁表面上)沉积为具有基本均匀的厚度。在实施例中，阻挡层140包括使用ALD沉积的氮化钛(TiN)或氮化钽(TaN)。在实施例中，操作218可以在原位集群工具300(图14)中的沉积室312或314中实施，而不会在操作216之后破坏真空。例如，可以在约250℃至约400℃的温度、约0.5torr至约5torr的总压力下，并且使用TDMAT(四(二甲氨基)钛)(用于TiN沉积)和PDMAT(五(二甲氨基)钽)(用于TaN沉积)作为前体来实施阻挡层140的沉积。可以将阻挡层140沉积至约至约/>厚。阻挡层140的厚度可以通过ALD循环的次数来控制。
在操作220中，方法200(图2B)在器件100上方沉积含Ru层142。参照图11，含Ru层142沉积为覆盖器件100的表面并且填充导通孔127c。在实施例中，操作220例如在原位集群工具300(图14)中的沉积室310中实施CVD工艺来沉积层142而不会在操作218之后破坏真空。例如，可以在约150℃至约300℃的温度、约5torr至约15torr的总压力下，并且使用Ru3(CO)12(十二羰基三钌)和H2作为反应气体来实施层142的沉积。可以将含Ru插塞142沉积至约至约/>厚。它们的厚度可以由工艺定时器控制。
在操作222中，方法200(图2B)对器件100实施化学机械平坦化(CMP)工艺。参照图12，除了导通孔127c中的之外，通过CMP工艺去除含Ru层142和阻挡层140。含Ru层142的剩余部分成为含Ru插塞142。
在操作224中，方法200(图2B)对器件100实施进一步的处理。例如，操作224可以在ILD层130上方沉积另一蚀刻停止层(ESL)和另一ILD层，蚀刻新沉积的ESL和ILD层以形成沟槽，并且在沟槽中沉积金属(例如铜)以形成金属线。金属线被配置为互连各个通孔插塞138和142以及其它电路部件。操作224可以重复这种工艺来建立金属线的任何数量的层。
图13示出了沿着图12的A-A线的器件100的实施例的一些化学分析。参照图13，在该实施例中，插塞138主要包括Co或基本由Co组成，阻挡层134包括TiN，阻挡层132包括氮化硅(Si3N4)，并且ILD层130主要包括氧化硅(SiO2)。一些Co元素从含Co插塞138扩散至阻挡层134内。一些少量的Co元素甚至扩散至阻挡层132内。但是ILD层130基本不含Co元素，这证明了双阻挡层132和134的有效性。
图14示出了用于实施方法200的一些制造步骤的原位集群工具300，并且还示出了工艺室304的示意性放大视图。参照图14，集群工具300包括用于例如通过架空传输系统连接至其它工艺工具的输入/输出端口(例如，加载闭锁)302。集群工具300还包括各个工艺室304、306、308、310、312、314和316。例如，工艺室304和306可以被配置为实施清洁工艺，诸如操作212中的预清洁工艺；工艺室308可以被配置为实施操作216中的钴沉积；工艺室310可以被配置为实施操作220中的钌沉积；工艺室312可以被配置为实施操作218中的ALD TaN沉积；工艺室314可以被配置为实施操作218中的ALD TiN沉积；并且工艺室316可以被配置为实施操作214中的W沉积。
虽然不旨在限制，但是本发明的一个或多个实施例为半导体器件及其形成提供许多益处。例如，本发明的实施例提供了具有钴和/或钌作为主金属的超低电阻通孔插塞，并且还具有薄双阻挡层以防止Co和Ru元素扩散至附近的含氧介电层内。这种通孔插塞能够完全填充小的导通孔，满足器件按比例缩小的要求。所公开的方法的实施例可以容易地集成至现有的制造工艺中。
一方面，本发明针对一种半导体器件。该半导体器件包括位于衬底上方的有源区域；设置在有源区域上方的第一含钴部件；设置在第一含钴部件上方并且与第一含钴部件物理接触的导电帽；以及设置在导电帽上方并且与导电帽物理接触的第二含钴部件。
在实施例中，半导体器件还包括：第一阻挡层，具有氮化钛并且设置在第二含钴部件和导电帽的侧壁上方；以及第二阻挡层，具有氮化硅并且设置在第一阻挡层上方。在进一步实施例中，半导体器件包括接触蚀刻停止层，设置在第二阻挡层的侧壁的下部上方；以及层间介电层，设置在接触蚀刻停止层上方和第二阻挡层的侧壁的上部上方。在实施例中，半导体器件还包括嵌入在接触蚀刻停止层内的导电部件；以及设置在导电部件上方并且与导电部件电接触的含钌部件。在进一步实施例中，半导体器件包括位于含钌部件的侧壁上方的第三阻挡层，其中，第三阻挡层包括TaN或TiN，其中，第一和第二阻挡层进一步设置在第三阻挡层的侧壁上。
在一些实施例中，第一和第二阻挡层的总厚度大于钴元素从第二含钴部件扩散至第一和第二阻挡层内的深度。在一些实施例中，第一和第二阻挡层具有大致相同的厚度，并且第一和第二阻挡层的总厚度为约2nm至约3nm。
在一些实施例中，导电帽包括钨或硅化钴(CoSix)。在半导体器件的一些实施例中，第二含钴部件中的大于60％的钴晶粒具有约11nm至约13nm的晶粒尺寸。在进一步的一些实施例中，第二含钴部件中的其它钴晶粒具有小于10nm的晶粒尺寸。在一些实施例中，第一含钴部件电连接至晶体管源极/漏极部件或晶体管栅极部件。
另一方面，本发明针对一种半导体器件。该半导体器件包括设置在衬底上方的第一含钴插塞；设置在第一含钴插塞上方并且与第一含钴插塞物理接触的导电帽；设置在导电帽上方并且与导电帽物理接触的第二含钴插塞；位于第二含钴插塞和导电帽的侧壁上方的第一阻挡层；位于第一阻挡层的侧壁上方的第二阻挡层；以及围绕第二阻挡层的一个或多个介电层。
在实施例中，第一阻挡层包括氮化钛，第二阻挡层包括氮化硅，并且一个或多个介电层包括氧化硅。在一些实施例中，半导体器件还包括嵌入在一个或多个介电层内的氮化钛层；以及设置在氮化钛层上方并且与氮化钛层电连接的含钌插塞。在进一步实施例中，半导体器件包括围绕含钌插塞的第三阻挡层，其中，第一和第二阻挡层也设置在第三阻挡层和一个或多个介电层之间。
在又一方面，本发明针对一种方法。该方法包括提供一种结构，该结构具有衬底、位于衬底上方的一个或多个第一介电层、嵌入在一个或多个第一介电层内的第一含钴插塞以及位于一个或多个第一介电层和第一含钴插塞上方的一个或多个第二介电层。该方法还包括：在一个或多个第二介电层中蚀刻导通孔以暴露第一含钴插塞；在导通孔中沉积具有氮化硅的第一阻挡层；在导通孔中和第一阻挡层上方沉积具有氮化钛或氮化钽的第二阻挡层；蚀刻导通孔中的第一和第二阻挡层以暴露第一含钴插塞；在暴露在导通孔中的第一含钴插塞上方形成导电帽；以及在导电帽上方选择性地生长钴。
在该方法的一些实施例中，导电帽的形成包括使用WF6和H2作为反应气体在第一含钴插塞上方选择性地生长钨。在一些实施例中，选择性地生长钴使用C5H5(CO)2CO和H2作为反应气体来实施。
在一些实施例中，该方法还包括在导电帽的形成之前使用H2等离子体清洁第一含钴插塞的暴露表面。在一些实施例中，该结构还包括嵌入在一个或多个第二介电层内的导电部件，并且该方法还包括在一个或多个第二介电层中蚀刻第二导通孔以暴露导电部件；在第二导通孔中沉积第一阻挡层；在第二导通孔中沉积第二阻挡层；蚀刻第二导通孔中的第一和第二阻挡层以暴露导电部件；在第二导通孔中沉积具有氮化钽或氮化钛的第三阻挡层；以及在第二导通孔中和第三阻挡层上方沉积含钌插塞。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种半导体器件，包括：
有源区域，位于衬底上方；
第一含钴部件，设置在所述有源区域上方；
导电帽，设置在所述第一含钴部件上方并且与所述第一含钴部件物理接触；
第二含钴部件，设置在所述导电帽上方并且与所述导电帽物理接触；
第一阻挡层，设置在所述第二含钴部件和所述导电帽的侧壁上方；以及
第二阻挡层，设置在所述第一阻挡层上方，其中，所述第一阻挡层的底部和所述第二阻挡层的底部均位于所述第一含钴部件上方。
2.根据权利要求1所述的半导体器件，其中，
所述第一阻挡层具有氮化钛，并且所述第二阻挡层具有氮化硅。
3.根据权利要求2所述的半导体器件，还包括：
接触蚀刻停止层，设置在所述第二阻挡层的侧壁的下部上方；以及
层间介电层，设置在所述接触蚀刻停止层上方和所述第二阻挡层的侧壁的上部上方。
4.根据权利要求3所述的半导体器件，还包括：
导电部件，嵌入在所述接触蚀刻停止层内；以及
含钌部件，设置在所述导电部件上方并且与所述导电部件电接触。
5.根据权利要求4所述的半导体器件，还包括：
第三阻挡层，位于所述含钌部件的侧壁上方，其中，所述第三阻挡层包括TaN或TiN，其中，所述第一阻挡层和所述第二阻挡层进一步设置在所述第三阻挡层的侧壁上。
6.根据权利要求2所述的半导体器件，其中，所述第一阻挡层和所述第二阻挡层的总厚度大于钴元素从所述第二含钴部件扩散至所述第一阻挡层和所述第二阻挡层内的深度。
7.根据权利要求2所述的半导体器件，其中，所述第一阻挡层和所述第二阻挡层具有相同的厚度，并且所述第一阻挡层和所述第二阻挡层的总厚度为2nm至3nm。
8.根据权利要求1所述的半导体器件，其中，所述导电帽包括钨或硅化钴(CoSix)。
9.根据权利要求1所述的半导体器件，其中，所述第二含钴部件中的大于60％的钴晶粒具有11nm至13nm的晶粒尺寸。
10.根据权利要求9所述的半导体器件，其中，所述第二含钴部件中的其它钴晶粒具有小于10nm的晶粒尺寸。
11.根据权利要求1所述的半导体器件，其中，所述第一含钴部件电连接至晶体管源极/漏极部件或晶体管栅极部件。
12.一种半导体器件，包括：
第一含钴插塞，设置在衬底上方；
导电帽，设置在所述第一含钴插塞上方并且与所述第一含钴插塞物理接触；
第二含钴插塞，设置在所述导电帽上方并且与所述导电帽物理接触；
第一阻挡层，位于所述第二含钴插塞和所述导电帽的侧壁上方；
第二阻挡层，位于所述第一阻挡层的侧壁上方，其中，所述第一阻挡层的底部和所述第二阻挡层的底部均位于所述第一含钴插塞上方；以及
一个或多个介电层，围绕所述第二阻挡层。
13.根据权利要求12所述的半导体器件，其中，所述第一阻挡层包括氮化钛，所述第二阻挡层包括氮化硅，并且所述一个或多个介电层包括氧化硅。
14.根据权利要求12所述的半导体器件，还包括：
氮化钛层，嵌入在所述一个或多个介电层内；以及
含钌插塞，设置在所述氮化钛层上方并且与所述氮化钛层电连接。
15.根据权利要求14所述的半导体器件，还包括：
第三阻挡层，围绕所述含钌插塞，其中，所述第一阻挡层和所述第二阻挡层也设置在所述第三阻挡层和所述一个或多个介电层之间。
16.一种形成半导体器件的方法，包括：
提供一种结构，所述结构具有衬底、位于所述衬底上方的一个或多个第一介电层、嵌入在所述一个或多个第一介电层内的第一含钴插塞以及位于所述一个或多个第一介电层和所述第一含钴插塞上方的一个或多个第二介电层；
在所述一个或多个第二介电层中蚀刻导通孔以暴露所述第一含钴插塞；
在所述导通孔中沉积具有氮化硅的第一阻挡层；
在所述导通孔中和所述第一阻挡层上方沉积具有氮化钛或氮化钽的第二阻挡层；
蚀刻所述导通孔中的所述第一阻挡层和所述第二阻挡层以暴露所述第一含钴插塞；
在暴露在所述导通孔中的所述第一含钴插塞上方形成导电帽；以及
在所述导电帽上方选择性地生长钴。
17.根据权利要求16所述的方法，其中，所述导电帽的形成包括使用WF6和H2作为反应气体在所述第一含钴插塞上方选择性地生长钨。
18.根据权利要求16所述的方法，其中，所述选择性地生长钴使用C5H5(CO)2CO和H2作为反应气体来实施。
19.根据权利要求16所述的方法，还包括：
在所述导电帽的形成之前，使用H2等离子体清洁所述第一含钴插塞的暴露表面。
20.根据权利要求16所述的方法，其中，所述结构还包括嵌入在一个或多个第二介电层内的导电部件，所述方法还包括：
在所述一个或多个第二介电层中蚀刻第二导通孔以暴露所述导电部件；
在所述第二导通孔中沉积所述第一阻挡层；
在所述第二导通孔中沉积所述第二阻挡层；
蚀刻所述第二导通孔中的所述第一阻挡层和所述第二阻挡层以暴露所述导电部件；
在所述第二导通孔中沉积具有氮化钽或氮化钛的第三阻挡层；以及
在所述第二导通孔中和所述第三阻挡层上方沉积含钌插塞。
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