TWI693689B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TWI693689B
TWI693689B TW107137531A TW107137531A TWI693689B TW I693689 B TWI693689 B TW I693689B TW 107137531 A TW107137531 A TW 107137531A TW 107137531 A TW107137531 A TW 107137531A TW I693689 B TWI693689 B TW I693689B
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barrier layer
cobalt
layer
semiconductor device
conductor
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TW107137531A
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TW201935649A (zh
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程仲良
陳彥羽
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台灣積體電路製造股份有限公司
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Abstract

一種半導體裝置，包括：一主動區，在一基底的上方；一第一含鈷構件，置於該主動區的上方；一導體蓋，置於該第一含鈷構件的上方並與該第一含鈷構件有物理性的接觸；以及一第二含鈷構件，置於該導體蓋的上方並與該導體蓋有物理性的接觸。

Description

半導體裝置及其形成方法
本發明實施例是關於半導體裝置及其形成方法，特別是關於用於使積體電路的不同層之間的導體構件互連的插塞。
半導體積體電路(integrated circuit；IC)工業已歷經了指數式的成長。在積體電路的材料與設計的技術發展下，已產出數個世代的積體電路，每個世代均比其前一個世代具有較小且更複雜的電路。在積體電路革命的過程中，通常是隨著功能密度(例如：每單位晶片面積的互連的裝置數量)的增加而縮減幾何尺寸(例如：使用一製程所能形成的最小構件(或是線))。這樣的尺寸縮減的過程會藉由增加製造效率與降低關連的成本而獲得效益。這樣的尺寸縮減亦會增加所加工及製造的積體電路的複雜度。
例如，具有鈦(Ti)與氮化鈦(TiN)阻障層的鎢(W)插塞，傳統上是用來作為金屬互連結構(metal interconnect)中的介層插塞。隨著尺寸的持續縮減，介層插塞亦變得越來越小，這樣的鎢插塞會表現出較大的電阻並在一些情況會變得不穩定。因此，在這些情況需要得到改善。
本發明實施例之一是關於一種半導體裝置。上述半導體裝置包括：一主動區，在一基底的上方；一第一含鈷構件，置於上述主動區的上方；一導體蓋，置於上述第一含鈷構件的上方並與上述第一含鈷構件有物理性的接觸；以及一第二含鈷構件，置於上述導體蓋的上方並與上述導體蓋有物理性的接觸。
另一個本發明實施例是關於一種半導體裝置。上述半導體裝置包括：一第一含鈷插塞，置於一基底的上方；一導體蓋，置於上述第一含鈷插塞的上方並與上述第一含鈷插塞有物理性的接觸；一第二含鈷插塞，置於上述導體蓋的上方並與上述導體蓋有物理性的接觸；一第一阻障層，在上述第二含鈷插塞的側壁上以及上述導體蓋的側壁上；一第二阻障層，置於上述第一阻障層的側壁上；以及一或多個介電層，圍繞上述第二阻障層。
又另一個本發明實施例是關於一種半導體裝置的形成方法。上述半導體裝置的形成方法包括：提供一結構，其包括一基底、一或多個第一介電層、一第一含鈷插塞與一或多個第二介電層，上述一或多個第一介電層在上述基底的上方，上述第一含鈷插塞嵌於上述一或多個第一介電層中，上述一或多個第二介電層在上述一或多個第一介電層的上方且在上述第一含鈷插塞的上方；在上述一或多個第二介電層中蝕刻出一介層孔，以曝露上述第一含鈷插塞；將具有氮化矽的一第一阻障層沉積至上述介層孔中；將具有氮化鈦或氮化鉭的一第二阻障層沉積至上述介層孔中且沉積至上述第一阻障層上；蝕刻上述介層孔中的上述第一阻障層與上述第二阻障層，以曝露上述第一含鈷插塞；在被曝露於上述介層孔中的上述第一含鈷插塞的上方，形成一導體蓋；以及在上述導體蓋的上方選擇性地成長鈷。
要瞭解的是，以下的揭露內容提供許多不同的實施例或範例以實施本發明實施例的不同構件。以下的揭露內容敘述各個構件及其排列方式的特定實施例或範例，以簡化本發明實施例的說明。當然，這些特定的範例並非用以限定。例如，元件的尺寸並非受限於所揭露的範圍或值，但可能依存於製程條件及/或裝置所需求的性質。此外，若是本發明實施例敘述了一第一構件形成於一第二構件之上或上方，即表示其可能包括上述第一構件與上述第二構件是直接接觸的實施例，亦可能包括了有附加構件形成於上述第一構件與上述第二構件之間，而使上述第一構件與第二構件可能未直接接觸的實施例。為了簡潔，可能以任意的比例繪示各種構件。此外，本發明實施例可能會在各種實施例重複使用相同的元件符號。這樣的重複是為了敘述上的簡化與明確，而非意指所討論的不同實施例及/或結構之間的關係。
此外，其與空間相關用詞。例如「在…下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用詞，係為了便於描述圖示中一個元件或構件與另一個(些)元件或構件之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包括使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。還有，當敘述的一數值或一數值範圍連接「約」、「大約」、「大致」等詞時，除非有另外指定，這些詞的目的是為了使所連接的數值的意義包含其值的正負百分之十(±10%)的範圍。例如，「約5nm」的詞，其亦包含4.5nm至5.5nm的數值範圍。
本發明實施例是關於半導體裝置及其形成方法，特別是關於用於使積體電路的不同層之間的導體構件互連的插塞。「插塞」有時亦稱為「介層插塞」或「接觸插塞」。本發明實施例的目的之一是提供一種插塞，其具有的電阻低於傳統的鎢插塞的電阻。在本發明實施例的一些實施形態中，一些嶄新的插塞包括鈷(Co)作為主要的插塞構件，且進一步包括雙重阻障層，上述雙重阻障層包括氮化鈦(TiN)與氮化矽(Si3 N4 )，而將Co插塞構件與鄰近的介電層(例如：一或多個氧化矽層)隔離。在上述結構之外或用於取代上述結構者，一些嶄新的插塞包括釕(Ru)作為主要的插塞構件，且進一步包括氮化鈦或氮化鉭(TaN)作為一阻障層。Co插塞與Ru插塞都提供比傳統的鎢插塞的電阻還低的電阻。在後文中，「Co插塞」、「含Co插塞」、「含鈷插塞」或其同類用詞都是指包括或包含鈷(Co)的插塞；而「Ru插塞」、「含Ru插塞」、「含釕插塞」或其同類用詞都是指包括或包含釕(Ru)的插塞。
第1圖是一剖面圖，顯示根據本發明實施例的態樣建構的半導體裝置(或半導體結構)100。請參考第1圖，半導體裝置100包括一基底102、複數個主動區104(顯示一個)以及一隔離結構106，隔離結構將複數個主動區104彼此隔離。在主動區104之中或之上建構各種主動裝置或被動裝置，例如p型場效電晶體(p-type field effect transistors；PFETs)、n型場效電晶體(n-type field effect transistors；NFETs)、例如鰭式場效電晶體(Fin Field Effect Transistors；FinFETs)等的多閘極場效電晶體(multi-gate field effect transistors)、金屬－氧化物－半導體場效電晶體(metal-oxide semiconductor field effect transistors；MOSFETs)、互補式金屬－氧化物－半導體場效電晶體(complementary metal-oxide semiconductor field effect transistors；CMOSFETs)、雙極性電晶體(bipolar transistors)、高電壓電晶體(high voltage transistors)、高頻電晶體(high frequency transistors)、靜態隨機存取記憶體(static random access memory；SRAM)胞、其他記憶體胞、電阻器、電容器、電感器等。
半導體裝置100更包括複數個電晶體的源極/汲極構件108(顯示一個)；複數個閘極堆疊(電晶體的閘極構件或閘極結構)(包括116a與116b)；閘極間隔物112與114；層間介電層(介電層)110、120與130；複數個含Co插塞(包括124a與124b、138a與138b)；複數個含Ru插塞142(顯示一個)；介層阻障層122、132、134與140；複數個矽化物構件118(顯示一個)；複數個導體蓋(包括136a與136b)；一接觸蝕刻停止層(contact etch stop layer；CESL)128以及一導體構件126。半導體裝置100可包括未顯示於第1圖的各種其他構件。在後文會進一步敘述半導體裝置100的構件。
在本實施例中，基底102是矽基底(例如：矽晶圓)。矽基底之外，基底102可包括：其他的元素半導體，例如鍺；一化合物半導體，包括碳化矽、氮化鎵、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦等；一合金半導體，包括矽鍺(silicon germanium)、砷磷化鎵(gallium arsenide phosphide)、磷化鋁銦(aluminum indium phosphide)、砷化鋁鎵(aluminum gallium arsenide)、砷化鎵銦(gallium indium arsenide)、磷化鎵銦(gallium indium phosphide)、砷磷化鎵銦(gallium indium arsenide phosphide)等；或是上述之組合。在一些實施例中，基底102可包括氧化銦錫(indium tin oxide；ITO)玻璃、可包括絕緣層上覆矽(silicon on insulator；SOI)基底、可為了效能的改善而承受應變及/或應力、可包括磊晶區、可包括摻雜區及/或可包括其他適用的構件及層。
主動區104可包括一或多層的半導體材料，例如矽或矽鍺，且為了形成主動裝置或被動裝置而可摻雜有適當的摻雜物。在一實施例中，主動區104包括逐一交互堆疊的半導體材料的多層結構，例如具有交互堆疊的多層矽與多層矽鍺。例如，為了形成平面電晶體(或是二維電晶體)，主動區104可具有一平面結構。取而代之或此外，例如為了形成例如鰭式場效電晶體等的多閘極電晶體(或是三維電晶體)，主動區104可包括例如鰭狀物等的三維(3D)結構。可藉由任何適當的方法，將主動區104圖形化。例如可使用一或多道光學微影製程，將主動區104圖形化，上述光學微影製程包括雙重圖形化(double-patterning)或多重圖形化(multi-patterning)製程。一般而言，雙重圖形化或多重圖形化製程是結合了微影及自對準(self-aligned)製程，得以使所形成的圖形具有的例如節距(pitch)小於使用一單一、直接的微影製程所能另外獲得的圖形的節距。例如在一實施例中，在一基底上形成一犧牲層，並使用一微影製程將此犧牲層圖形化。使用一自對準製程，倚靠著圖形化的上述犧牲層而形成間隔物。然後，移除上述犧牲層，然後可以將留下來的間隔物或心軸(mandrels)作為一罩幕元件使用，用以將主動區104圖形化。例如，可將上述罩幕元件用來在基底102中或基底102的上方的半導體層內，蝕刻出複數個凹部，而留下基底102上的主動區104。上述蝕刻製程可包括乾蝕刻、溼蝕刻、反應性離子蝕刻(reactive ion etching；RIE)及/或其他適當的製程。例如，一乾蝕刻製程可應用一含氧氣體、一含氟氣體(例如：CF4 、SF6 、CH2 F2 、CHF3 及/或C2 F6 )、一含氯氣體(例如：Cl2 、CHCl3 , CCl4 及/或BCl3 )、一含溴氣體(例如：HBr及/或CHBr3 )、一含碘氣體、其他適當的氣體及/或電漿、及/或上述之組合。例如，一溼蝕刻製程可包括在以下的溶液中進行蝕刻：稀釋的氫氟酸(diluted hydrofluoric acid；DHF)；氫氧化鉀(KOH)溶液；氨；包括氫氟酸(HF)、硝酸(HNO3 )及/或醋酸(CH3 COOH)的溶液；或是其他適當的溼式蝕刻劑。可適用多種其他實施例的方法來形成主動區104。
隔離結構106可包括氧化矽(SiO2 )、氮化矽(Si3 N4 )、氧氮化矽(SiON)、摻氟的矽玻璃(fluoride-doped silicate glass；FSG)、一低介電常數介電材料及/或其他適當的絕緣材料。在一實施例中，隔離結構106是藉由以下步驟而形成：在基底102中或上方蝕刻出複數個溝槽(例如：作為形成主動區104的製程的一部分)；以一絕緣材料填充上述溝槽；以及對上述絕緣材料施行一化學機械研磨(chemical mechanical planarization；CMP)製程及/或一回蝕製程，以使留下來的絕緣材料成為隔離結構106。亦可適用其他形式的隔離結構，例如場氧化物(field oxide)與矽的局部氧化(LOCal Oxidation of Silicon；LOCOS)。隔離結構106可包括一多層結構，例如具有在基底102與主動區104的表面上的一或多個襯墊層(liner layers)以及在上述一或多個襯墊層的上方的一主要隔離層。
源極/汲極構件108可包括用於n型場效電晶體的n型摻雜矽、用於p型場效電晶體的p型摻雜矽鍺或其他適當的材料。源極/汲極構件108的形成可藉由以下步驟：在鄰接閘極間隔物112與114的主動區104中，蝕刻出複數個凹部；以及在上述凹部中進行半導體材料的磊晶成長。上述磊晶成長的半導體材料可以以適當的摻雜物作臨場(in-situ)或異地(ex-situ)摻雜。如第1圖所示，源極/汲極構件108可具有任何適當的形狀並可以局部地嵌入主動區104中。
閘極間隔物112可包括一介電材料，例如氧化矽或氧氮化矽。閘極間隔物114可包括一介電材料，例如氧化矽、氮化矽、氧氮化矽、碳化矽、其他介電材料或上述之組合。可藉由沉積(例如：化學氣相沉積(chemical vapor deposition；CVD)或物理氣相沉積(physical vapor deposition；PVD))與蝕刻製程來形成閘極間隔物112與114。
每個閘極堆疊(例如：閘極堆疊116a與116b)可包括一閘極介電層與一閘極層，且可以在上述閘極介電層的下方更包括一界面層。上述界面層可包括一介電材料，例如SiO2 或SiON，且可藉由化學性氧化、熱氧化、原子層沉積(atomic layer deposition；ALD)、化學氣相沉積及/或其他適當的方法來形成。上述閘極介電層可包括SiO2 或一高介電常數介電材料，例如氧化鉿矽(HfSiO)、氧化鉿(HfO2 )、氧化鋁(Al2 O3 )、氧化鋯(ZrO2 )、氧化鑭(La2 O3 )、氧化鈦(TiO2 )、氧化釔(Y2 O3 )、氧化鍶鈦(SrTiO3 )或上述之組合。上述閘極介電層可使用化學氣相沉積、物理氣相沉積、原子層沉積及/或其他適當的方法而沉積。上述閘極層可包括多晶矽及/或一或多層的含金屬層。例如，上述閘極層可包括一或多個功函數金屬層、一或多個導體阻障層以及一或多個金屬填充層。依存於裝置的形態(p型場效電晶體或n型場效電晶體)，上述功函數金屬層可以是一p型或一n型的功函數層。上述p型的功函數層包括一金屬，其選自但不限於氮化鈦鋁(TiAlN)、氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、鎢(W)、鉑(Pt)或上述之組合的族群。上述n型的功函數層包括一金屬，其選自但不限於鈦(Ti)、鋁(Al)、碳化鉭(TaC)、氮化碳化鉭(TaCN)、氮化鉭矽(TaSiN)、氮化鈦鋁(TiAlN)、氮化鈦矽(TiSiN)或上述之組合的族群。上述金屬充層可包括鋁(Al)、鎢(W)、鈷(Co)及/或其他適當的材料。上述閘極層可使用例如化學氣相沉積、物理氣相沉積、鍍膜法(plating)及/或其他適當的製程等方法來沉積。可藉由包括先閘極製程(gate-first processes)或後閘極製程(gate-last processes)等的任何適當的製程來形成上述閘極堆疊(例如：閘極堆疊116a與116b)。在一例示的先閘極製程中，沉積各種材料層並將其圖形化，以在電晶體的源極/汲極構件108形成之前變成閘極堆疊(例如：閘極堆疊116a與116b)。在一例示的後閘極製程(亦稱為一取代閘極製程)中，先形成一暫時性的閘極結構。然後，在形成電晶體的源極/汲極構件108之後，移除上述暫時性的閘極結構並以閘極堆疊(例如：閘極堆疊116a與116b)取而代之。在本實施例中，是將閘極堆疊116a置於一電晶體的一通道區的上方，並作為一閘極端點。雖然未繪示於目前的剖面圖，半導體裝置100可更包括一含Co插塞，此含Co插塞是置於閘極堆疊116a的上方。
介電層110、120與130亦被稱為層間介電層(interlayer dielectric (ILD) layer)。每個層間介電層110、120與130可包括四乙氧基矽烷(tetraethylorthosilicate；TEOS)的氧化物、非摻雜的矽玻璃(un-doped silicate glass)、例如硼磷矽玻璃(boron phosphate silicate glass；BPSG)、摻氟的矽玻璃(fluorinated silicate glass；FSG)、磷矽玻璃(phosphosilicate glass；PSG)、硼矽玻璃(borosilicate glass；BSG)等的摻雜的二氧化矽(doped silicon oxide)及/或其他適當的介電材料。每個層間介電層110、120與130可藉由電漿輔助化學氣相沉積法(plasma enhanced chemical vapor deposition；PECVD)、可流動化學氣相沉積法(flowable chemical vapor deposition；FCVD)或其他適當的方法而形成。層間介電層110、120與130可具有相同或不同的材料。
在本實施例中，介層阻障層122包括一雙重阻障層，其包括一第一阻障層與一第二阻障層。上述第一阻障層在含Co插塞(例如：含Co插塞124a與124b)的側壁上；上述第二阻障層在上述第一阻障層的側壁上，例如在上述第一阻障層與層間介電層120之間。在一實施例中，上述第一阻障層包括氮化鈦(TiN)或氮化鉭(TaN)。在一實施例中，上述第二阻障層包括氮化矽(Si3 N4 )。可藉由化學氣相沉積、原子層沉積或其他適當的方法來形成含Co插塞(例如：含Co插塞124a與124b)。
在一實施例中，設計介層阻障層122的厚度，以使其夠大而使來自含Co插塞(例如：含Co插塞124a與124b)的鈷元素不會經擴散而進入臨近的例如層間介電層120等的含氧介電層中。同時，設計介層阻障層122的厚度，以使其儘量小而留下空間給含Co插塞(例如：含Co插塞124a與124b)。含Co插塞(例如：含Co插塞124a與124b)的尺寸愈大，其可提供愈小的電阻。本案諸位發明人已發現在介層阻障層122的範圍，鈷元素可能擴散為約1nm至約1.5nm。在一例示的實施例中，將介層阻障層122的厚度設計為約2nm至約3nm。在另一實施例中，將介層阻障層122中的二層設計為具有大約相同的厚度。
含Co插塞124a是置於源極/汲極構件108的上方而且與源極/汲極構件108電性接觸。在本實施例中，含Co插塞124a是經由矽化物構件118而連接於源極/汲極構件108。在一替代性的實施例中，含Co插塞124a是直接連接於源極/汲極構件108而未藉由矽化物構件118。矽化物構件118可藉由以下的製程形成，其包括：沉積一金屬層；對此金屬層進行退火而使此金屬層與源極/汲極構件108中的半導體材料反應而形成矽化物；然後，移除未反應的金屬層。矽化物構件118可包括矽化鎳、矽化鈦、矽化鈷或其他適當的矽化物或矽鍺化合物(germano silicidation)。
含Co插塞124b是置於閘極堆疊116b的上方而且與閘極堆疊116b(直接或間接)電性接觸。含Co插塞(包括含Co插塞124a與124b)可藉由化學氣相沉積、物理氣相沉積、鍍膜法或其他適當的方法形成。在一實施例中，含Co插塞(例如：含Co插塞124a與124b)與介層阻障層122是藉由以下程序形成，其包括：在層間介電層120中蝕刻出複數個接觸孔；將介層阻障層122沉積至上述接觸孔中；局部移除介層阻障層122，以曝露閘極堆疊116a與116b；視需求形成矽化物構件118；以及將含Co插塞(例如：含Co插塞124a與124b)沉積至上述接觸孔中。
接觸蝕刻停止層128可包括氮化矽、氧氮化矽、含氧(O)元素或碳(C)元素的氮化矽及/或其他材料，且可藉由化學氣相沉積、物理氣相沉積、原子層沉積或其他適當的方法形成。接觸蝕刻停止層128可包括多層結構(例如：在不同時間沉積的多個介電層)。
導體構件126可包括任何適當的導體材料。在一實施例中，導體構件126提供高電阻(或低電導)，例如作為一電阻器的一部分。此外，在本實施例中，導體構件126可包括氮化鈦或其他適當材料。在一實施例中，是藉由以下程序來形成導體構件126，其包括：在接觸蝕刻停止層128的多層中的一層的上方形成一導體層(例如：TiN)；在上述導體層的上方形成一介電質硬罩幕層；將上述介電質硬罩幕層與上述導體層圖形化；以及沉積接觸蝕刻停止層128的多層中的另一層，藉此將導體構件126(視需求，也將上述圖形化的介電質硬罩幕層)嵌入接觸蝕刻停止層128中。
在本實施例中，介層阻障層132包括氮化矽(Si3 N4 )，介層阻障層134包括氮化鈦(TiN)或氮化鉭(TaN)，而導體蓋(例如：導體蓋136a與136b)則包括鎢或矽化鈷(CoSix ，例如CoSi、CoSi2 及/或Co2 Si)。介層阻障層132與134、導體蓋(例如：導體蓋136a與136b)及含Co插塞(例如：含Co插塞138a與138b)可藉由原子層沉積、化學氣相沉積或其他適當的方法而形成。
在一實施例中，設計介層阻障層132與134的總厚度，以使其夠大而使來自含Co插塞(例如：含Co插塞138a與138b)的鈷元素不會經擴散而進入臨近的例如具有SiO2 的層間介電層130等的含氧介電層中。同時，設計介層阻障層132與134的總厚度，以使其儘量小而留下空間給含Co插塞(例如：含Co插塞138a與138b)。含Co插塞(例如：含Co插塞138a與138b)的尺寸愈大，其可提供愈小的電阻。本案諸位發明人已發現在介層阻障層132與134的範圍，鈷元素可能擴散為約1nm至約1.5nm。在一實施例中，可將介層阻障層132與134設計為具有大約相同的厚度，且可將介層阻障層132與134的總厚度設計為約2nm至約3nm。
在本實施例中，將在含Co插塞(例如：含Co插塞124a、124b、138a與138b)中的鈷晶粒適當地設計為配合小尺寸的介層孔，以提供低電阻。在一實施例中，在每個含Co插塞(例如：含Co插塞124a、124b、138a與138b)中，其鈷晶粒中有超過百分之六十的鈷晶粒的晶粒尺寸為約11nm至約13nm、其餘的鈷晶粒的晶粒尺寸低於10nm。即使在小尺寸的介層孔中，這樣的晶粒尺寸仍提供低電阻。含Co插塞(例如：含Co插塞124a、124b、138a與138b)中的鈷晶粒所提供的電阻低於傳統的鎢插塞的電阻。這樣可以藉由半導體裝置100，使較小電路的形成成為可能及/或低耗能的實現成為可能。
介層阻障層140可包括氮化鈦或氮化鉭，且可藉由原子層沉積或其他適當的方法而形成。含Ru插塞142可藉由化學氣相沉積或其他適當的方法而形成。在本實施例中，是將含Ru插塞142置於導體構件126的上方並與導體構件126電性接觸。例如，含Ru插塞142可作為包括導體構件126的電阻器的一個端點。含Ru插塞142提供低電阻，其低於傳統的鎢插塞的電阻。這樣，對於半導體裝置100提供了一些效益。例如，對於包括導體構件126的電路路徑的總電阻，含Ru插塞142僅貢獻了可忽略的電阻。因此，可以更精確地設計並製造上述電路路徑。
在本實施例中，含Co插塞(例如：含Co插塞138a與138b)及含Ru插塞142可具有梯形的剖面輪廓，其底部寬度小於對應的頂部寬度。在一實施例中，其底部寬度大於其對應的頂部寬度的百分之五十，但是不大於其對應的頂部寬度的百分之九十。這樣的幾何形狀設計得以使含Co插塞(例如：含Co插塞138a與138b)及含Ru插塞142完全填滿對應的介層孔。
第2A與2B圖分別是一流程圖，分別顯示一方法200，用以形成根據一些實施例的半導體裝置100。方法200僅為一範例，並無用來限制明確記載於申請專利範圍的技術以外的本發明實施例的範圍。可以在方法200之前、過程中及之後提供附加的操作，此處敘述的一些操作，在可以被取代、刪除或改變順序，用於此方法的額外實施例。以下敘述的方法200與第3~12圖有關，其繪示半導體裝置100在根據方法200的製造步驟的過程中的各種剖面圖。
在操作202，如第3圖所示，方法200(第2A圖)提供一裝置結構或工件(半導體裝置100)或將裝置結構或工件(半導體裝置100)提供於方法200(第2A圖)。此裝置結構(半導體裝置100)包括：基底102；主動區104；隔離結構106；源極/汲極構件108；矽化物構件118；閘極堆疊(例如：閘極堆疊116a與116b)；閘極間隔物112與114；層間介電層110、120與130；含Co插塞(例如：含Co插塞124a與124b)；介層阻障層122；導體構件126；以及接觸蝕刻停止層128。這些不同的構件已在前文對第1圖的敘述討論。
在操作204，方法200(第2A圖)對層間介電層130及蝕刻停止層128進行蝕刻，以形成複數個介層孔，包括介層孔127a、127b與127c。請參考第4圖，介層孔127a與127b是分別在含Co插塞124a與124b的上方被蝕刻，而至少部份地曝露含Co插塞124a與124b的各自的頂表面。介層孔127c是在導體構件126的上方被蝕刻，而曝露導體構件126的頂表面的一部分。在一實施例中，操作204包括一微影製程與一或多道的蝕刻製程。例如，操作204可藉由光阻塗布、曝光、曝光後烘烤以及顯影，在半導體裝置100的上方形成一圖形化的光阻。然後，操作204使用此圖形化的光阻或一衍生物作為一蝕刻罩幕，對層間介電層130及蝕刻停止層128進行蝕刻，以形成上述介層孔(包括介層孔127a、127b與127c)。上述蝕刻製程可包括溼蝕刻、乾蝕刻、反應性離子蝕刻或其他適當的蝕刻方法。之後，例如藉由阻劑剝除(resist stripping)，將上述圖形化的光阻移除。在本實施例中，控制此蝕刻製程，以在上述介層孔(包括介層孔127a、127b與127c)中形成梯形的輪廓。特別是在每個上述介層孔(包括介層孔127a、127b與127c)中，其開口底部寬度W1是對應的開口頂部寬度W2(沿著方向X)的至少百分之五十但不大於百分之九十。這樣得以使材料層(例如：介層阻障層132、介層阻障層134、介層阻障層140、含Co插塞(例如：含Co插塞138a與138b)及含Ru插塞142)在後續的步驟中適當地填滿上述介層孔(包括介層孔127a、127b與127c)。如果上述介層孔(包括介層孔127a、127b與127c)太接近垂直(例如：W1超過W2的百分之九十)，就無法適當地填滿上述介層孔(包括介層孔127a、127b與127c)的下方的角落，而在其內留下孔隙(void)的缺陷。如果上述介層孔(包括介層孔127a、127b與127c)過於傾斜(例如：W1小於W2的百分之五十)，含Co插塞(例如：含Co插塞138a與138b)及含Ru插塞142的電阻可能會過高。
在操作206，方法200(第2A圖)將介層阻障層132沉積至上述介層孔(包括介層孔127a、127b與127c)中。請參考第5圖，在本實施例中，是將介層阻障層132沉積為覆蓋上述介層孔(包括介層孔127a、127b與127c)的底表面及側壁表面的一實質上的共形(conformal)層。在一實施例中，是將介層阻障層132沉積為具有約1nm至1.5nm的厚度。在本實施例中，介層阻障層132包括氮化矽(Si3 N4 )。操作206可使用原子層沉積或化學氣相沉積的方法來沉積介層阻障層132。
在操作208，方法200(第2A圖)將介層阻障層134沉積至上述介層孔(包括介層孔127a、127b與127c)中。請參考第6圖，在本實施例中，是將介層阻障層134沉積為在介層阻障層132上方的一實質上的共形層。在一實施例中，是將介層阻障層134沉積為具有約1nm至1.5nm的厚度。在本實施例中，介層阻障層134包括氮化鈦。在一替代性的實施例中，介層阻障層134包括氮化鉭。操作208可使用原子層沉積或化學氣相沉積的方法來沉積介層阻障層134。在一實施例中，方法200在操作206與208之間打破真空。
在操作210，方法200(第2A圖)對介層阻障層134與132進行蝕刻，以移除其在上述介層孔(包括介層孔127a、127b與127c)中的底部部分。請參考第7圖，介層阻障層132與134留在上述介層孔(包括介層孔127a、127b與127c)的側壁上，而從上述介層孔(包括介層孔127a、127b與127c)的底部移除介層阻障層132與134，以曝露含Co插塞(例如：含Co插塞124a與124b)與導體構件126。在本實施例中，操作210使用一或多道乾蝕刻製程，以對介層阻障層132與134進行蝕刻。另外，操作210可施加例如標準清潔液1(Standard Clean 1；SC1)或標準清潔液2(Standard Clean 2；SC2)等的一溼式清潔製程，以從含Co插塞(例如：含Co插塞124a與124b)的頂表面及導體構件126的頂表面移除殘留物。由於上述介層孔(包括介層孔127a、127b與127c)的傾斜的輪廓，在上述介層孔(包括介層孔127a、127b與127c)的側壁上的介層阻障層134亦可能從上述蝕刻及清潔製程受到若干損失。這些損失是列入操作208的考量。換句話說，(藉由操作208)將介層阻障層134沉積至一充足的厚度，使得在操作210之後，介層阻障層134具有的厚度大約與本實施例中的介層阻障層132的厚度相同。
在一些實施例中，在操作210之後，含Co插塞(例如：含Co插塞124a與124b)的頂表面可能會輕微地受到氧化(來自環境空氣)，而包括例如CoO、Co3 O4 、Co2 O3 等的一些鈷的氧化物(CoOx )。在操作212，方法200(第2A圖)對半導體裝置100施行了一預清潔製程。特別是，上述預清潔製程是對含Co插塞(例如：含Co插塞124a與124b)的頂表面清潔，且移除其上的任何氧化物。在一實施例中，例如在第14圖所示的臨場的整合型設備300中的一預清潔反應室304中，操作212對半導體裝置100施加氫(H2 )電漿。例如，可使用具有約800瓦至約900瓦的功率的一2MHz射頻源(RF2)、以具有約100瓦至約150瓦的範圍的功率的一13.56MHz射頻源(RF1)作為偏壓、使用流速為約20sccm (standard cubic centimeter per minute；標準立方公分/分鐘)至約100sccm的純H2 氣體以及總壓力為約3 mtorr至約6 mtorr來產生氫電漿。在一實施例中，可將例如氬等的一些惰性氣體混入上述H2 氣體。上述氫電漿有助於從含Co插塞(例如：含Co插塞124a與124b)的表面移除任何氧化物。
在操作214，方法200(第2B圖)施行一選擇性的沉積製程，以在含Co插塞(例如：含Co插塞124a與124b)的上方沉積導體蓋(例如：導體蓋136a與136b)，但未沉積於不含鈷的導體構件126的上方。請參考第8圖，分別在含Co插塞124a與124b的上方沉積導體蓋136a與136b，並使導體蓋136a與136b分別直接接觸含Co插塞124a與124b，而仍維持經由介層孔127c曝露導體構件126的頂表面的狀態。在一實施例中，可在臨場的整合型設備300中的一沉積反應室316(第14圖)中進行操作214而不在操作212之後破真空。在一實施例中，操作214選擇性地沉積鎢(W)而作為導體蓋(例如：導體蓋136a與136b)。例如可以在約250 °C至約300 °C的溫度、約5 torr至約15 torr的總壓力以及使用WF6 與H2 作為反應氣體之下，進行選擇性的鎢沉積。這樣的低溫與低壓對於操作214是理想的，因為高溫及/或高壓可能會造成非選擇性的鎢沉積。可以將導體蓋(例如：導體蓋136a與136b)沉積至約300Å至約500Å厚，其厚度可以藉由一製程計時器來控制。在另一實施例中，操作214選擇性地沉積矽化鈷(CoSix )作為導體蓋(例如：導體蓋136a與136b)。例如，操作214可以在約250°C至約500°C的溫度、約5 torr至約55 torr的總壓力以及使用SiH4 作為反應氣體之下，沉積矽化鈷。
在操作216，方法200(第2B圖)選擇性地在導體蓋(例如：導體蓋136a與136b)上成長鈷(Co)，但未在導體構件126上成長鈷。請參考第9圖，分別在導體蓋136a與136b的上方成長含Co插塞138a與138b，並完全填滿介層孔127a與127b。介層孔127c仍維持開放的狀態，經由介層孔127c曝露導體構件126的頂表面。在一實施例中，可在臨場的整合型設備300中的一沉積反應室308(第14圖)中進行操作216而不在操作214之後破真空。例如可以在約150 °C至約300 °C的溫度、約5 torr至約15 torr的總壓力以及使用C5 H5 Co(CO)2 (環戊雙烯二羰基鈷；Cyclopentadienylcobalt dicarbonyl)與H2 作為反應氣體之下，進行選擇性的鈷沉積。這樣的低溫與低壓對於操作216是理想的，因為高溫及/或高壓可能會造成非選擇性的鈷沉積。可以將含Co插塞(例如：含Co插塞138a與138b)沉積至約300Å至約1500Å厚，其厚度可以藉由一製程計時器來控制。
在操作218，方法200(第2B圖)是在半導體裝置100的上方沉積一介層阻障層140。請參考第10圖，是將介層阻障層140沉積為在半導體裝置100的表面上具有實質上均勻的厚度，特別是在介層孔127c的底面及側面上。在一實施例中，介層阻障層140包括使用原子層沉積的氮化鈦(TiN)或氮化鉭(TaN)。在一實施例中，可在臨場的整合型設備300(第14圖)中的一沉積反應室312或314中進行操作218而不在操作216之後破真空。例如可以在約250°C至約400°C的溫度、約0.5 torr至約5 torr的總壓力以及使用四（二甲胺基）鈦(Tetrakis(dimethylamido)titanium；TDMAT)(用於沉積TiN)或五（二甲胺基）鉭(Pentakis(dimethylamido) tantalum；PDMAT)(用於沉積TaN)作為前驅物(precursor)之下，進行介層阻障層140的沉積。可以將介層阻障層140沉積至約10Å至約20Å厚。介層阻障層140的厚度可以藉由原子層沉積的周期數量來控制。
在操作220，方法200(第2B圖)是在半導體裝置100的上方沉積一含Ru層142。請參考第11圖，是將含Ru層142沉積為覆蓋半導體裝置100的表面並填滿介層孔127c。在一實施例中，操作220施行一化學氣相沉積製程以沉積含Ru層142，例如在臨場的整合型設備300(第14圖)中的一沉積反應室310而不在操作218之後破真空。例如可以在約150°C至約300°C的溫度、約5 torr至約15 torr的總壓力以及使用Ru3 (CO)12 (十二羰基三釕；Triruthenium dodecacarbonyl)與H2 作為反應氣體之下，進行含Ru層142的沉積。可以將含Ru層142沉積至約300Å至約1500Å厚，其厚度可以藉由一製程計時器來控制。
在操作222，方法200(第2B圖)對半導體裝置100進行一化學機械平坦化(chemical mechanical planarization；CMP)製程。請參考第12圖，藉由上述化學機械平坦化製程移除在介層孔127c的內部以外的含Ru層142與介層阻障層140。含Ru層142的流下來的部分即成為含Ru插塞142。
在操作224，方法200(第2B圖)對半導體裝置100進行進一步的加工。例如，操作224可以在層間介電層130的上方沉積另一個蝕刻停止層(etch stop layer；ESL)與另一個層間介電層；蝕刻新沉積的蝕刻停止層與層間介電層以形成複數個溝槽；以及在上述溝槽內沉積金屬(例如：銅)以形成複數個金屬線。上述金屬線是用來使不同的含Co插塞(例如：含Co插塞138a與138b)與含Ru插塞142互連，並使其他的電路構件互連。操作224可重複這樣的製程，以建立任何數量的層數的金屬線。
第13圖顯示沿著第12圖的A—A線的半導體裝置100的一實施例的一些化學分析。請參考第13圖，在本實施例中：含Co插塞138(例如：上述含Co插塞138a與138b)基本上包括鈷或基本上由鈷組成；介層阻障層134包括TiN；介層阻障層132包括氮化矽(Si3 N4 )；以及層間介電層130基本上包括氧化矽(SiO2 )。有些鈷元素會從含Co插塞138(例如：上述含Co插塞138a與138b)擴散至介層阻障層134中。有些少量的鈷元素甚至會擴散至介層阻障層132中。然而，層間介電層130是實質上不含鈷元素，而證明了雙重介層阻障層132與134的功效。
第14圖顯示一臨場的整合型設備300，其可用於施行方法200的一些製造步驟，並進一步繪示預清潔反應室304的示意性的爆炸圖。請參考第14圖，臨場的整合型設備300包括輸入/輸出埠(例如：裝卸平台)302，用以例如經由一頭頂搬運系統(overhead transport system)而連接至其他的製程設備。臨場的整合型設備300還包括各種的製程反應室(元件符號為304、306、308、310、312、314與316者)。例如：預清潔反應室304與306可用來進行清潔製程，例如在操作212中的預清潔製程；沉積反應室308可用來進行操作216中的鈷沉積；沉積反應室310可用來進行操作2220中的釕沉積；沉積反應室312可用來進行操作218中的原子層沉積的TaN沉積；沉積反應室314可用來進行操作218中的原子層沉積的TiN沉積；以及沉積反應室316可用來進行操作214中的鎢沉積。
以下敘述並無作任何限制的意圖。本發明實施例的一或多個實施形態對於一半導體裝置及其形成方法提供了許多效益。例如，本發明實施例的實施形態提供了極低電阻的介層插塞，上述介層插塞具有鈷及/或釕作為主要金屬，且還具有薄層的雙重阻障層，以避免鈷與釕擴散至鄰近的含氧介電層。這樣的介層插塞可以完全填滿小尺寸的介層孔，而達成持續的裝置的尺寸縮減的需求。所揭露的方法的實施例可以被平順地整合至現行的製程。
在一態樣中，本發明實施例是關於一種半導體裝置。上述半導體裝置包括：一主動區，在一基底的上方；一第一含鈷構件，置於上述主動區的上方；一導體蓋，置於上述第一含鈷構件的上方並與上述第一含鈷構件有物理性的接觸；以及一第二含鈷構件，置於上述導體蓋的上方並與上述導體蓋有物理性的接觸。
在一實施例中，上述半導體裝置，更包括：具有氮化鈦的一第一阻障層，置於上述第二含鈷構件的側壁上以及上述導體蓋的側壁上；以及具有氮化矽的一第二阻障層，置於上述第一阻障層上。在另一實施例中，上述半導體裝置，更包括：一接觸蝕刻停止層，置於上述第二阻障層的側壁的下部的上方；以及一層間介電層，置於上述接觸蝕刻停止層的上方且置於上述第二阻障層的側壁的上部上。在一實施例中，上述半導體裝置，更包括：一導體構件，嵌於上述接觸蝕刻停止層中；以及一含釕構件，置於上述導體構件的上方並與上述導體構件有電性的接觸。在另一實施例中，上述半導體裝置，更包括：一第三阻障層，置於上述含釕構件的側壁上，其中上述第三阻障層包括TaN或TiN，上述第一阻障層與上述第二阻障層進一步置於上述第三阻障層的側壁上。
在一些實施例中，上述第一阻障層與上述第二阻障層的總厚度大於鈷元素從上述第二含鈷構件擴散至上述第一阻障層與上述第二阻障層的擴散深度。在一些實施例中，上述第一阻障層與上述第二阻障層具有大約相同的厚度，且上述第一阻障層與上述第二阻障層的總厚度為約2nm至約3nm。
在一些實施例中，上述導體蓋包括鎢或矽化鈷(CoSix )。在一些實施例中，上述第二含鈷構件中的鈷晶粒的超過百分之六十的晶粒尺寸(grain size)為約11nm至約13nm。在一些實施例中，上述第二含鈷構件中的其他鈷晶粒的晶粒尺寸小於10nm。在一些實施例中，上述第一含鈷構件是電性連接於一電晶體的源極/汲極構件或一電晶體的閘極構件。
在另一態樣中，本發明實施例是關於一種半導體裝置。上述半導體裝置包括：一第一含鈷插塞，置於一基底的上方；一導體蓋，置於上述第一含鈷插塞的上方並與上述第一含鈷插塞有物理性的接觸；一第二含鈷插塞，置於上述導體蓋的上方並與上述導體蓋有物理性的接觸；一第一阻障層，在上述第二含鈷插塞的側壁上以及上述導體蓋的側壁上；一第二阻障層，置於上述第一阻障層的側壁上；以及一或多個介電層，圍繞上述第二阻障層。
在一實施例中，上述第一阻障層包括氮化鈦，上述第二阻障層包括氮化矽，且上述一或多個介電層包括氧化矽。在一些實施例中，上述半導體裝置，更包括：一氮化鈦層，嵌於上述一或多個介電層中；以及一含釕插塞，置於上述氮化鈦層的上方並與上述氮化鈦層有電性的接觸。在另一實施例中，上述半導體裝置，更包括：一第三阻障層，圍繞上述含釕插塞，其中上述第一阻障層與上述第二阻障層亦置於上述第三阻障層與上述一或多個介電層之間。
在又另一態樣中，本發明實施例是關於一種半導體裝置的形成方法。上述半導體裝置的形成方法包括：提供一結構，其包括一基底、一或多個第一介電層、一第一含鈷插塞與一或多個第二介電層，上述一或多個第一介電層在上述基底的上方，上述第一含鈷插塞嵌於上述一或多個第一介電層中，上述一或多個第二介電層在上述一或多個第一介電層的上方且在上述第一含鈷插塞的上方；在上述一或多個第二介電層中蝕刻出一介層孔，以曝露上述第一含鈷插塞；將具有氮化矽的一第一阻障層沉積至上述介層孔中；將具有氮化鈦或氮化鉭的一第二阻障層沉積至上述介層孔中且沉積至上述第一阻障層上；蝕刻上述介層孔中的上述第一阻障層與上述第二阻障層，以曝露上述第一含鈷插塞；在被曝露於上述介層孔中的上述第一含鈷插塞的上方，形成一導體蓋；以及在上述導體蓋的上方選擇性地成長鈷。
在一些實施例中，上述導體蓋的形成包括：使用WF6 與H2 作為反應氣體，在上述第一含鈷插塞的上方選擇性地成長鎢。在一些實施例中，鈷的選擇性成長是使用C5 H5 (CO)2 Co與H2 作為反應氣體而進行。
在一些實施例中，上述半導體裝置的形成方法，更包括：在形成上述導體蓋之前，使用H2 電漿對上述第一含鈷插塞的曝露的表面進行清潔。在一些實施例中，上述結構更包括一導體構件，上述導體構件嵌於上述一或多個第二介電層中；而且上述半導體裝置的形成方法更包括：在上述一或多個第二介電層中蝕刻出一第二介層孔，以曝露上述導體構件；在上述第二介層孔中沉積上述第一阻障層；在上述第二介層孔中沉積上述第二阻障層；蝕刻上述第二介層孔中的上述第一阻障層與上述第二阻障層，以曝露上述導體構件；在上述第二介層孔中沉積一第三阻障層，上述第三阻障層包括氮化鉭或氮化鈦；以及在上述第二介層孔中且在上述第三阻障層的上方，沉積一含釕插塞。
前述內文概述了許多實施例的特徵，使所屬技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。所屬技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。所屬技術領域中具有通常知識者也應了解這些均等的結構並未背離本發明實施例的發明精神與範圍。在不背離本發明實施例的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
100‧‧‧半導體裝置 102‧‧‧基底 104‧‧‧主動區 106‧‧‧隔離結構 108‧‧‧電晶體的源極/汲極構件 110、120、130‧‧‧層間介電層 112、114‧‧‧閘極間隔物 116a、116b‧‧‧閘極堆疊 118‧‧‧矽化物構件 122、132、134、140‧‧‧介層阻障層 124a、124b、138、138a、138b‧‧‧含Co插塞 126‧‧‧導體構件 127a、127b、127c‧‧‧介層孔 128‧‧‧接觸蝕刻停止層 136a、136b‧‧‧導體蓋 142‧‧‧含Ru插塞(含Ru層) 200‧‧‧方法 202、204、206、208、210、212、214、216、218、220、222、224‧‧‧操作 300‧‧‧臨場的整合型設備 302‧‧‧輸入/輸出埠 304、306‧‧‧預清潔反應室 308、310、312、314、316‧‧‧沉積反應室
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。 第1圖是一剖面圖，顯示根據本發明實施例的態樣建構的半導體結構。 第2A圖是一流程圖，顯示如第1圖所示的根據本發明實施例的半導體結構的形成方法。 第2B圖是一流程圖，顯示如第1圖所示的根據本發明實施例的半導體結構的形成方法。 第3圖是一剖面圖，顯示關於一些實施例而根據第2A~2B圖所示的方法的製造步驟的過程中的半導體結構。 第4圖是一剖面圖，顯示關於一些實施例而根據第2A~2B圖所示的方法的製造步驟的過程中的半導體結構。 第5圖是一剖面圖，顯示關於一些實施例而根據第2A~2B圖所示的方法的製造步驟的過程中的半導體結構。 第6圖是一剖面圖，顯示關於一些實施例而根據第2A~2B圖所示的方法的製造步驟的過程中的半導體結構。 第7圖是一剖面圖，顯示關於一些實施例而根據第2A~2B圖所示的方法的製造步驟的過程中的半導體結構。 第8圖是一剖面圖，顯示關於一些實施例而根據第2A~2B圖所示的方法的製造步驟的過程中的半導體結構。 第9圖是一剖面圖，顯示關於一些實施例而根據第2A~2B圖所示的方法的製造步驟的過程中的半導體結構。 第10圖是一剖面圖，顯示關於一些實施例而根據第2A~2B圖所示的方法的製造步驟的過程中的半導體結構。 第11圖是一剖面圖，顯示關於一些實施例而根據第2A~2B圖所示的方法的製造步驟的過程中的半導體結構。 第12圖是一剖面圖，顯示關於一些實施例而根據第2A~2B圖所示的方法的製造步驟的過程中的半導體結構。 第13圖是顯示根據本發明實施例的態樣建構的半導體結構的一部分中的元素分析。 第14圖顯示一臨場的(in-situ)整合型設備(cluster tool)，其可用於施行關於一些實施例而根據第2A~2B圖所示的方法的一些製造步驟。
100‧‧‧半導體裝置
102‧‧‧基底
104‧‧‧主動區
106‧‧‧隔離結構
108‧‧‧電晶體的源極/汲極構件
110、120、130‧‧‧層間介電層
112、114‧‧‧閘極間隔物
116a、116b‧‧‧閘極堆疊
118‧‧‧矽化物構件
122、132、134、140‧‧‧介層阻障層
124a、124b、138a、138b‧‧‧含Co插塞
126‧‧‧導體構件
128‧‧‧接觸蝕刻停止層
136a、136b‧‧‧導體蓋
142‧‧‧含Ru插塞(含Ru層)

Claims (15)

  1. 一種半導體裝置，包括：一主動區，在一基底的上方；一第一含鈷構件，置於該主動區的上方；一導體蓋，置於該第一含鈷構件的上方；一第二含鈷構件，置於該導體蓋的上方；一第一阻障層，置於該第二含鈷構件的側壁上以及該導體蓋的側壁上；以及一第二阻障層，置於該第一阻障層上。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一阻障層具有氮化鈦，且該第二阻障層具有氮化矽。
  3. 如申請專利範圍第2項所述之半導體裝置，更包括：一接觸蝕刻停止層，置於該第二阻障層的側壁的下部的上方；以及一層間介電層，置於該接觸蝕刻停止層的上方且置於該第二阻障層的側壁的上部上。
  4. 如申請專利範圍第3項所述之半導體裝置，更包括：一導體構件，嵌於該接觸蝕刻停止層中；以及一含釕構件，置於該導體構件的上方並與該導體構件有電性的接觸。
  5. 如申請專利範圍第4項所述之半導體裝置，更包括：一第三阻障層，置於該含釕構件的側壁上，其中該第三阻障層包括TaN或TiN，該第一阻障層與該第二阻障層進一步置於該第三阻障層的側壁上。
  6. 如申請專利範圍第1至5項任一項所述之半導體裝置，其中該第二含鈷構件中超過百分之六十的鈷晶粒的晶粒尺寸(grain size)為約11nm至約13nm，該第二含鈷構件中的其他鈷晶粒的晶粒尺寸小於10nm。
  7. 一種半導體裝置，包括：一第一含鈷插塞，置於一基底的上方；一導體蓋，置於該第一含鈷插塞的上方並與該第一含鈷插塞有物理性的接觸；一第二含鈷插塞，置於該導體蓋的上方並與該導體蓋有物理性的接觸；一第一阻障層，在該第二含鈷插塞的側壁上以及該導體蓋的側壁上；一第二阻障層，置於該第一阻障層的側壁上；以及一或多個介電層，圍繞該第二阻障層。
  8. 如申請專利範圍第7項所述之半導體裝置，其中該第一阻障層包括氮化鈦，該第二阻障層包括氮化矽，且上述一或多個介電層包括氧化矽。
  9. 如申請專利範圍第7或8項所述之半導體裝置，更包括：一氮化鈦層，嵌於上述一或多個介電層中；以及一含釕插塞，置於該氮化鈦層的上方並與該氮化鈦層有電性的接觸。
  10. 如申請專利範圍第9項所述之半導體裝置，更包括：一第三阻障層，圍繞該含釕插塞，其中該第一阻障層與該第二阻障層亦置於該第三阻障層與上述一或多個介電層之間。
  11. 一種半導體裝置的形成方法，包括：提供一結構，其包括一基底、一或多個第一介電層、一第一含鈷插塞與一或多個第二介電層，上述一或多個第一介電層在該基底的上方，該第一含鈷插塞嵌於上述一或多個第一介電層中，上述一或多個第二介電層在上述一或多個第一介電層的上方且在該第一含鈷插塞的上方；在上述一或多個第二介電層中蝕刻出一介層孔，以曝露該第一含鈷插塞；將具有氮化矽的一第一阻障層沉積至該介層孔中；將具有氮化鈦或氮化鉭的一第二阻障層沉積至該介層孔中且沉積至該第一 阻障層上；蝕刻該介層孔中的該第一阻障層與該第二阻障層，以曝露該第一含鈷插塞；在被曝露於該介層孔中的該第一含鈷插塞的上方，形成一導體蓋；以及在該導體蓋的上方選擇性地成長鈷。
  12. 如申請專利範圍第11項所述之半導體裝置的形成方法，其中該導體蓋的形成包括：使用WF6與H2作為反應氣體，在該第一含鈷插塞的上方選擇性地成長鎢。
  13. 如申請專利範圍第11項所述之半導體裝置的形成方法，其中鈷的選擇性成長是使用C5H5(CO)2Co與H2作為反應氣體而進行。
  14. 如申請專利範圍第11項所述之半導體裝置的形成方法，更包括：在形成該導體蓋之前，使用H2電漿對該第一含鈷插塞的曝露的表面進行清潔。
  15. 如申請專利範圍第11至14項任一項所述之半導體裝置的形成方法，其中該結構更包括一導體構件，該導體構件嵌於上述一或多個第二介電層中，該半導體裝置的形成方法更包括：在上述一或多個第二介電層中蝕刻出一第二介層孔，以曝露該導體構件；在該第二介層孔中沉積該第一阻障層；在該第二介層孔中沉積該第二阻障層；蝕刻該第二介層孔中的該第一阻障層與該第二阻障層，以曝露該導體構件；在該第二介層孔中沉積一第三阻障層，該第三阻障層包括氮化鉭或氮化鈦；以及在該第二介層孔中且在該第三阻障層的上方，沉積一含釕插塞。
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