TW202201543A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TW202201543A
TW202201543A TW110123313A TW110123313A TW202201543A TW 202201543 A TW202201543 A TW 202201543A TW 110123313 A TW110123313 A TW 110123313A TW 110123313 A TW110123313 A TW 110123313A TW 202201543 A TW202201543 A TW 202201543A
Authority
TW
Taiwan
Prior art keywords
source
fin
layer
dummy
dielectric layer
Prior art date
Application number
TW110123313A
Other languages
English (en)
Inventor
耿文駿
徐國修
楊智銓
洪連嶸
王屏薇
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202201543A publication Critical patent/TW202201543A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02603—Nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本發明的半導體裝置包括第一源極/汲極結構；第二源極/汲極結構；第三源極/汲極結構；第一虛置鰭狀物，沿著方向位於第一源極/汲極結構與第二源極/汲極結構之間，以隔離第一源極/汲極結構與第二源極/汲極結構；以及第二虛置鰭狀物，沿著方向位於第二源極/汲極結構與第三源極/汲極結構之間，以隔離第二源極/汲極結構與第三源極/汲極結構。第一虛置鰭狀物包括外側介電層、內側介電層位於外側介電層上、與第一蓋層位於外側介電層與內側介電層上。第二虛置鰭狀物包括底部與第二蓋層位於底部上。

Description

半導體裝置
本發明實施例一般關於源極/汲極分隔結構與其製作方法，更特別關於形成不同的虛置鰭狀物以達主動區之間的不同空間以減少尺寸或改善效能。
半導體積體電路產業已經歷指數成長。積體電路材料與設計的技術進展，使每一代的積體電路比前一代具有更小且更複雜的電路。在積體電路演進中，功能密度(比如單位晶片面積的內連線裝置數目)通常隨著幾何尺寸(比如採用的製作製程所能產生的最小構件或線路)縮小而增加。尺寸縮小的製程有利於增加產能並降低相關成本。尺寸縮小亦會增加處理與製造積體電路的複雜度。
舉例來說，由於積體電路技術朝更小的技術節點進展，已導入多閘極裝置以增加閘極-通道耦合、減少關閉狀態電流、與減少短通道效應，進而改善閘極控制。多閘極裝置通常視作閘極結構或其部分位於通道區的多側上的裝置。鰭狀場效電晶體與多橋狀通道電晶體為多閘極裝置的例子，其為高效能與漏電流應用的有力候選。鰭狀場效電晶體具有隆起的通道，而閘極包覆通道的多側(比如包覆自基板延伸的半導體材料鰭狀物的頂部與側壁)。多橋狀通道電晶體的閘極結構可部分或完全延伸於通道區周圍，以由兩側或更多側接觸通道區。由於閘極結構圍繞通道區，多橋狀通道電晶體亦可視作圍繞閘極電晶體或全繞式閘極電晶體。可由奈米線、奈米片、或其他奈米結構形成多橋狀通道電晶體的通道區，因此多橋狀通道電晶體亦可視作奈米線電晶體或奈米片電晶體。
積體電路裝置可包含重複的物理設計區塊，其可視作標準單元。這些標準單元可包含邏輯門如NAND、NOR、XNOR、XOR、AND、OR、或逆變器的標準單元，或記憶體位元如靜態隨機存取記憶體單元。達到較小幾何尺寸的方法之一為減少標準單元的尺寸。由於標準單元重複多次，標準單元的尺寸縮小可轉換成實質的尺寸縮小。標準單元可包含交錯的多個主動區(如多個鰭狀結構或橋狀通道組件的多個堆疊)與多個虛置鰭狀物，而虛置鰭狀物用於隔離相鄰裝置的源極/汲極結構。虛置鰭狀物會增加空間，且在縮小標準單元尺寸時造成挑戰。雖然現有的虛置鰭狀物與其形成方法通常適用於其發展目的，但無法符合所有方面的需求。
本發明一例示性的實施例關於半導體裝置。半導體裝置包括第一源極/汲極結構；第二源極/汲極結構；第三源極/汲極結構；第一虛置鰭狀物，沿著方向位於第一源極/汲極結構與第二源極/汲極結構之間，以隔離第一源極/汲極結構與第二源極/汲極結構；以及第二虛置鰭狀物，沿著方向位於第二源極/汲極結構與第三源極/汲極結構之間，以隔離第二源極/汲極結構與第三源極/汲極結構。第一虛置鰭狀物包括外側介電層、內側介電層位於外側介電層上、與第一蓋層位於外側介電層與內側介電層上，第二虛置鰭狀物包括底部與第二蓋層位於底部上。
本發明另一實施例關於靜態隨機存取記憶體單元。靜態隨機存取記憶體單元包括下拉電晶體，包括第一源極/汲極結構；上拉電晶體，包括第二源極/汲極結構；第一虛置鰭狀物，沿著方向分隔下拉電晶體與上拉電晶體；以及第二虛置鰭狀物，與第二源極/汲極結構相鄰。上拉電晶體沿著方向位於第一虛置鰭狀物與第二虛置鰭狀物之間。第一虛置鰭狀物包括外側介電層、內側介電層位於外側介電層上、與第一蓋層位於外側介電層與內側介電層上。第二虛置鰭狀物包括底部與第二蓋層位於底部上。
本發明又一實施例關於半導體裝置的形成方法。方法包括接收工件，其包括:第一鰭狀結構，其長度方向沿著第一方向延伸，並具有第一基底部分與第一堆疊部分位於第一基底部分上；第二鰭狀結構，其長度方向沿著第一方向延伸，並具有第二基底部分與第二堆疊部分位於第二基底部分上，其中第一鰭狀結構與第二鰭狀結構隔有第一空間，以及第三鰭狀結構，其長度方向沿著第一方向延伸，並具有第三基底部分與第三堆疊部分位於第三基底部分上，其中第二鰭狀結構與第三鰭狀結構隔有第二空間，且第二空間小於第一空間。方法更包括形成隔離結構於第一基底部分與第二基底部分之間，以及第二基底部分與第三基底部分之間；順應性地沉積第一介電層於第一堆疊部分、第二堆疊部分、第三堆疊部分、與隔離結構上；沉積第二介電層於第一介電層上；平坦化工件以形成第一虛置鰭狀物於第一堆疊部分與第二堆疊部分之間，並形成第二虛置鰭狀物於第二堆疊部分與第三堆疊部分之間；回蝕刻第一虛置鰭狀物與第二虛置鰭狀物；選擇性回蝕刻第二虛置鰭狀物；在選擇性回蝕刻之後，沉積第三介電層於工件上；使第一堆疊部分、第二堆疊部分、與第三堆疊部分凹陷；以及形成第一源極/汲極結構於第一基底部分上、形成第二源極/汲極結構於第二基底部分上、並形成第三源極/汲極結構於第三基底部分上。
下述詳細描述可搭配圖式說明，以利理解本發明的各方面。值得注意的是，各種結構僅用於說明目的而未按比例繪製，如本業常態。實際上為了清楚說明，可任意增加或減少各種結構的尺寸。
下述內容提供的不同實施例或例子可實施本發明實施例的不同結構。特定構件與排列的實施例係用以簡化本揭露而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明之多種實例可重複採用相同標號以求簡潔，但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「下側」、「上方」、「上側」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。設備亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。此外，當數值或數值範圍的描述有「約」、「近似」、或類似用語時，除非特別說明否則其包含所述數值的+/-10%。舉例來說，用語「約5 nm」包含的尺寸範圍為4.5 nm至5.5 nm。
如上所述，多橋狀通道電晶體亦可視作圍繞閘極電晶體、全繞式閘極電晶體、奈米片電晶體、或奈米線電晶體，且其可為n型或p型。標準單元可包含多個多橋狀通道電晶體，其可自鰭狀結構形成。每一鰭狀結構包括交錯的多個通道層與多個犧牲層。在一些習知技術中，鰭狀結構彼此平行且間隔相同，而虛置鰭狀物插置於鰭狀結構之間。虛置鰭狀物用於分隔相鄰裝置的源極/汲極結構。當鰭狀結構的間隔不同，虛置鰭狀物寬度的變化與蝕刻負載可能造成虛置鰭狀物的高度與結構不一致，導致源極/汲極結構合併與裝置失效。
本發明實施例提供不同寬度與結構的不同虛置鰭狀物所用的形成製程。這些不同虛置鰭狀物可包含第一虛置鰭狀物，與比第一虛置鰭狀物狹窄的第二虛置鰭狀物。由於寬度差異，第一虛置鰭狀物與第二虛置鰭狀物可具有不同結構，且回蝕刻製程中可不同地蝕刻第一虛置鰭狀物與第二虛置鰭狀物。本發明實施例提供的製程可確保第一虛置鰭狀物與第二虛置鰭狀物的高度一致，並完全分隔相鄰的源極/汲極結構。本發明實施例的製程與結構可減少標準單元尺寸或改善標準單元效能。
本發明的多種實施例將搭配圖式詳述。圖1係本發明一或多個實施例中，自工件形成半導體裝置的方法之流程圖。方法100僅用於舉例，而非侷限本發明實施例至方法100實際記載處。可在方法100之前、之中、與之後提供額外步驟，且方法的額外實施例可置換、省略、或調換一些步驟。此處不詳述所有步驟以簡化說明。方法100將搭配圖2至12說明如下，而圖2至12係依據方法100的實施例之不同製作階段的工件之部分剖視圖。
如圖1及2所示，方法100的步驟102接收工件200。由於自工件200形成半導體裝置，工件200亦可依說明需要而視作半導體裝置。如圖2所示，工件200包括基板202，與位於基板202上的堆疊204。在一實施例中，基板202可為矽基板。在一些其他實施例中，基板202可包含其他半導體，比如鍺、矽鍺、或III-V族半導體材料。III-V族半導體材料可包含砷化鎵、磷化銦、磷化鎵、氮化鎵、磷砷化鎵、砷化鋁銦、砷化鋁鎵、磷化鎵銦、或砷化鎵銦。基板202亦可包含絕緣層如氧化矽層，以具有絕緣層上矽結構或絕緣層上鍺結構。在一些實施例中，基板202可包含一或多個井區(比如摻雜n型摻質如磷或砷的n型井區，或摻雜p型摻質如硼的p型井區)，以形成不同型的裝置。n型井與p型井的摻雜方法可採用離子佈植或熱擴散。
如圖2所示，堆疊204可包含交錯的多個通道層208與多個犧牲層206。通道層208與犧牲層206可具有不同的半導體組成。在一些實施方式中，通道層208的組成為矽，而犧牲層206的組成為矽鍺。在這些實施方式中，犧牲層206中的額外鍺含量使犧牲層206可選擇性凹陷或移除，而不實質損傷通道層208。在一些實施例中，犧牲層206與通道層208的沉積方法可採用磊晶製程。磊晶成長堆疊204的方法可採用化學氣相沉積技術(如氣相磊晶及/或超高真空化學氣相沉積)、分子束磊晶、及/或其他合適製程。可依序交錯沉積犧牲層206與通道層208以形成堆疊204。值得注意的是，圖2所示之四個犧牲層206與三個通道層208交錯地垂直配置，僅用於說明目的而非侷限本發明實施例至請求項未實際記載處。層狀物的數目取決於半導體裝置如工件200所用的通道組件之所需數目。在一些實施例中，通道層208的數目介於2至10之間。為了圖案化的目的，工件200亦可包含硬遮罩層210位於堆疊204上。硬遮罩層210可為單層或多層。在一例中，硬遮罩層210包括氧化矽層與氮化矽層。
如圖1及3所示，方法100的步驟104形成第一鰭狀結構212-1、第二鰭狀結構212-2、第三鰭狀結構212-3、第四鰭狀結構212-4、與第五鰭狀結構212-5。為了易於說明，第一鰭狀結構212-1、第二鰭狀結構212-2、第三鰭狀結構212-3、第四鰭狀結構212-4、與第五鰭狀結構212-5可一起視作鰭狀結構212。如圖3所示，可自堆疊204與基板202的一部分形成鰭狀結構212。在一些實施例中，步驟104圖案化堆疊204與基板202以形成鰭狀結構212。鰭狀結構212沿著Z方向自基板202垂直延伸。每一鰭狀結構212包括自基板202形成的基底部分12B，與自堆疊204形成的堆疊部分12S。可採用合適製程圖案化鰭狀結構212，包含多重圖案化或多重圖案化製程。一般而言，雙重圖案化或多重圖案化製程結合光微影與自對準製程，其產生的圖案間距小於採用單一的直接光微影製程所得的圖案間距。舉例來說，一些實施例形成材料層於基板上，並採用光微影製程圖案化材料層。可採用自對準製程沿著圖案化的材料層之側部形成間隔物。接著移除材料層，而保留的間隔物或芯之後可用於圖案化鰭狀結構212，且圖案化方法可為蝕刻堆疊204與基板202。蝕刻製程可包含乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他合適製程。
在圖3所示的一些實施例中，鰭狀結構212的間隔不同。第一鰭狀結構212-1與第二鰭狀結構212-2隔有第一空間S1。第二鰭狀結構212-2與第三鰭狀結構212-3隔有第二空間S2。第三鰭狀結構212-3與第四鰭狀結構212-4隔有第一空間S1。第四鰭狀結構212-4與第五鰭狀結構212-5隔有第一空間S1。在所述例子中，第二空間S2小於第一空間S1。在本發明實施例中，實施較小的第二空間S2的理由至少有兩個。在標準單元的情況下，與含有一致的第一空間S1的另一標準單元相較，較小的第二空間S2可減少標準單元的寬度。當標準單元的寬度固定時，較小的第二空間S2可轉換成較大的第一空間S1或較寬的鰭狀結構212以改善裝置效能。在一些例子中，第一空間S1可介於約15 nm至約40 nm之間，而第二空間S2可介於約5 nm至約40 nm之間。
如圖1及3所示，方法100的步驟106形成隔離結構203。在形成鰭狀結構212之後，可形成隔離結構203於相鄰的鰭狀結構212之間。隔離結構203亦可視作淺溝槽隔離結構203。在例示性製程中，可先沉積介電層於工件200上，以將介電材料填入鰭狀結構212之間的溝槽。在一些實施例中，介電層可包含氧化矽、氮化矽、氮氧化矽、氟矽酸鹽玻璃、低介電常數的介電層、上述之組合、及/或其他合適材料。在多種例子中，介電層的沉積方法可採用化學氣相沉積製程、次壓化學氣相沉積製程、可流動的化學氣相沉積製程、原子層沉積製程、物理氣相沉積製程、旋轉塗佈、及/或其他合適製程。接著可由化學機械研磨製程等方法薄化與平坦化沉積的介電材料。可由乾蝕刻製程、濕蝕刻製程、及/或上述之組合使平坦化的介電層進一步凹陷，以形成隔離結構203。如圖3所示，鰭狀結構212的堆疊部分12S高於隔離結構203。
如圖1及3所示，方法100的步驟108形成覆層214於第一鰭狀結構212-1、第二鰭狀結構212-2、第三鰭狀結構212-3、第四鰭狀結構212-4、與第五鰭狀結構212-5上。在一些實施例中，覆層214的組成可與犧牲層206的組成類似。在一例中，覆層214的組成可為矽鍺。由於共同組成，後續製程中釋放通道層208時可選擇性地移除犧牲層206與覆層214。在一些其他實施例中，犧牲層206與覆層214的組成為矽鍺但鍺含量不同，以在形成內側間隔物凹陷時導入不同的蝕刻選擇性。覆層214的鍺含量可小於犧牲層206的鍺含量。在一些例子中，犧牲層206的鍺含量可介於約20%至約25%之間，而覆層214的鍺含量可介於約15%至約19%之間。在步驟108中，覆層214的磊晶成長方法可採用氣相磊晶或分子束磊晶。在未圖示於圖3的一些實施方式中，形成覆層214的方法對鰭狀結構212的堆疊部分12S之表面具有選擇性，而不沉積或少量沉積覆層214於硬遮罩層210或隔離結構203上。在圖3所示的一些其他實施例中，可順應性地形成覆層214於鰭狀結構212上，包括形成於硬遮罩層210上。在一些實施例中，步驟108亦可包含回蝕刻製程以移除隔離結構203上的覆層214。回蝕刻製程的一例可為乾蝕刻製程，其採用溴化氫、氧氣、氯氣、或上述之混合物的電漿。
如圖1及4所示，方法100的步驟110形成第一虛置鰭狀物216與第二虛置鰭狀物218。如圖4所示，第一虛置鰭狀物216填入第一鰭狀結構212-1與第二鰭狀結構212-2之間、第三鰭狀結構212-3與第四鰭狀結構212-4之間、以及第四鰭狀結構212-4與第五鰭狀結構212-5之間的第一空間S1。第二虛置鰭狀物218填入第二鰭狀結構212-2與第三鰭狀結構212-3之間，以及其他兩個類似位置的鰭狀結構之間的第二空間S2。在製程的一例中，先順應性沉積第一介電層220於工件200上，包括沿著鰭狀結構212的側壁與隔離結構203的上表面沉積第一介電層220。在一些實施例中，第一介電層220可包含碳氮化矽或碳氮氧化矽，且其沉積方法可採用化學氣相沉積或原子層沉積。如圖4所示，順應性沉積的第一介電層220不完全填滿第一空間S1，但可完全填滿第二空間S2。在一些例子中，第一介電層220過早封閉第二鰭狀結構212-2與第三鰭狀結構212-3之間的開口，因此可在第二虛置鰭狀物218中發現空洞219。在沉積第一介電層220之後，可沉積第二介電層222於工件200上，包括沉積於第一介電層220上。在一些實施例中，第二介電層222可包含氧化矽，且其沉積方法可採用旋轉塗佈、可流動的化學氣相沉積製程、或合適的沉積製程。在一些例子中，為了改善第二介電層222的完整性與密度，可進行退火製程以退火第二介電層222。在沉積第二介電層222之後，可進行平坦化製程如化學機械研磨製程以平坦化第一介電層220與第二介電層222的上表面。在平坦化製程之後，即形成第一虛置鰭狀物216與第二虛置鰭狀物218。
以圖4進行說明。由於第一虛置鰭狀物216形成於第一空間S1中，每一第一虛置鰭狀物216沿著X方向的寬度可與第一空間S1相當。在一實施例中，第一虛置鰭狀物216的寬度與第一空間S1相同。類似地，由於第二虛置鰭狀物218形成於第二空間S2中，每一第二虛置鰭狀物218沿著X方向的寬度可與第二空間S2相當。在一實施例中，第二虛置鰭狀物218的寬度與第二空間S2相同。在此階段中，第一虛置鰭狀物216可視作具有第一介電層220 (如外側介電層)，以及第二介電層222 (如內側介電層)。如圖4所示，外側介電層如第一介電層220包覆內側介電層如第二介電層222的側壁與下表面，並隔開內側介電層如第二介電層222與覆層214。第二虛置鰭狀物218包括第一介電層220，且不含第二介電層222。由於第一虛置鰭狀物216與第二虛置鰭狀物218的構造不同，其可具有不同的抗蝕刻性與性質。第一介電層220的組成可為碳氮化矽或碳氮氧化矽，第二介電層222的組成可為氧化矽，因此第一介電層220的抗蝕刻性大於第二介電層222的抗蝕刻性。由於第二虛置鰭狀物218由第一介電層220形成而無第二介電層222，回蝕刻製程(如步驟112的回蝕刻製程，見下述內容)中的第二虛置鰭狀物218的蝕刻速率小於第一虛置鰭狀物216的蝕刻速率。
如圖1及5所示，方法100的步驟112回蝕刻第一虛置鰭狀物216與第二虛置鰭狀物218。在步驟112中，可選擇性地非等向回蝕刻第一虛置鰭狀物216與第二虛置鰭狀物218，以形成第一凹陷21與第二凹陷22。如圖5所示，由於第一虛置鰭狀物216與第二虛置鰭狀物218的構造不同，第一凹陷21比第二凹陷22深。在一些實施方式中，第一凹陷21可各自具有沿著Z方向的第一深度D1，而第二凹陷22可各自具有沿著Z方向的第二深度D2。第一深度D1大於第二深度D2。步驟112的回蝕刻可採用乾蝕刻製程。乾蝕刻製程的一例可採用含氧氣體、氫氣、含氟氣體(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、含氯氣體(如氯氣、氯仿、四氯化碳、及/或三氯化硼)、含溴氣體(如溴化氫及/或溴仿)、含碘氣體、其他合適氣體及/或電漿、及/或上述之組合。
如圖1、6、及7所示，方法100的步驟114選擇性修整第二虛置鰭狀物218。由於蓋層228 (如下述)可沉積於第一虛置鰭狀物216與第二虛置鰭狀物218上的凹陷中，較小的第二深度D2可能造成第二虛置鰭狀物218上的蓋層228較薄。由於蓋層228作為抗蝕刻的保護層，其厚度較小則可能會預期之外地移除蓋層228，並使第二虛置鰭狀物218的高度額外減少。第二虛置鰭狀物218的高度較小，則可能無法分隔相鄰裝置的源極/汲極結構。為解決此挑戰，本發明實施例實施步驟114以選擇性修整第二虛置鰭狀物218，進而增加第二凹陷22的深度以形成較深的第三凹陷23 (見圖7)。
先參考圖6。在製程的一例中，步驟114的選擇性修整可包含形成光阻遮罩224以露出第二虛置鰭狀物218，並覆蓋工件200的其餘部分。舉例來說，可採用旋轉塗佈或合適製程塗佈光阻層於工件200上。為了圖案化光阻層以形成光阻遮罩224，可軟烘烤、以穿過光罩或自光罩反射的射線曝光、在曝光後烘烤製程中烘烤、在顯影溶液中顯影、沖洗、並乾燥光阻層。在圖案化之後，光阻遮罩224包含開口226以露出第二虛置鰭狀物218。在光阻遮罩224的存在下，可由乾蝕刻製程、濕蝕刻製程、或其他合適的蝕刻製程蝕刻第二虛置鰭狀物218。合適的乾蝕刻製程可採用含氧氣體、氫氣、含氟氣體(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、含氯氣體(如氯氣、氯仿、四氯化碳、及/或三氯化硼)、含溴氣體(如溴化氫及/或溴仿)、含碘氣體、其他合適氣體及/或電漿、及/或上述之組合。合適的濕蝕刻製程可採用稀釋氫氟酸或緩衝清氟酸。在圖7所示的一些實施例中，步驟114的修整方法可增加第二凹陷22的第二深度D2以形成第三凹陷23。在其他實施例中，雖然第三凹陷23的深度大於第二深度D2，其可小於或大於第一深度D1。如此一來，本發明實施例的第三凹陷23的深度不需與第一深度D1相同，只要大於第二深度D2即可。如圖7所示，在選擇性修整第二虛置鰭狀物218之後，可由灰化或其他合適製程移除光阻遮罩224。
如圖1及8所示，方法100的步驟116沉積蓋層228於第一虛置鰭狀物216與第二虛置鰭狀物218上。在一些實施例中，蓋層228可包含高介電常數的介電材料，比如金屬氧化物。此處所用的高介電常數的介電材料，指的是介電常數大於氧化矽的介電常數(約3.9)的介電材料。合適的金屬氧化物可包含氧化鉿、氧化鋯、氧化鈦、氧化鉭、或氧化鋁。在一實施例中，蓋層228包括氧化鉿。在一些實施方式中，蓋層228的沉積方法可採用化學氣相沉積、可流動的化學氣相沉積、或合適的沉積方法。沉積的蓋層228可覆蓋第一虛置鰭狀物216、第二虛置鰭狀物218、硬遮罩層210、與覆層214的上表面。沉積蓋層228之後可進行平坦化製程如化學機械研磨製程，以移除鰭狀結構212上的蓋層228。此時的第一虛置鰭狀物216與第二虛置鰭狀物218的上表面共平面。在平坦化製程之後，蓋層228蓋住第一虛置鰭狀物216與第二虛置鰭狀物218的每一者。蓋層228可視作第一虛置鰭狀物216或第二虛置鰭狀物218的一部分。在此考量下，每一第二虛置鰭狀物218可視作具有第一介電層220所形成的底部，以及底部上的蓋層228。如此一來，步驟116之後的每一第一虛置鰭狀物216包含外側介電層如第一介電層220、內側介電層如第二介電層222、與蓋層228，而每一第二虛置鰭狀物218包含蓋層228位於第一介電層220上。在一些例子中，第一虛置鰭狀物216亦可視作第一混合鰭狀物或第一介電鰭狀物。類似地，第二虛置鰭狀物218亦可視作第二混合鰭狀物或第二介電鰭狀物。由於第一虛置鰭狀物216與第二虛置鰭狀物218只用於分隔結構且組成非半導體材料，其不形成半導體裝置如工件200的功能電路之部分。
如圖1及9所示，方法100的步驟118形成一或多個虛置閘極堆疊230於鰭狀結構212、第一虛置鰭狀物216、與第二虛置鰭狀物218上。在一些實施例中，採用閘極置換製程(或閘極後製製程)，其中一或多個虛置閘極堆疊230作為功能閘極結構所用的占位物。其他製程與設置亦屬可能。當一或多個虛置閘極堆疊230出現在圖9的剖視圖的平面之外時，採用虛線表示一個或多個虛置閘極堆疊230的相對位置。雖然圖式中的一或多個虛置閘極堆疊230為連續結構，其長度方向沿著X方向延伸越過鰭狀結構212，但虛置閘極堆疊230可包含超過一個虛置閘極部分。一或多個虛置閘極堆疊230之下的鰭狀結構212之區域，可視作通道區。鰭狀結構中的每一通道區夾設於形成源極/汲極所用的兩個源極/汲極區之間。
一或多個虛置閘極堆疊230的每一者可包含虛置介電層與虛置閘極。在一些實施例中，一或多個虛置閘極堆疊230的形成方法可為多種製程步驟，比如層狀物沉積、圖案化、蝕刻、以及其他合適的製程步驟。例示性的層狀物沉積製程可包含低壓化學氣相沉積、化學氣相沉積、電漿輔助化學氣相沉積、物理氣相沉積、原子層沉積、熱氧化、電子束蒸鍍、其他合適的沉積技術、或上述之組合。圖案化製程可包含微影製程(如光微影或電子束微影)，其可進一步包含塗佈光阻(如旋轉塗佈)、軟烘烤、對準光罩、曝光、曝光後烘烤、顯影光阻、沖洗、乾燥(如旋乾及/或硬烘烤)、其他合適的微影技術、及/或上述之組合。在一些實施 例中，蝕刻製程可包含乾蝕刻(如反應性離子蝕刻)、濕蝕刻、及/或其他蝕刻方法。在製程的一例中，可依序沉積虛置介電層、虛置閘極層、與閘極頂部的硬遮罩層於工件200上，包括沉積於鰭狀結構212上。接著採用光微影製程圖案化虛置介電層與虛置閘極層，以形成一或多個虛置閘極堆疊230。在一些實施例中，虛置介電層可包含氧化矽，而虛置閘極層可包含多晶矽。閘極頂部的硬遮罩層可包含氧化矽層與氮化物層。
雖然未圖示，在形成一或多個虛置閘極堆疊230之後，可沿著一或多個虛置閘極堆疊230的側壁沉積一或多個閘極間隔物。一或多個閘極間隔物可包含介電材料，其可用於選擇性移除一或多個虛置閘極堆疊230。一或多個閘極間隔物所用的合適介電材料可包含氮化矽、碳氮氧化矽、碳氮化矽、氧化矽、碳氧化矽、碳化矽、氮氧化矽、及/或上述之組合。在製程的一例中，先順應性沉積一或多個閘極間隔物的層狀物於含有一或多個虛置閘極堆疊230的工件200上，其可採用化學氣相沉積、次壓化學氣相沉積、或原子層沉積。接著可採用回蝕刻製程以自頂面表面移除這些層狀物，並沿著一或多個虛置閘極堆疊230的側壁留下一或多個閘極間隔物。
如圖1及10所示，方法100的步驟120使第一鰭狀結構212-1的源極/汲極區、第二鰭狀結構212-2的源極/汲極區、第三鰭狀結構212-3的源極/汲極區、第四鰭狀結構212-4的源極/汲極區、與第五鰭狀結構212-5的源極/汲極區凹陷。以一或多個虛置閘極堆疊230與一或多個閘極間隔物遮罩通道區，並使鰭狀結構212的源極/汲極區凹陷以形成第一源極/汲極溝槽234-1、第二源極/汲極溝槽234-2、第三源極/汲極溝槽234-3、第四源極/汲極溝槽234-4、與第五源極/汲極溝槽234-5。第一源極/汲極溝槽234-1位於第一鰭狀結構212-1的源極/汲極區中。第二源極/汲極溝槽234-2位於第二鰭狀結構212-2的源極/汲極區中。第三源極/汲極溝槽234-3位於第三鰭狀結構212-3的源極/汲極區中。第四源極/汲極溝槽234-4位於第四鰭狀結構212-4的源極/汲極區中。第五源極/汲極溝槽234-5位於第五鰭狀結構212-5的源極/汲極區中。為了方便說明，第一源極/汲極溝槽234-1、第二源極/汲極溝槽234-2、第三源極/汲極溝槽234-3、第四源極/汲極溝槽234-4、與第五源極/汲極溝槽234-5可一起視作源極/汲極溝槽234。在圖10所示的一些實施例中，步驟120可實質上移除鰭狀結構212的堆疊部分12S。步驟120的凹陷方法可包含乾蝕刻製程或其他合適的蝕刻製程。舉例來說，乾蝕刻製程可實施含氧氣體、氫氣、含氟氣體(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、含氯氣體(如氯氣、氯仿、四氯化碳、及/或三氯化硼)、含溴氣體(如溴化氫及/或溴仿)、含碘氣體、其他合適氣體及/或電漿、及/或上述之組合。如圖10所示，源極/汲極溝槽234中露出通道區中的犧牲層206與通道層208的側壁。由於通道區在圖10的剖視平面之外，因此以虛線表示犧牲層206與通道層208。
如圖1及11所示，方法100的步驟122形成內側間隔物結構232。在步驟122中，使源極/汲極溝槽234中露出的犧牲層206選擇性地部分凹陷以形成內側間隔物凹陷，而實質上未蝕刻露出的通道層208。在一實施例中，通道層208基本上由矽組成，而犧牲層206基本上由矽鍺組成，且使犧牲層206選擇性地部分凹陷之步驟可包括矽鍺氧化製程與之後的矽鍺氧化物移除。在這些實施例中，矽鍺氧化製程可採用臭氧。在一些實施例中，選擇性凹陷步驟可為選擇性等向蝕刻製程(如選擇性乾蝕刻製程或選擇性濕蝕刻製程)，而蝕刻製程的時間可控制犧牲層206的凹陷量。選擇性乾蝕刻製程可採用一或多種福為主的蝕刻劑，比如氟氣或氫氟碳化物。選擇性濕蝕刻製程可包含氫氟酸或氫氧化銨的蝕刻劑。接著順應性沉積內側間隔物材料層於工件200上，包括形成於內側間隔物凹陷之上與之中，且沉積方法可採用化學氣相沉積或原子層沉積。內側間隔物材料可包含氮化矽、碳氮氧化矽、碳氮化矽、氧化矽、碳氧化矽、碳化矽、或氮氧化矽。在沉積內側間隔物材料層之後，可回蝕刻內側間隔物材料層以形成內側間隔物結構232。
如圖1及12所示，方法100的步驟124形成第一型源極/汲極結構236與第二型源極/汲極結構238於源極/汲極溝槽234中。在一些實施例中，第一型源極/汲極結構236為n型源極/汲極結構，而第二型源極/汲極結構238為p型源極/汲極結構。在一些其他實施例中，第一型源極/汲極結構236為p型源極/汲極結構，而第二型源極/汲極結構238為n型源極/汲極結構。由於第一型源極/汲極結構236與第二型源極/汲極結構238不同，因此可採用至少一遮罩層分開形成上述兩者。在一些實施例中，第一型源極/汲極結構236與第二型源極/汲極結構238之形成方法可採用磊晶製程，比如氣相磊晶、超高真空化學氣相沉積、分子束磊晶、及/或其他合適製程。磊晶成長製程可採用氣態及/或液態前驅物，其可與基板202以及通道層208的組成作用。n型源極/汲極結構的例子可包含矽、砷化鎵、砷化矽、磷化矽、磷砷化鎵、或其他合適材料。在磊晶製程時可導入n型摻質如磷、砷、或上述兩者以原位摻雜n型源極/汲極結構，或採用佈植製程(比如接面佈植製程)摻雜n型源極/汲極結構。p型源極/汲極結構的例子可包含鍺、矽鍺、砷化鋁鎵、硼化矽鍺、或其他合適材料。在磊晶製程時可導入p型摻質如硼以原位摻雜p型源極/汲極結構，或採用佈植製程(比如接面佈植製程)摻雜p型源極/汲極結構。
如圖1所示，方法100的步驟126可進行後續製程。如圖1及13所示，方法100可包含後續製程。舉例來說，這些後續製程可包含沉積接點蝕刻停止層、沉積層間介電層、移除虛置閘極堆疊230 (見圖12)、選擇性移除通道區中的犧牲層206、以及形成閘極結構。在製程的一例中，可先沉積接點蝕刻停止層於工件200上。接點蝕刻停止層可包含氮化矽、氧化矽、氮氧化矽、及/或本技術領域已知的其他材料。接點蝕刻停止層的沉積方法可採用原子層沉積、電漿輔助化學氣相沉積製程、及/或其他合適的沉積或氧化製程。層間介電層沉積於接點蝕刻停止層上。在一些實施例中，層間介電層包含的材料可為四乙氧基矽烷的氧化物、未摻雜的矽酸鹽玻璃、或摻雜的氧化矽(如硼磷矽酸鹽玻璃、氟矽酸鹽玻璃、磷矽酸鹽玻璃、或硼矽酸鹽玻璃)、及/或其他合適的介電材料。層間介電層的沉積方法可為旋轉塗佈、電漿輔助化學氣相沉積製程、或其他合適的沉積技術。一些實施例在形成層間介電層之後，可退火工件200以改善層間介電層的完整性。為了移除多餘材料與露出虛置閘極堆疊230的上表面，可進行平坦化製程如化學機械研磨製程。接著自工件200移除露出的虛置閘極堆疊230。移除虛置閘極堆疊230可形成閘極溝槽於一或多個閘極間隔物所定義的通道區上。移除虛置閘極堆疊230的方法可包含一或多道蝕刻製程，其對虛置閘極堆疊230中的材料具有選擇性。舉例來說，可採用選擇性濕蝕刻、選擇性乾蝕刻、或上述之組合以移除虛置閘極堆疊230。在移除虛置閘極堆疊230之後，閘極溝槽中可露出通道區中的覆層214、通道層208、與犧牲層206的側壁。
在移除虛置閘極堆疊230之後，可選擇性移除通道區中的通道層208與覆層之間的犧牲層206以釋放通道層208，進而形成通道組件。選擇性移除犧牲層206的步驟可實施選擇性乾蝕刻、選擇性濕蝕刻、或其他選擇性蝕刻製程。在一些實施例中，選擇性濕蝕刻包括採用氫氧化銨、過氧化氫、與水的混合物之蝕刻。在犧牲層206與覆層214的組成為矽鍺的實施例中，選擇性移除的方法包括氧化矽鍺，接著移除矽鍺氧化物。舉例來說，可由臭氧清潔進行氧化，接著以蝕刻劑如氫氧化銨移除氧化矽鍺。接著沉積閘極結構於閘極溝槽中，以在X-Z平面上包覆每一通道組件。在一些實施例中，閘極結構可包含閘極介電層，與形成於閘極介電層上的閘極。在一些實施例中，閘極介電層可包含界面層與高介電常數的介電層。此處所用與所述的高介電常數的閘極介電層包含高介電常數的介電材料，比如介電常數大於熱氧化矽的介電常數(約3.9)的介電材料。界面層可包含介電材料如氧化矽、矽酸鉿、或氮氧化矽。界面層的沉積方法可採用化學氧化、熱氧化、原子層沉積、化學氣相沉積、及/或其他合適方法。高介電常數的介電層可包含氧化鉿。在其他實施例中，高介電常數的介電層可包含其他高介電常數的介電材料，比如氧化鈦、氧化鉿鋯、氧化鉭、氧化鉿矽、氧化鋯、氧化鋯矽、氧化鑭、氧化鋁、氧化釔、鈦酸鍶、鈦酸鋇、氧化鋇鋯、氧化鉿鑭、氧化鑭矽、氧化鋁矽、氧化鉿鉭、氧化鉿鈦、鈦酸鋇鍶、氮化矽、氮氧化矽、上述之組合、或其他合適材料。高介電常數的介電層之形成方法可為原子層沉積、物理氣相沉積、化學氣相沉積、氧化、及/或其他合適方法。
閘極結構的閘極可包含單層或多層結構，比如具有選定功函數的金屬層之多種組合以增進裝置效能(如功函數金屬層)、襯墊層、濕潤層、黏著層、金屬合金、或金屬矽化物。舉例來說，閘極可為氮化鈦、鈦鋁、氮化鈦鋁、氮化鉭、鉭鋁、氮化鉭鋁、碳化鉭鋁、碳氮化鉭、鋁、鎢、鎳、鈦、釕、鈷、鉑、碳化鉭、氮化鉭矽、銅、其他耐火金屬、其他合適的金屬材料、或上述之組合。在多種實施例中，閘極結構的閘極之形成方法可為原子層沉積、物理氣相沉積、化學氣相沉積、電子束蒸鍍、或其他合適製程。在多種實施例中，可進行平坦化製程如化學機械研磨製程移除多餘材料，以提供閘極結構的實質上平坦的上表面。
參考圖3。依據本發明實施例，第二空間S2小於第一空間S1，且第二空間S2為相同導電型的電晶體所用的空間。在圖3中，較小的第二空間S2為第二鰭狀結構212-2與第三鰭狀結構212-3之間的X方向空間。第二鰭狀結構212-2與第三鰭狀結構212-3用於一導電型的的電晶體，而第一鰭狀結構212-1、第四鰭狀結構212-4、與第五鰭狀結構212-5用於其他導電型的電晶體。舉例來說，第二鰭狀結構212-2與第三鰭狀結構212-3用於p型多橋狀通道電晶體，而第一鰭狀結構212-1、第四鰭狀結構212-4、與第五鰭狀結構212-5用於n型多橋狀通道電晶體。在一例中，第二鰭狀結構212-2與第三鰭狀結構212-3用於n型多橋狀通道電晶體，而第一鰭狀結構212-1、第四鰭狀結構212-4、與第五鰭狀結構212-5用於p型多橋狀通道電晶體。此設置具有一些理由。舉例來說，可分開形成不同型的多橋狀通道電晶體所用的源極/汲極結構，使不同的源極/汲極結構不易合併。
較小的第二空間S2可提供優點。在具有多個n型多橋狀通道電晶體與多個p型多橋狀通道電晶體的標準單元中，減少相鄰的n型多橋狀通道電晶體之間或相鄰的p型多橋狀通道電晶體的空間，可減少標準單元的X方向尺寸以增加封裝密度。當標準單元的X方向尺寸維持固定，某一型裝置之間的第二空間S2較小可加寬其他型裝置所用的通道組件。本發明實施例的優點如圖13所示，其為半導體裝置如工件200的上視圖。如圖13所示，半導體裝置如工件200包含靜態隨機存取記憶體單元250。靜態隨機存取記憶體單元250包含第一下拉電晶體PD-1、第二下拉電晶體PD-2、第一上拉電晶體PU-1、第二上拉電晶體PU-2、第一穿閘電晶體PG-1、與第二穿閘電晶體PG-2。在圖13所示的一些實施方式中，靜態隨機存取記憶體單元250可進一步包含第一隔離電晶體IS-1與第二隔離電晶體IS-2。第一閘極結構240可控制第一穿閘電晶體PG-1。第一下拉電晶體PD-1、第一上拉電晶體PU-1、與第二隔離電晶體IS-2可共用第二閘極結構242。第一隔離電晶體IS-1、第二上拉電晶體PU-2、與第二下拉電晶體PD-2可共用第三閘極結構244。第四閘極結構246可控制第二穿閘電晶體PG-2。
在一些實施例中，第一下拉電晶體PD-1、第一穿閘電晶體PG-1、第二穿閘電晶體PG-2、與第二下拉電晶體PD-2為位於p型井上的n型多橋狀通道電晶體，而第一上拉電晶體PU-1與第二上拉電晶體PU-2為位於n型井上的p型裝置。第一下拉電晶體PD-1、第一穿閘電晶體PG-1、第二穿閘電晶體PG-2、與第二下拉電晶體PD-2的源極/汲極結構為第一型源極/汲極結構236。第一上拉電晶體PU-1與第二上拉電晶體PU-2的源極/汲極結構為第二型源極/汲極結構238。在這些實施例中，第一型源極/汲極結構236為n型源極/汲極結構，而第二型源極/汲極結構238為p型源極/汲極結構。第一型源極/汲極結構236與第二型源極/汲極結構238隔有第一虛置鰭狀物216。相鄰的第二型源極/汲極結構238彼此隔有第二虛置鰭狀物218。相鄰的第一型源極/汲極結構236彼此隔有第一虛置鰭狀物216。如圖13所示，較小的第二空間S2可減少靜態隨機存取記憶體單元250的尺寸，或沿著X方向增加n型電晶體(如第一下拉電晶體PD-1、第一穿閘電晶體PG-1、第二穿閘電晶體PG-2、與第二下拉電晶體PD-2)所用的通道寬度。在後者的狀況中，增加n型多橋狀通道電晶體的通道寬度，可改善n型多橋狀通道電晶體的效能並減少靜態隨機存取記憶體單元250的最小電源電壓。
本發明一例示性的實施例關於半導體裝置。半導體裝置包括第一源極/汲極結構；第二源極/汲極結構；第三源極/汲極結構；第一虛置鰭狀物，沿著方向位於第一源極/汲極結構與第二源極/汲極結構之間，以隔離第一源極/汲極結構與第二源極/汲極結構；以及第二虛置鰭狀物，沿著方向位於第二源極/汲極結構與第三源極/汲極結構之間，以隔離第二源極/汲極結構與第三源極/汲極結構。第一虛置鰭狀物包括外側介電層、內側介電層位於外側介電層上、與第一蓋層位於外側介電層與內側介電層上，第二虛置鰭狀物包括底部與第二蓋層位於底部上。
在一些實施例中，第一源極/汲極結構為n型源極/汲極結構，而第二源極/汲極結構與第三源極/汲極結構為p型源極/汲極結構。在一些實施例中，第一源極/汲極結構包括矽與n型摻質，而第二源極/汲極結構與第三源極/汲極結構包括矽鍺與p型摻質。在 些實施例中，內側介電層與第一源極/汲極結構隔有外側介電層，並與第二源極/汲極結構隔有外側介電層。在一些例子中，外側介電層包括碳氮化矽或碳氮氧化矽，內側介電層包括氧化矽，且第一蓋層包括氧化鉿、氧化鋯、氧化鈦、氧化鉭、或氧化鋁。在一些實施例中，底部包括碳氮化矽或碳氮氧化矽，且第二蓋層包括氧化鉿、氧化鋯、氧化鈦、氧化鉭、或氧化鋁。在一些實施例中，內側介電層的上表面與底部的上表面實質上共平面。在一些實施例中，第一虛置鰭狀物沿著方向的寬度大於第二鰭狀物沿著方向的寬度。
本發明另一實施例關於靜態隨機存取記憶體單元。靜態隨機存取記憶體單元包括下拉電晶體，包括第一源極/汲極結構；上拉電晶體，包括第二源極/汲極結構；第一虛置鰭狀物，沿著方向分隔下拉電晶體與上拉電晶體；以及第二虛置鰭狀物，與第二源極/汲極結構相鄰。上拉電晶體沿著方向位於第一虛置鰭狀物與第二虛置鰭狀物之間。第一虛置鰭狀物包括外側介電層、內側介電層位於外側介電層上、與第一蓋層位於外側介電層與內側介電層上。第二虛置鰭狀物包括底部與第二蓋層位於底部上。
在一些實施例中，下拉電晶體包括n型電晶體，且上拉電晶體包括p型電晶體。在一些實施例中，第一源極/汲極結構包括矽與n型摻質，且第二源極/汲極結構包括矽鍺與p型摻質。在一些實施方式中，內側介電層與第一源極/汲極結構隔有外側介電層，並與第二源極/汲極結構隔有外側介電層。在一些實施例中，外側介電層包括碳氮化矽或碳氮氧化矽，內側介電層包括氧化矽，且第一蓋層包括氧化鉿、氧化鋯、氧化鈦、氧化鉭、或氧化鋁。在一些例子中，底部包括碳氮化矽或碳氮氧化矽，且第二蓋層包括氧化鉿、氧化鋯、氧化鈦、氧化鉭、或氧化鋁。在一些實施方式中，第一虛置鰭狀物沿著方向的寬度大於第二虛置鰭狀物沿著方向的寬度。
本發明又一實施例關於半導體裝置的形成方法。方法包括接收工件，其包括:第一鰭狀結構，其長度方向沿著第一方向延伸，並具有第一基底部分與第一堆疊部分位於第一基底部分上；第二鰭狀結構，其長度方向沿著第一方向延伸，並具有第二基底部分與第二堆疊部分位於第二基底部分上，其中第一鰭狀結構與第二鰭狀結構隔有第一空間，以及第三鰭狀結構，其長度方向沿著第一方向延伸，並具有第三基底部分與第三堆疊部分位於第三基底部分上，其中第二鰭狀結構與第三鰭狀結構隔有第二空間，且第二空間小於第一空間。方法更包括形成隔離結構於第一基底部分與第二基底部分之間，以及第二基底部分與第三基底部分之間；順應性地沉積第一介電層於第一堆疊部分、第二堆疊部分、第三堆疊部分、與隔離結構上；沉積第二介電層於第一介電層上；平坦化工件以形成第一虛置鰭狀物於第一堆疊部分與第二堆疊部分之間，並形成第二虛置鰭狀物於第二堆疊部分與第三堆疊部分之間；回蝕刻第一虛置鰭狀物與第二虛置鰭狀物；選擇性回蝕刻第二虛置鰭狀物；在選擇性回蝕刻之後，沉積第三介電層於工件上；使第一堆疊部分、第二堆疊部分、與第三堆疊部分凹陷；以及形成第一源極/汲極結構於第一基底部分上、形成第二源極/汲極結構於第二基底部分上、並形成第三源極/汲極結構於第三基底部分上。
在一些實施例中，第一堆疊部分、第二堆疊部分、與第三堆疊部分包括交錯的多個通道層與多個犧牲層。多個通道層包括矽，且多個犧牲層包括矽鍺。一些實施例更包括在順應性沉積第一介電層之前，沉積矽鍺覆層於第一堆疊部分、第二堆疊部分、與第三堆疊部分上。在一些實施例中，第一介電層包括碳氮化矽或碳氮氧化矽，第二介電層包括氧化矽，且第三介電層包括氧化鉿、氧化鋯、氧化鈦、氧化鉭、或氧化鋁。在一些例子中，回蝕刻第一虛置鰭狀物與第二虛置鰭狀物之後，第二虛置鰭狀物的上表面與隔離結構的距離大於第一虛置鰭狀物的上表面與隔離結構的距離。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
D1:第一深度 D2:第二深度 IS-1:第一隔離電晶體 IS-2:第二隔離電晶體 PD-1:第一下拉電晶體 PD-2:第二下拉電晶體 PG-1:第一穿閘電晶體 PG-2:第二穿閘電晶體 PU-1:第一上拉電晶體 PU-2:第二上拉電晶體 S1:第一空間 S2:第二空間 12B:基底部分 12S:堆疊部分 21:第一凹陷 22:第二凹陷 23:第三凹陷 100:方法 102,104,106,108,110,112,114,116,118,120,122,124, 126:步驟 200:工件 202:基板 203:隔離結構 204:堆疊 206:犧牲層 208:通道層 210:硬遮罩層 212:鰭狀結構 212-1:第一鰭狀結構 212-2:第二鰭狀結構 212-3:第三鰭狀結構 212-4:第四鰭狀結構 212-5:第五鰭狀結構 214:覆層 216:第一虛置鰭狀物 218:第二虛置鰭狀物 219:空洞 220:第一介電層 222:第二介電層 224:光阻遮罩 226:開口 228:蓋層 230:虛置閘極堆疊 232:內側間隔物結構 234:源極/汲極溝槽 234-1:第一源極/汲極溝槽 234-2:第二源極/汲極溝槽 234-3:第三源極/汲極溝槽 234-4:第四源極/汲極溝槽 234-5:第五源極/汲極溝槽 236:第一型源極/汲極結構 238:第二型源極/汲極結構 240:第一閘極結構 242:第二閘極結構 244:第三閘極結構 246:第四閘極結構 250:靜態隨機存取記憶體單元
圖1係本發明一或多個實施例中，形成半導體裝置所用的方法之流程圖。 圖2至12係本發明一或多個實施例中，依據圖1的方法之製作製程時的工件之部分剖視圖。 圖13係本發明一或多個實施例中，依據圖1的方法之製作製程時的半導體裝置之部分上視圖。
100:方法
102,104,106,108,110,112,114,116,118,120,122,124,126:步驟

Claims (1)

  1. 一種半導體裝置，包括： 一第一源極/汲極結構； 一第二源極/汲極結構； 一第三源極/汲極結構； 一第一虛置鰭狀物，沿著一方向位於該第一源極/汲極結構與該第二源極/汲極結構之間，以隔離該第一源極/汲極結構與該第二源極/汲極結構；以及 一第二虛置鰭狀物，沿著該方向位於該第二源極/汲極結構與該第三源極/汲極結構之間，以隔離該第二源極/汲極結構與該第三源極/汲極結構， 其中該第一虛置鰭狀物包括一外側介電層、一內側介電層位於該外側介電層上、與一第一蓋層位於該外側介電層與該內側介電層上， 其中該第二虛置鰭狀物包括一底部與一第二蓋層位於該底部上。
TW110123313A 2020-06-29 2021-06-25 半導體裝置 TW202201543A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/915,609 US11637109B2 (en) 2020-06-29 2020-06-29 Source/drain feature separation structure
US16/915,609 2020-06-29

Publications (1)

Publication Number Publication Date
TW202201543A true TW202201543A (zh) 2022-01-01

Family

ID=78238183

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110123313A TW202201543A (zh) 2020-06-29 2021-06-25 半導體裝置

Country Status (3)

Country Link
US (2) US11637109B2 (zh)
CN (1) CN113594164A (zh)
TW (1) TW202201543A (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11211381B2 (en) * 2019-01-29 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US11024650B2 (en) * 2019-04-26 2021-06-01 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and a method for fabricating the same
US11908910B2 (en) * 2020-10-27 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having embedded conductive line and method of fabricating thereof

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7780865B2 (en) * 2006-03-31 2010-08-24 Applied Materials, Inc. Method to improve the step coverage and pattern loading for dielectric films
US8625334B2 (en) * 2011-12-16 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell
US8697536B1 (en) * 2012-11-27 2014-04-15 International Business Machines Corporation Locally isolated protected bulk finfet semiconductor device
US10199502B2 (en) 2014-08-15 2019-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure of S/D contact and method of making same
US9312186B1 (en) * 2014-11-04 2016-04-12 Taiwan Semiconductor Manufacturing Company Limited Method of forming horizontal gate all around structure
US9818872B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9858985B2 (en) * 2015-10-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Dual port SRAM cell
US9754840B2 (en) 2015-11-16 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Horizontal gate-all-around device having wrapped-around source and drain
US10032627B2 (en) 2015-11-16 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming stacked nanowire transistors
US9887269B2 (en) 2015-11-30 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9899269B2 (en) 2015-12-30 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd Multi-gate device and method of fabrication thereof
US9899398B1 (en) 2016-07-26 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory device having nanocrystal floating gate and method of fabricating same
DE112016007104T5 (de) * 2016-09-30 2019-04-18 Intel Corporation Dual-finne-endkappe für selbstjustierte (sage) architekturen
US10290546B2 (en) 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold voltage adjustment for a gate-all-around semiconductor structure
US10134876B2 (en) * 2017-03-31 2018-11-20 Globalfoundries Inc. FinFETs with strained channels and reduced on state resistance
US10170318B2 (en) * 2017-04-28 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned contact and manufacturing method thereof
US10475902B2 (en) 2017-05-26 2019-11-12 Taiwan Semiconductor Manufacturing Co. Ltd. Spacers for nanowire-based integrated circuit device and method of fabricating same
US10658370B2 (en) * 2017-06-29 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10403714B2 (en) * 2017-08-29 2019-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. Fill fins for semiconductor devices
US10510580B2 (en) * 2017-09-29 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy fin structures and methods of forming same
US10978351B2 (en) * 2017-11-17 2021-04-13 Taiwan Semiconductor Manufacturing Co., Ltd. Etch stop layer between substrate and isolation structure
US10930767B2 (en) * 2018-07-16 2021-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-like field effect transistor patterning methods for achieving fin width uniformity
KR20210000529A (ko) * 2019-06-25 2021-01-05 삼성전자주식회사 집적 회로 반도체 소자

Also Published As

Publication number Publication date
CN113594164A (zh) 2021-11-02
US20220367482A1 (en) 2022-11-17
US11637109B2 (en) 2023-04-25
US20210408012A1 (en) 2021-12-30

Similar Documents

Publication Publication Date Title
TWI692104B (zh) 半導體裝置與其製作方法
TWI791855B (zh) 半導體裝置及其製造方法和多閘極半導體裝置
US20230377873A1 (en) Cut metal gate process for reducing transistor spacing
TW201913757A (zh) 半導體結構與其製作方法
TW202127663A (zh) 半導體裝置
TWI768834B (zh) 半導體裝置及其製造方法
TWI786608B (zh) 半導體裝置及其製造方法
TW202017189A (zh) 半導體裝置
TW202201543A (zh) 半導體裝置
TW202220210A (zh) 半導體裝置
TW202147458A (zh) 半導體裝置及其製造方法
TW202205389A (zh) 半導體裝置及其形成方法
TW202205436A (zh) 半導體裝置
TW202201558A (zh) 製造半導體裝置的方法
TW201933492A (zh) 半導體裝置的形成方法
TWI807398B (zh) 半導體裝置與其形成方法
TWI780649B (zh) 半導體裝置及其形成方法
TW202230740A (zh) 半導體裝置
TW202215540A (zh) 半導體裝置的形成方法
US11615965B2 (en) Semiconductor FinFET device and method
TW202242971A (zh) 積體電路結構之製造方法
TW202230606A (zh) 半導體裝置
TWI795774B (zh) 填充結構及其製造方法
US20230187216A1 (en) Semiconductor FinFET Device and Method
TW202433559A (zh) 半導體裝置及其製造方法