TW202147458A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW202147458A
TW202147458A TW110102051A TW110102051A TW202147458A TW 202147458 A TW202147458 A TW 202147458A TW 110102051 A TW110102051 A TW 110102051A TW 110102051 A TW110102051 A TW 110102051A TW 202147458 A TW202147458 A TW 202147458A
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gate
fully wound
layer
length
thickness
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TWI773094B (zh
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鍾政庭
蔡慶威
程冠倫
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台灣積體電路製造股份有限公司
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Abstract

依據本發明實施例的半導體裝置包含在第一裝置區中的第一複數個全繞式閘極裝置以及在第二裝置區中的第二複數個全繞式閘極裝置。第一複數個全繞式閘極裝置的每一者包含沿第一方向延伸的第一垂直堆疊通道元件以及在第一垂直堆疊通道元件上方並圍繞第一垂直堆疊通道元件的第一閘極結構。第二複數個全繞式閘極裝置的每一者包含沿第二方向延伸的第二垂直堆疊通道元件以及在第二垂直堆疊通道元件上方並圍繞第二垂直堆疊通道元件的第二閘極結構。第一複數個全繞式閘極裝置的每一者包含一第一通道長度，且第二複數個全繞式閘極裝置的每一者包含小於第一通道長度的第二通道長度。

Description

半導體裝置及其製造方法
本發明實施例係有關於半導體技術，且特別是有關於半導體裝置及其製造方法。
積體電路(integrated circuit，IC)產業已經歷了快速成長。在積體電路材料和設計上的技術進步產生了數代積體電路，每一代都比前一代具有更小且更複雜的電路。在積體電路的發展史中，功能密度(即每一晶片區互連的裝置數目)增加，同時幾何尺寸(即製造過程中所產生的最小的組件或線路)縮小。此元件尺寸微縮化的製程提供增加生產效率與降低相關費用的益處。此元件尺寸微縮化也增加了加工和製造積體電路的複雜性。
舉例來說，隨著積體電路(IC)技術朝更小的技術節點發展，已引進多閘極裝置透過增加閘極通道耦合、降低關態電流及減少短通道效應(short-channel effects，SCEs)來改善閘極控制。多閘極裝置一般代表具有閘極結構或閘極結構的一部分設置於通道區的多於一面上方的裝置。鰭式場效電晶體(Fin-like field effect transistors，FinFETs)和全繞式閘極(gate-all-around，GAA)電晶體(兩者也被稱為非平面電晶體)為高效能且低漏電應用之已流行且有潛力的候選的多閘極裝置的範例。鰭式場效電晶體具有由閘極在多於一面圍繞的升高的通道(舉例來說，閘極圍繞從基底延伸的半導體材料的“鰭”的頂部和側壁)。相較於平面電晶體，此配置提供通道的較佳控制以及大幅地減少短通道效應(特別來說，透過減少次臨界漏電流(即在關態的鰭式場效電晶體的源極與汲極之間的耦合)來達到)。全繞式閘極電晶體具有可部分延伸或完全延伸於通道區周圍的閘極結構，以在兩面或更多面上提供入口至通道區。全繞式閘極電晶體的通道區可由奈米線、奈米片、其他奈米結構及/或其他合適的結構形成。在一些實施例中，此通道區包含垂直堆疊的多個奈米線(其水平延伸，進而提供水平定向的通道)。這種全繞式閘極電晶體可被稱為垂直堆疊水平全繞式閘極(vertically-stacked horizontal GAA，VGAA)電晶體。
已發展不同的製程來實現在不同裝置區域中有著不同臨界電壓之不同的全繞式閘極電晶體。不同的電壓允許在不同裝置區域中電晶體的階段啟動。已觀察到的是，這些傳統製程可能導致閘極邊緣粗糙及降低製程穩定性。因此，雖然傳統全繞式閘極裝置一般對於其預期目的為足夠的，但是這些全繞式閘極裝置並非在所有方面都令人滿意。
在一些實施例中，提供半導體裝置，半導體裝置包含第一複數個全繞式閘極裝置，在第一裝置區中，其中第一複數個全繞式閘極裝置的每一者包含第一垂直堆疊通道元件，沿第一方向延伸；及第一閘極結構，在第一垂直堆疊通道元件上方並圍繞第一垂直堆疊通道元件；以及第二複數個全繞式閘極裝置，在第二裝置區中，其中第二複數個全繞式閘極裝置的每一者包含:第二垂直堆疊通道元件，沿第二方向延伸；及第二閘極結構，在第二垂直堆疊通道元件上方並圍繞第二垂直堆疊通道元件，其中第一複數個全繞式閘極裝置的每一者包含一第一通道長度，其中第二複數個全繞式閘極裝置的每一者包含小於第一通道長度的第二通道長度。
在一些其他實施例中，提供半導體裝置，半導體裝置包含第一複數個全繞式閘極裝置，在第一裝置區中，其中第一複數個全繞式閘極裝置的每一者包含:第一垂直堆疊通道元件，沿第一方向延伸；第一閘極頂部部件，設置於第一垂直堆疊通道元件的最頂部通道元件上方；及複數個第一下方閘極部件，設置於第一垂直堆疊通道元件的兩相鄰通道元件之間；以及第二複數個全繞式閘極裝置，在第二裝置區中，其中第二複數個全繞式閘極裝置的每一者包含:第二垂直堆疊通道元件，沿第二方向延伸；第二閘極頂部部件，設置於第二垂直堆疊通道元件的最頂部通道元件上方；及複數個第二下方閘極部件，設置於第二垂直堆疊通道元件的兩相鄰通道元件之間，其中第一閘極頂部部件包含沿第一方向的第一長度，其中第二閘極頂部部件包含沿第二方向的第二長度，且第一長度和第二長度大致相等，其中複數個第一下方閘極部件的每一者包含沿第一方向的第三長度，其中複數個第二下方閘極部件的每一者包含沿第二方向的第四長度，其中第三長度大於第四長度。
在另外一些實施例中，提供半導體裝置的製造方法，此方法包含在基底上形成堆疊物層，堆疊物層包含交錯的複數個第一半導體層和複數個第二半導體層；從基底的第一區的堆疊物層形成第一複數個鰭元件；從基底的第二區的堆疊物層形成第二複數個鰭元件；在第一複數個鰭元件上方形成第一複數個虛設閘極堆疊物；在第二複數個鰭元件上方形成第二複數個虛設閘極堆疊物；在第一複數個虛設閘極堆疊物和第二複數個虛設閘極堆疊物上方沉積間隔層；在沉積於第一複數個虛設閘極堆疊物上方的間隔層上方選擇性沉積聚合物層，且聚合物層不覆蓋設置於第二複數個虛設閘極堆疊物上方的間隔層；以及蝕刻在第一複數個虛設閘極堆疊物和第二複數個虛設閘極堆疊物上方的間隔層。
要瞭解的是以下的揭露內容提供許多不同的實施例或範例，以實施提供之主體的不同部件。以下敘述各個構件及其排列方式的特定範例，以求簡化揭露內容的說明。當然，這些僅為範例並非用以限定本發明。例如，以下的揭露內容敘述了將一第一部件形成於一第二部件之上或上方，即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例，亦包含了尚可將附加的部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與上述第二部件可能未直接接觸的實施例。此外，揭露內容中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語也涵蓋裝置在使用或操作中的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。再者，當用“大約”、“近似”及類似術語描述數字或數字範圍時，除非另有指明，否則此術語目的在涵蓋在所描述的數字的+/- 10%內的數字。舉例來說，術語“約5nm”涵蓋4.5nm至5.5nm的尺寸範圍。
本發明實施例一般為有關於多閘極電晶體及製造方法，且特別為有關於在半導體裝置的不同裝置區域中製造全繞式閘極(GAA)電晶體。
多閘極裝置包含電晶體，這些電晶體的閘極結構形成於通道區的至少兩面上。這些多閘極裝置可包含p型金屬氧化物半導體裝置或n型金屬氧化物半導體裝置。多閘極電晶體的範例包含鰭式場效電晶體(由其鰭狀結構得名)及全繞式閘極裝置。全繞式閘極裝置包含具有閘極結構或閘極結構的一部分設置於通道區的四面上(例如圍繞通道區的一部分)。本發明實施例可具有設置於奈米線通道、棒狀通道、奈米片通道、奈米結構通道、圓柱形通道、柱狀通道及/或其他合適的通道配置中的通道區。依據本發明實施例的裝置可具有與單一、連續閘極結構相關聯的一個或多個通道區(例如奈米線、奈米片、奈米結構)。然而，具通常知識者將理解本發明實施例的教示可應用於單一通道(例如單一奈米線、單一奈米片、單一奈米結構)或任何數量的通道。本領域具通常知識者可理解半導體裝置的其他範例可受益於本發明實施例的各方面。
隨著鰭式場效電晶體中的鰭寬度的尺寸縮小，通道寬度變異可導致不期望的變異及移動率損失。將全繞式閘極電晶體研究作為鰭式場效電晶體的變化型。在全繞式閘極電晶體中，將電晶體的閘極製作為全部圍繞通道，使得閘極圍繞或環繞通道。此類電晶體具有透過閘極改善通道的靜電控制的優點，也減少了漏電流。全繞式閘極電晶體包含各種間隙壁，例如內部間隙壁和閘極間隙壁(也被稱為外部間隙壁、頂部間隙壁或主要間隙壁)。內部間隙壁用以減少電容，並防止閘極結構與源極/汲極部件之間的漏電流。在全繞式閘極電晶體的形成期間，閘極間隙壁作為源極/汲極溝槽形成期間的遮罩。在閘極取代製程期間，閘極間隙壁用以維持在移除虛設閘極堆疊物之後的閘極溝槽的完整性，以為金屬閘極堆疊物騰出空間。將本發明實施例的方法設計為製造具有不同臨界電壓的全繞式閘極電晶體，以在不同區域中形成不同厚度的閘極間隙壁。
第1A-1C圖顯示形成半導體裝置的方法100，半導體裝置具有多個閘極裝置的多個裝置區域。如本文所使用，術語“多閘極裝置”用於描述具有至少一些閘極材料設置於裝置的至少一通道的多個面上的裝置(例如半導體裝置)。在一些範例中，多閘極裝置可被稱為全繞式閘極裝置，全繞式閘極裝置具有閘極材料設置於裝置的至少一通道的至少四面上。通道區可被稱為奈米線、奈米片、奈米結構、通道元件、半導體通道元件，如本文所使用，通道區包含各種幾何形狀(例如圓柱狀、棒狀、片狀)及各種尺寸。
如本文討論的其他方法實施例和例示性裝置，應當理解的是，顯示於第2、3、4A-4B、5A-5B、6A-6B、7A-7B、8A-8B、9A-9B、10A-10B、11A-11B、12A-12B、13A-13B、14A-14B、15、16、17、18、19、20、21和22A-22B圖中的工件200的一部分可透過互補式金屬氧化物半導體技術製程流程製造，因此本文僅簡要描述一些製程。在完成製造過程之後，工件200將被製造為半導體裝置。從這個意義上來說，在合適的上下文中，工件200可被稱為半導體裝置。再者，例示性半導體裝置可包含各種其他裝置和部件，例如包含額外電晶體、雙極性接面電晶體、電阻、電容、電感、二極體、熔絲、靜態隨機存取記憶體及/或其他邏輯電路等的其他類型裝置，但是為了更容易理解本發明實施例的發明概念，將例示性半導體裝置簡化。在一些實施例中，例示性裝置包含複數個半導體裝置(例如電晶體)，這些裝置包含可互連的n型全繞式閘極電晶體、p型全繞式閘極電晶體、p型場效電晶體、n型場效電晶體等。再者，應當注意的是，在方法100的製程步驟中，包含參考第2、3、4A-4B、5A-5B、6A-6B、7A-7B、8A-8B、9A-9B、10A-10B、11A-11B、12A-12B、13A-13B、14A-14B、15、16、17、18、19、20、21和22A-22B圖的任何描述，以及方法的其他部分以及本發明實施例提供的例示性圖式都僅為例示性，並不意圖限制以下請求項中具體描述的內容。
請參照第1A、2和3圖，方法100包含方塊102，其中在基底202上方形成磊晶堆疊物204。磊晶堆疊物204包含在交替配置中垂直堆疊的第一半導體層206和第二半導體層208。工件200顯示於第2圖中。工件200包含基底202，基底202可為半導體基底，例如矽基底。基底202可包含各種層，包含形成於半導體基底上的導電層或絕緣層。如本領域已知，依據設計需求，基底202可包含各種摻雜配置。舉例來說，不同的摻雜輪廓(例如n型井、p型井)可形成於基底202設計用於不同裝置類型(例如n型全繞式閘極電晶體和p型全繞式閘極電晶體)的區域中。合適的摻雜可包含摻雜物的離子佈植及/或擴散製程。基底202可在提供不同裝置類型的區域之間具有隔離部件。基底202也可包含其他半導體，例如鍺、碳化矽(SiC)、矽鍺(SiGe)或鑽石。或者，基底202可包含化合物半導體及/或合金半導體。再者，基底202可選擇性地包含磊晶層(epi-layer)，可為應變基底以增強效能，基底202可包含絕緣層上覆矽(silicon-on-insulator，SOI)結構及/或具有其他合適的增強部件。在方法100的一實施例中，進行抗擊穿(anti-punch through，APT)佈植。舉例來說，可對裝置的通道區下方的區域進行抗擊穿佈植，以防止擊穿或不想要的擴散。
磊晶堆疊物204包含第一半導體層206和第二半導體層208，第一半導體層206設置於第二半導體層208之間。磊晶堆疊物204也可被稱為堆疊物層。如第2圖所示，第一半導體層206和第二半導體層208沿Z方向交替且磊晶沉積，使得第一半導體層206和第二半導體層208交錯。第一半導體層206和第二半導體層208的組成不同。在一實施例中，第一半導體層206可由矽鍺(SiGe)形成，且第二半導體層208可由矽(Si)形成。然而，可能有其他實施例，這些其他實施例提供具有不同氧化速率及/或蝕刻選擇性的第一半導體組成和第二半導體組成。舉例來說，第一半導體層206和第二半導體層208可包含其他材料(例如鍺)、化合物半導體(例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、合金半導體(例如SiGe、GaAsP、AlInAs、AlGaAs、InGaAs、GaInP及/或GaInAsP)或前述之組合。舉例來說，磊晶堆疊物204的各層的磊晶成長可透過分子束磊晶(molecular beam epitaxy，MBE)製程、金屬有機化學氣相沉積(metalorganic chemical vapor deposition，MOCVD)製程及/或其他合適的磊晶成長製程進行。在一些實施例中，磊晶成長層例如第二半導體層208包含與基底202相同的材料。在一些實施例中，第一半導體層206和第二半導體層208大致不含摻雜物(即具有外來摻雜物濃度在約0cm-3 至約1x1017 cm-3 )。舉例來說，在磊晶成長製程期間不意圖進行摻雜。
可以注意的是，第2圖及其他圖式顯示交替排列的3層第一半導體層206和3層第二半導體層208，顯示的數量僅為顯示目的，並不意圖限制請求項中具體描述的內容。應當理解的是，任何數量的磊晶層可形成於磊晶堆疊物204中。層的數量取決於所期望之工件200的通道元件的數量。在一些實施例中，第二半導體層208的數量在2與10之間。
在一些實施例中，每個第一半導體層206具有厚度在約2nm至約6nm的範圍中，在一特定範例中，例如3nm。第一半導體層206在厚度上可大致一致。在一些實施例中，每個第二半導體層208具有厚度在約6nm至約12nm的範圍中，在一特定範例中，例如9nm。在一些實施例中，磊晶堆疊物204的第二半導體層208在厚度上可大致一致。如以下更詳細描述，第二半導體層208或第二半導體層208的一部分可作為後續形成的多閘極裝置的通道元件，且依據裝置效能考量來選擇第二半導體層208的厚度。可最終移除通道區中的第一半導體層206，且第一半導體層206可用以定義後續形成的多閘極裝置的相鄰通道區之間的垂直距離，而依據裝置效能考量來選擇第一半導體層206的厚度。因此，第一半導體層206也可被稱為犧牲層，而第二半導體層208也可被稱為通道層。
請參照第1A、3、4A、4B、5A和5B圖，方法100包含方塊104，其中從磊晶堆疊物204形成鰭元件211。請參照第3圖，在工件200上方沉積第一頂部硬遮罩層210。第一頂部硬遮罩層210可為單一層或多層。在一些實施例中，第一頂部硬遮罩層210可包含氧化矽、氮化矽、氮氧化矽、氮碳氧化矽、碳化矽或前述之組合。在第一頂部硬遮罩層210為多層的實施例中，第一頂部硬遮罩層210可包含沉積於磊晶堆疊物上的氧化矽層及沉積於氧化矽層上的氮化矽層。在圖案化製程中使用第一頂部硬遮罩層210，以將磊晶堆疊物204圖案化，以形成鰭元件211，如第4A和4B圖所示。舉例來說，圖案化製程可包含微影製程(例如光微影或電子束微影)，微影製程可更包含光阻塗佈(例如旋塗)、軟烤、遮罩對準、曝光、曝光後烘烤、光阻顯影、清洗、乾燥(例如旋乾及/或硬烤)、其他合適的微影技術及/或前述之組合。在一些實施例中，蝕刻製程可包含乾蝕刻(例如反應性離子蝕刻(reactive ion etching，RIE))、濕蝕刻及/或其他蝕刻方法。可對工件200進行圖案化製程，直到鰭元件211從基底202延伸。在一些實施例中，圖案化也蝕刻至基底202中，使得每個鰭元件211包含從基底202形成的下部以及從磊晶堆疊物204形成的上部。上部包含磊晶堆疊物204的每個磊晶層，即包含第一半導體層206和第二半導體層208。在一些實施例中，鰭元件211可雙重圖案化或多重圖案化製程製造。一般來說，雙重圖案化或多重圖案化製程結合了光微影和自對準製程，以創造具有較小間距的圖案，舉例來說，此圖案具有比使用單一直接光微影製程可獲得的間距更小的圖案。舉例來說，在一實施例中，犧牲層形成於基底上方，並透過使用光微影製程圖案化。間隔物透過使用自對準製程形成於圖案化犧牲層旁邊。接著，移除犧牲層，且可接著透過蝕刻磊晶堆疊物204來使用剩下的間隔物或心軸將鰭元件211圖案化。蝕刻製程可包含乾蝕刻、濕蝕刻、反應性離子蝕刻(RIE)及/或其他合適的製程。如第4A和4B圖所示，鰭元件211沿X軸在長度方向延伸。
請參照第5A和5B圖，在形成鰭元件211之後，在相鄰鰭元件211之間形成隔離部件212。隔離部件212也可被稱為淺溝槽隔離(shallow trench isolation，STI)部件。舉例來說，在一些實施例中，先在基底202上方沉積介電層，接著以介電材料填充鰭元件211之間的溝槽。在一些實施例中，介電層可包含氧化矽、氮化矽、氮氧化矽、氟摻雜矽酸鹽玻璃(fluorine-doped silicate glass，FSG)、低介電常數介電質、前述之組合及/或其他合適的材料。在各種實施例中，介電層可透過化學氣相沉積製程、次常壓化學氣相沉積(subatmospheric CVD，SACVD)製程、可流動化學氣相沉積製程、原子層沉積製程、物理氣相沉積(physical vapor deposition，PVD)製程及/或其他合適的製程來沉積。接著，例如透過化學機械研磨(chemical mechanical polishing，CMP)製程可將沉積的介電材料薄化及平坦化。可進一步透過乾蝕刻製程、濕蝕刻製程及/或前述之組合將平坦化的介電層凹陷，以形成隔離部件212。在凹陷之後，至少鰭元件211的上部突出於隔離部件212之上。在一些實施例中，介電層(及後續形成的隔離部件212)可包含多層結構，多層結構例如具有一個或多個襯墊層。
在不各別顯示的一些實施例中，方法100的方塊104也可形成介電鰭。與鰭元件211平行延伸的狹縫形成於隔離部件212的介電材料中，且接著介電鰭沉積於狹縫中。介電鰭材料不同於用來形成隔離部件212的介電材料，使得可選擇性蝕刻用來形成隔離部件212的介電材料，留下突出於隔離部件212之上的介電鰭。在一些實施例中，介電鰭材料可包含氮化矽、氮碳化矽、碳化矽、氧化鋁、氧化鋯或其他合適的材料。在應用介電鰭的實施例中，介電鰭設置於鰭元件211之間，並用以將相鄰裝置的源極/汲極部件隔開。介電鰭也可被稱為虛設鰭或混合鰭。在一些其他實施例中，介電鰭的上部可在閘極切割製程期間移除，並以不同或相似於介電鰭的反向材料部件取代。當形成介電鰭時，介電鰭限制了磊晶源極/汲極部件的形成，並防止相鄰磊晶源極/汲極部件之間產生不期望的合併。
請參照第1A、6A、6B、7A和7B圖，方法100包含方塊106，其中在鰭元件211的通道區30上方形成虛設閘極堆疊物220。在一些實施例中，採用閘極取代製程(或閘極後製製程)，其中虛設閘極堆疊物220作為金屬閘極堆疊物的佔位物，且將移除虛設閘極堆疊物220，並以金屬閘極堆疊物取代虛設閘極堆疊物220。可能為其他製程或配置。請參照第6A和6B圖，為了形成虛設閘極堆疊物220，在包含鰭元件211的工件200上方形成虛設介電層214，虛設介電層214可包含氧化矽、氮化矽或其他合適的介電材料，虛設介電層214先透過化學氣相沉積製程、次常壓化學氣相沉積(SACVD)製程、可流動化學氣相沉積製程、原子層沉積製程沉積。虛設介電層214可用以防止鰭元件211遭後續製程(例如形成虛設閘極堆疊物)損壞。接著，在虛設介電層214上方沉積虛設閘極材料層216，虛設閘極材料層216可由多晶矽形成。為了圖案化目的，可在虛設閘極材料層216上方沉積閘極頂部硬遮罩218。閘極頂部硬遮罩218可為單一層或多層，且可包含氧化矽、氮化矽、氮氧化矽、碳化矽、氮碳氧化矽或前述之組合。在閘極頂部硬遮罩218為多層的範例中，閘極頂部硬遮罩218包含沉積於虛設閘極材料層216上的氧化矽層以及沉積於氧化矽層上的氮化矽層。在圖案化製程中將閘極頂部硬遮罩218、虛設閘極材料層216和虛設介電層214圖案化，圖案化製程可包含微影製程(例如光微影或電子束微影)，微影製程可更包含光阻塗佈(例如旋塗)、軟烤、遮罩對準、曝光、曝光後烘烤、光阻顯影、清洗、乾燥(例如旋乾及/或硬烤)、其他合適的微影技術及/或前述之組合。在一些實施例中，蝕刻製程可包含乾蝕刻(例如反應性離子蝕刻)、濕蝕刻及/或其他蝕刻方法。
請參照第7A和7B圖，在基底202上方形成虛設閘極堆疊物220，且虛設閘極堆疊物220部分設置於鰭元件211上方。在圖案化之後，虛設閘極材料層216塑形為虛設電極。鰭元件211在虛設閘極堆疊物220下方的部分為鰭元件211的通道區30。虛設閘極堆疊物220也可定義與通道區30相鄰且在通道區30兩側的源極/汲極(source/drain，S/D)區40。如第7A圖所示，每個通道區30可沿X方向夾設於兩個源極/汲極區40之間。在一些實施例中，在形成虛設閘極堆疊物220之後，從鰭元件211的源極/汲極區40移除虛設介電層214。也就是說，移除虛設介電層214不被虛設閘極材料層216覆蓋的部分。移除製程可包含濕蝕刻、乾蝕刻及/或前述之組合。選擇蝕刻製程以選擇性蝕刻虛設介電層214，而大致不蝕刻鰭元件211、閘極頂部硬遮罩218和虛設閘極材料層216。如第7A圖所示，虛設閘極堆疊物220以一致的間距P設置於整個工件200上。
請參照第1A、8A和8B圖，方法100包含方塊108，其中在基底202上方(包含在虛設閘極堆疊物220上方)沉積閘極間隔層221。在一些實施例中，用以形成閘極間隔層221的間隙壁材料順應性沉積於工件200上方，包含沉積於虛設閘極堆疊物220的頂表面和側壁上方。本文使用的術語“順應性”為方便描述在各區域上方具有大致一致的厚度。閘極間隔層221可具有單一層結構或包含多層。在第8A和8B圖呈現的一些實施例中，閘極間隔層221單一層結構。閘極間隔層221可包含氧化矽、氮氧化矽、氮化矽、氮碳化矽、碳氧化矽、氮碳氧化矽、其他合適的介電材料或前述之組合。間隙壁材料可透過使用例如化學氣相沉積製程、次常壓化學氣相沉積(SACVD)製程、可流動化學氣相沉積製程、原子層沉積製程或其他合適的製程來沉積於虛設閘極堆疊物220上方。接著，在非等向性蝕刻製程中回蝕刻間隙壁材料，以形成閘極間隔層221。非等向性蝕刻製程暴露出鰭元件211與虛設閘極堆疊物220相鄰且未被虛設閘極堆疊物220覆蓋的部分(例如在源極/汲極區40中)。雖然未明確顯示於第8A和8B圖中，但是可透過此非等向性蝕刻製程部分或完全移除間隙壁材料在虛設閘極堆疊物220正上方的部分，而閘極間隔層221保留在虛設閘極堆疊物220的側壁上。
請參照第1A、9A和9B圖，方法100包含方塊110，其中在第一區10中的閘極間隔層221上方選擇性形成圖案層224，而暴露出在第二區20中的閘極間隔層221。在一些實施例中，圖案層224可由介電材料或聚合物材料形成。舉例來說，此介電材料可包含氧化矽、氮化矽、氮氧化矽、氮碳氧化矽、碳氧化矽或其他合適的介電材料。此聚合物材料可為光阻材料或聚醯亞胺。在一些實施例中，聚合物材料包含氟和碳在氟碳(CFx ，x=1、2或3)官能基或氯碳(CClx ，x=1、2或3)官能基的形式。圖案層224可透過使用化學氣相沉積(CVD)或旋塗製程來沉積。相較於第二區20中虛設閘極堆疊物220上未受保護/未被覆蓋的閘極間隔層221，第一區10中的圖案層224為第一區10中虛設閘極堆疊物220上的閘極間隔層221提供額外的耐蝕性。如以下將結合第12A和12B圖描述，此額外的耐蝕性導致在第一區10中有著較厚的第一閘極間隔層222，且在第二區20中有著較薄的第二閘極間隔層222’。
請參照第1A、10A和10B圖，方法100包含方塊112，其中使用第一閘極間隔層222、圖案層224和第二閘極間隔層222’作為蝕刻遮罩，以在鰭元件211中形成源極/汲極溝槽。在一些實施例中，將第一區10中的鰭元件211的源極/汲極區40凹陷，以形成第一源極/汲極溝槽227，並將第二區20中的鰭元件211的源極/汲極區40凹陷，以形成第二源極/汲極溝槽227’。雖然未明確顯示，可使用光微影製程及至少一硬遮罩來進行方塊112的操作。舉例來說，乾蝕刻製程可使用含氧氣體、含氟氣體(例如CF4 、SF6 、CH2 F2 、CHF3 及/或C2 H6 )、含氯氣體(例如Cl2 、CHCl3 、CCl4 及/或BCl3 )、含溴氣體(例如HBr及/或CHBr3 )、含碘氣體、其他合適的氣體及/或電漿及/或前述之組合。如以上結合方塊110所述，在方塊112的蝕刻中，在蝕刻第一閘極間隔層222之前，蝕刻並移除圖案層224。圖案層224的使用減緩了第一區10中的閘極間隔層221的薄化，導致第一閘極間隔層222比第二閘極間隔層222’更厚。在一些實施例中，第一閘極間隔層222具有第一厚度T1，且第二閘極間隔層222’具有第二厚度T2。在一些範例中，第一厚度T1比第二厚度T2大約0.5nm至5nm。由於第一閘極間隔層222與第二閘極間隔層222’之間的厚度差異以及橫跨整個工件200的一致間距P，第一區10中的第一源極/汲極溝槽227比第二區20中的第二源極/汲極溝槽227’更窄。第一區10中的第一源極/汲極溝槽227沿X方向具有第一間隔S1，且第二區20中的第二源極/汲極溝槽227’ 沿X方向具有第二間隔S2。第二間隔S2大於第一間隔S1。在一些範例中，第一間隔S1在約10nm與約40nm之間，且第二間隔S2在約15nm與約45nm之間。在第10A和10B圖呈現的一些實施例中，將鰭元件211的上部凹陷，以暴露出第一半導體層206和第二半導體層208。在一些實施例中，也將鰭元件211的下部的至少一部分凹陷。也就是說，第一源極/汲極溝槽227和第二源極/汲極溝槽227’可延伸至第一區10和第二區20中的最底部第一半導體層206下方。在方塊112的操作結束之後，鰭元件211的源極/汲極區40可變得與隔離部件212的頂表面齊平或低於隔離部件212的頂表面。
第11A、11B、12A和12B圖顯示方塊110和方塊112的操作的其他實施例。在這些其他實施例中，不在第一區10選擇性沉積圖案層224。取而代之的是，方塊108在工件200上方形成閘極間隔層221之後，各別形成第一區10中的第一源極/汲極溝槽227以及第二區20中的第二源極/汲極溝槽227’。如第11A和11B圖所示，第一光阻層226-1選擇性沉積於第一區10中，且在第一回蝕刻製程中非等向性蝕刻工件200的第二區20中的鰭元件211，以形成第二源極/汲極溝槽227’。之後，如第12A和12B圖所示，第二光阻層226-2選擇性沉積於第二區20中，且在第二回蝕刻製程中非等向性蝕刻工件200的第一區10中的鰭元件211，以形成第一源極/汲極溝槽227。第一回蝕刻製程和第二回蝕刻製程的參數可不同，使得蝕刻第二區20中閘極間隔層221的第一回蝕刻製程比蝕刻第一區10中閘極間隔層221的第二回蝕刻製程更快。舉例來說，相較於第二回蝕刻製程，第一回蝕刻製程可包含不同的蝕刻劑、較低的製程壓力、較大的偏壓、較大的電漿密度、更多的反應性蝕刻劑或較高的溫度。
請參照第1A、13A和13B圖，方法100包含方塊114，其中將第一區10和第二區20中的鰭元件211中的第一半導體層206凹陷，以形成內部間隙壁凹口228。在第13A和13B圖呈現的一些實施例中，將暴露於第一源極/汲極溝槽227和第二源極/汲極溝槽227’中的第一半導體層206選擇性且部分地凹陷，以形成內部間隙壁凹口228，而大致不蝕刻暴露的第二半導體層208。在第二半導體層208基本上由Si組成且第一半導體層206基本上由SiGe組成的一實施例中，第一半導體層206的選擇性凹陷可包含SiGe氧化製程及之後的SiGe氧化物移除。在這些實施例中，SiGe氧化製程可包含臭氧的使用。在一些實施例中，選擇性凹陷可為選擇性等向性蝕刻製程(例如選擇性乾蝕刻製程或選擇性濕蝕刻製程)，且透過蝕刻製程的持續時間控制第一半導體層206凹陷的程度。在一些實施例中，選擇性乾蝕刻製程可包含使用一個或多個氟基蝕刻劑，例如氟氣體或氫氟碳化物。如第13A和13B圖所示，內部間隙壁凹口228從第一區10中的第一源極/汲極溝槽227或從第二區20中的第二源極/汲極溝槽227’向內延伸。在一些實施例中，選擇性濕蝕刻製程可包含氟化氫(HF)或NH4 OH蝕刻劑。雖然第一區10中的第一閘極間隔層222和第二區20中的第二閘極間隔層222’具有不同的厚度，但是內部間隙壁凹口228具有橫跨工件200的大致一致的尺寸。也就是說，在第一區10中的內部間隙壁凹口228和第二區20中的內部間隙壁凹口228以大致相等量從第一半導體層206向內延伸。
請參照第1B、14A和14B圖，方法100包含方塊116，其中在內部間隙壁凹口228中形成內部間隙壁230。在一些實施例中，內部間隔層可透過使用化學氣相沉積、電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition，PECVD)、低壓化學氣相沉積、原子層沉積或其他合適的方法沉積於工件200上方。內部間隔層可由氧化鋁、氧化鋯、氧化鉭、氧化釔、氧化鈦、氧化鑭、氧化矽、氮碳化矽、氮碳氧化矽、碳氧化矽、低介電常數材料、其他合適的金屬氧化物或前述之組合形成。在一些實施例中，內部間隔層可順應性沉積於閘極頂部硬遮罩218的頂表面、第一閘極間隔層222的頂表面和側壁、第二閘極間隔層222’的頂表面和側壁、基底202暴露於第一源極/汲極溝槽227和第二源極/汲極溝槽227’中的部分上方。之後，可回蝕刻沉積的內部間隔層，以在內部間隙壁凹口228中形成內部間隙壁230。在回蝕刻製程中，移除在內部間隙壁凹口228之外的內部間隔層。
請參照第1B和15圖，方法100包含方塊118，其中在第一源極/汲極溝槽227和第二源極/汲極溝槽227’中形成磊晶源極/汲極部件232。由於磊晶源極/汲極部件232的形成在整個工件200中大致相同，因此在第一區10和第二區20中的磊晶源極/汲極部件232的形成共同顯示於第15圖中。雖然未各別顯示於本發明實施例的圖式中，磊晶源極/汲極部件232可包含用於n型裝置的n型磊晶源極/汲極部件以及用於p型裝置的p型磊晶源極/汲極部件。在一些實施例中，在先前或後續製程中，工件200中的n型裝置的n型磊晶源極/汲極部件可共同形成，而工件200中的p型裝置的p型磊晶源極/汲極部件可共同形成。磊晶源極/汲極部件232可透過使用合適的磊晶製程形成，例如化學氣相沉積技術(例如氣相磊晶(vapor-phase epitaxy，VPE)、超高真空化學氣相沉積(ultra-high vacuum CVD，UHV-CVD))、分子束磊晶(MBE)及/或其他合適的製程。n型磊晶源極/汲極部件的範例可包含Si、GaAs、GaAsP、SiP或其他合適的材料。n型磊晶源極/汲極部件可在磊晶製程期間透過引進摻雜物種來原位摻雜，摻雜物種包含n型摻雜物，例如磷或砷及/或包含前述之組合的其他合適摻雜物。如果n型磊晶源極/汲極部件並非原位摻雜，進行佈植製程(即接面佈植製程)，以對n型磊晶源極/汲極部件摻雜。p型磊晶源極/汲極部件的範例可包含Si、Ge、AlGaAs、硼摻雜SiGe或其他合適的材料。p型磊晶源極/汲極部件可在磊晶製程期間透過引進摻雜物種來原位摻雜，摻雜物種包含p型摻雜物，例如硼或BF2 及/或包含前述之組合的其他合適摻雜物。如果p型磊晶源極/汲極部件並非原位摻雜，進行佈植製程(即接面佈植製程)，以對p型磊晶源極/汲極部件摻雜。
請參照第1B和16圖，方法100包含方塊120，其中在磊晶源極/汲極部件232上方形成層間介電(interlayer dielectric，ILD)層236。由於層間介電層236的形成在整個工件200中大致相同，因此在第一區10和第二區20中的層間介電層236的形成共同顯示於第16圖中。在一些實施例中，接觸蝕刻停止層(contact etch stop layer，CESL)234先沉積於磊晶源極/汲極部件232上。在一些範例中，接觸蝕刻停止層234包含氮化矽層、氧化矽層、氮氧化矽層及/或本領域已知的其他材料。接觸蝕刻停止層234可透過原子層沉積、電漿輔助化學氣相沉積(PECVD)製程及/或其他合適的沉積或氧化製程形成。接著，層間介電層236沉積於接觸蝕刻停止層234上方。在一些實施例中，層間介電層236包含材料例如四乙氧基矽烷(tetraethylorthosilicate，TEOS)氧化物、未摻雜矽酸鹽玻璃或摻雜氧化矽，例如硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)、熔融石英玻璃(fused silica glass，FSG)、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼摻雜矽玻璃(boron doped silicon glass，BSG)及/或其他合適的介電材料。層間介電層236可透過電漿輔助化學氣相沉積製程或其他合適的沉積技術沉積。在一些實施例中，在形成層間介電層236之後，可將工件200退火，以改善層間介電層236的完整性。在層間介電層236的沉積及退火之後，可透過例如化學機械研磨(CMP)製程將工件200平坦化，以形成齊平的頂表面來進行進一步加工。
請參照第1B和17圖，方法100包含方塊122，其中移除虛設閘極堆疊物220，以形成閘極溝槽238。由於虛設閘極堆疊物220的移除在整個工件200中大致相同，因此在第一區10和第二區20中的虛設閘極堆疊物220的移除共同顯示於第17圖中。在所示的實施例中，蝕刻製程完全移除虛設閘極堆疊物220，以暴露出通道區30中的第一半導體層206和第二半導體層208。蝕刻製程可為乾蝕刻製程、濕蝕刻製程、其他合適的蝕刻製程或前述之組合。可選擇蝕刻製程，使得蝕刻製程對虛設閘極堆疊物220有選擇性，且大致不蝕刻接觸蝕刻停止層234和層間介電層236。在第17圖呈現的一些實施例中，從通道區30移除虛設閘極堆疊物220和虛設介電層214，以暴露出通道區30中的第一半導體層206和第二半導體層208。
請參照第1B和18圖，方法100包含方塊124，其中釋放鰭元件211的通道區中的第二半導體層208，以形成通道元件239。由於第二半導體層208的釋放在整個工件200中大致相同，因此在第一區10和第二區20中的第二半導體層208的釋放共同顯示於第18圖中。在所示的實施例中，蝕刻製程選擇性蝕刻第一半導體層206(即犧牲層)，而最小化蝕刻或不蝕刻第二半導體層208(即通道層)，且在一些實施例中，最小化蝕刻或不蝕刻第一閘極間隔層222、第二閘極間隔層222’及/或內部間隙壁230。可調整各種蝕刻參數，以達到第一半導體層206的選擇性蝕刻，例如蝕刻劑組成、蝕刻溫度、蝕刻溶液濃度、蝕刻時間、蝕刻壓力、電源功率、射頻偏壓電壓、射頻偏壓功率、蝕刻劑流量、其他合適的蝕刻參數或前述之組合。舉例來說，選擇用於蝕刻製程的蝕刻劑，使得蝕刻第一半導體層206的材料(在所示的實施例中為矽鍺)的速率大於蝕刻第二半導體層208的材料(在所示的實施例中為矽)的速率，即蝕刻劑對第一半導體層206的材料具有高蝕刻選擇性。蝕刻製程可為乾蝕刻製程、濕蝕刻製程、其他合適的蝕刻製程或前述之組合。在一些實施例中，乾蝕刻製程(例如反應性離子蝕刻製程)使用含氟氣體(例如SF6 )來選擇性蝕刻第一半導體層206(即犧牲層)。在一些實施例中，可調整含氟氣體對含氧氣體(例如O2 或O3 )的比例、蝕刻溫度及/或射頻功率，以選擇性蝕刻矽鍺或矽。在一些實施例中，濕蝕刻製程使用包含清氧化銨(NH4 OH)和水(H2 O)的蝕刻溶液，以選擇性蝕刻第一半導體層206(即犧牲層)。在一些實施例中，使用鹽酸(HCl)的化學氣相蝕刻製程選擇性蝕刻第一半導體層206(即犧牲層)。在方塊124的操作結束之後，通道區30中的第二半導體層208變得懸置，且可被稱為通道元件239。如以下將結合第22A和22B圖更詳細描述，第一區10中的通道元件239沿X方向的通道長度可大於第二區20中的通道元件239沿X方向的通道長度，因為在第一區10中具有較厚的第一閘極間隔層222。
請參照第1C和19圖，方法100包含方塊126，其中形成閘極介電層242圍繞通道元件239。由於閘極介電層242的形成在整個工件200中大致相同，因此在第一區10和第二區20中的閘極介電層242的形成共同顯示於第19圖中。在一些實施例中，界面層240可形成於通道元件239上，以提供通道元件239與閘極介電層242之間的黏著性。在一些實施例中，界面層240可包含介電材料，例如氧化矽、矽酸鉿或氮氧化矽。界面層240可透過化學氧化、熱氧化、原子層沉積(ALD)、化學氣相沉積(CVD)及/或其他合適的方法形成。閘極介電層242沉積於通道元件239上方並圍繞通道元件239，且閘極介電層242可包含一個或多個高介電常數介電材料。本文使用及描述的高介電常數介電材料包含具有高介電常數(例如大於熱氧化矽的介電常數(~3.9))的介電材料。閘極介電層242的範例高介電常數介電材料可包含TiO2 、HfZrO、Ta2 O3 、HfSiO4 、ZrO2 、ZrSiO2 、LaO、AlO、ZrO、TiO、Ta2 O5 、Y2 O3 、SrTiO3 (STO)、BaTiO3 (BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3 (BST)、Al2 O3 、Si3 N4 、氮氧化物 (SiON)、其他高介電常數介電材料或前述之組合。閘極介電層242可透過原子層沉積、物理氣相沉積(PVD)、化學氣相沉積、氧化及/或其他合適的方法形成。
請參照第1C和20圖，方法100包含方塊128，其中形成閘極堆疊物244。由於閘極堆疊物244的形成在整個工件200中大致相同，因此在第一區10和第二區20中的閘極堆疊物244的形成共同顯示於第20圖中。雖然未各別顯示，閘極堆疊物244可包含一個或多個功函數層及一個或多個金屬填充層。在一些實施例中，不同的功函數層堆疊物可形成於n型裝置區和p型裝置區中。在這些實施例中，雖然n型裝置區和p型裝置區可分享特定的共用功函數層，但是n型裝置區可包含不存在於p型裝置區中的一個或多個功函數層。相似地，在其他實施例中，p型裝置區可包含不存在於n型裝置區中的一個或多個功函數層。p型功函數層可包含任何合適的p型功函數材料，例如TiN、TaN、TaSN、Ru、Mo、Al、WN、WCN、ZrSi2 、MoSi2 、TaSi2 、NiSi2 、其他p型功函數材料或前述之組合。n型功函數層可包含任何合適的n型功函數材料，例如Ti、Al、Ag、Mn、Zr、TiAl、TiAlC、TaC、TaCN、TaSiN、TaAl、TaAlC、TaSiAlC、TiAlN、其他n型功函數材料或前述之組合。應當注意的是，p型功函數材料不限於使用在p型裝置區中，且n型功函數材料不限於使用在n型裝置區中。p型功函數層和n型功函數層可應用於n型裝置區和p型裝置區中，以達到所期望的臨界電壓。在一些實施例中，閘極堆疊物244可包含一個或多個金屬填充層。舉例來說，化學氣相沉積製程或物理氣相沉積製程在n型功函數層和p型功函數層上沉積一個或多個金屬填充層，使得金屬填充層填充了閘極溝槽238的任何剩下部分。金屬填充層可包含合適的導電材料，例如Al、W及/或Cu。金屬填充層可額外地或共同地包含其他金屬、金屬氧化物、金屬氮化物、其他合適的材料或前述之組合。
請參照第1C和21圖，方法100包含方塊130，其中將工件200平坦化，以提供水平表面。由於方塊130的平坦化在整個工件200中大致相同，因此在第一區10和第二區20中的平坦化共同顯示於第21圖中。在一些實施例中，進行平坦化，以移除在工件200上方多餘的界面層240、閘極介電層242以及閘極堆疊物244。舉例來說，平坦化可包含化學機械研磨製程，且可進行平坦化直到層間介電層236的頂表面與閘極堆疊物244的頂表面大致齊平。
請參照第22A和22B圖，在完成方塊130的操作之後，第22A圖所示的第一全繞式閘極電晶體250可形成於工件200的第一區10中，且第22B圖所示的第二全繞式閘極電晶體260可形成於工件200的第二區20中。如第22A圖所示，有著較大的第一厚度T1的第一閘極間隔層222使得第一通道元件239-1沿X方向具有第一寬度W1。由於第一閘極間隔層222較厚，因此在第一區10中的每個閘極堆疊物244包含第一閘極頂部部件244A，第一閘極頂部部件244A設置於最頂部通道元件239及第一下方閘極部件244B上，每個第一下方閘極部件244B夾設/設置於兩相鄰通道元件239之間。第一閘極頂部部件244A包含第一閘極寬度L1，且每個第一下方閘極部件244B包含第二閘極寬度L2。在第一區10中的磊晶源極/汲極部件232具有第二寬度W2。由於虛設閘極間距P橫跨工件200為一致的，因此間距P等於第一區10中的第一寬度W1和第二寬度W2的總和。在一些實施例中，間距P在約30nm與約60nm之間，第一寬度W1在約16nm與約46nm之間，第二寬度W2在約9nm與約40nm之間，第一閘極寬度L1在約5nm與約20nm之間，且第二閘極寬度L2在約6nm與約30nm之間。如第22B圖所示，有著較小的第二厚度T2的第二閘極間隔層222’使得第二通道元件239-2沿X方向具有第三寬度W3。在第二區20中的每個閘極堆疊物244包含第二閘極頂部部件244C，第二閘極頂部部件244C設置於最頂部通道元件239及第二下方閘極部件244D上，每個第二下方閘極部件244D夾設/設置於兩相鄰通道元件239之間。第二閘極頂部部件244C包含第三閘極寬度L3，且每個第二下方閘極部件244D包含第四閘極寬度L4。在第二區20中的磊晶源極/汲極部件232具有第四寬度W4。由於虛設閘極間距P橫跨工件200為一致的，因此間距P等於第二區20中的第三寬度W3和第四寬度W4的總和。在一些實施例中，間距P在約30nm與約60nm之間，第三寬度W3在約15nm與約45nm之間，第四寬度W4在約10nm與約40nm之間，第三閘極寬度L3在約5nm與約20nm之間，且第四閘極寬度L4在約5nm與約20nm之間。在第22B圖顯示的實施例中，第三閘極寬度L3大致等於第四閘極寬度L4。
可以看到的是，除了第一閘極頂部部件244A，第一全繞式閘極電晶體250的特徵在於第二閘極寬度L2。第二全繞式閘極電晶體260的特徵在於第三閘極寬度L3。在第22A和22B圖呈現的實施例中，第二閘極寬度L2比第三閘極寬度L3更大約1nm與約10nm之間。已觀察到的是，全繞式閘極電晶體的漏電流可隨著閘極寬度增加而降低，且全繞式閘極電晶體的臨界電壓可隨著全繞式閘極電晶體的漏電流降低而增加。由於第一全繞式閘極電晶體250的第二閘極寬度L2大於第二全繞式閘極電晶體260的第三閘極寬度L3，因此第一全繞式閘極電晶體250具有比第二全繞式閘極電晶體260更小的漏電流及更大的臨界電壓。在一些範例中，第一全繞式閘極電晶體250具有第一臨界電壓(VT1)，且第二全繞式閘極電晶體260具有第二臨界電壓(VT2)。透過使用第一區10中的第一全繞式閘極電晶體250和第二區20中的第二全繞式閘極電晶體260，依據本發明實施例的工件200可包含有著不同臨界電壓的全繞式閘極電晶體，即第一臨界電壓(VT1)和第二臨界電壓(VT2)。
請參照第1C圖，方法100包含方塊132，其中進行進一步的製程。可進行製造，以繼續工件200的製造。舉例來說，可形成各種接點，以有利於工件200中的全繞式閘極電晶體的操作。舉例來說，一個或多個層間介電層(相似於層間介電層236)以及接觸蝕刻停止層可形成於基底202上方(特別來說，形成於層間介電層236和閘極堆疊物244上方)。接著，接點可形成於層間介電層236中，及/或層間介電層設置於層間介電層236上方。舉例來說，接點對應電性及/或物理耦接閘極堆疊物244，且接點對應電性及/或物理耦接至全繞式閘極電晶體的源極/汲極區。由於第一區10中的磊晶源極/汲極部件232比在第二區20中的磊晶源極/汲極部件232更窄(沿X方向，如第22A和22B圖所示)，因此第一區10中的第一全繞式閘極電晶體250的源極/汲極接點可比第二區20中的第二全繞式閘極電晶體260的源極/汲極接點更窄。接點包含導電材料，例如鋁、鋁合金(例如鋁/銀/銅合金)、銅、銅合金、鈦、氮化鈦、鉭、氮化鉭、鎢、多晶矽、金屬矽化物、其他合適的金屬或前述之組合。在一些實施例中，金屬矽化物層可形成於磊晶源極/汲極部件232與源極/汲極接點之間的界面處。金屬矽化物可包含矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀或前述之組合。在一些實施例中，設置於層間介電層236上方的層間介電層及接點(例如延伸通過層間介電層236及/或其他層間介電層)為多層互連(multilayer interconnect，MLI)結構的一部分。
在一例示性方面，本發明實施例為有關於半導體裝置。半導體裝置包含在第一裝置區中的第一複數個全繞式閘極(GAA)裝置以及在第二裝置區中的第二複數個全繞式閘極裝置。第一複數個全繞式閘極裝置的每一者包含沿第一方向延伸的第一垂直堆疊通道元件以及在第一垂直堆疊通道元件上方並圍繞第一垂直堆疊通道元件的第一閘極結構。第二複數個全繞式閘極裝置的每一者包含沿第二方向延伸的第二垂直堆疊通道元件以及在第二垂直堆疊通道元件上方並圍繞第二垂直堆疊通道元件的第二閘極結構。第一複數個全繞式閘極裝置的每一者包含一第一通道長度，且第二複數個全繞式閘極裝置的每一者包含小於第一通道長度的第二通道長度。
在一些實施例中，每個第一閘極結構包含設置於第一垂直堆疊通道元件的最頂部通道元件上方的第一閘極頂部部件，以及設置於第一垂直堆疊通道元件的兩相鄰通道元件之間的複數個第一下方閘極部件。每個第二閘極結構包含設置於第二垂直堆疊通道元件的最頂部通道元件上方的第二閘極頂部部件以及設置於第二垂直堆疊通道元件的兩相鄰通道元件之間的複數個第二下方閘極部件。第一閘極頂部部件包含沿第一方向的第一長度，第二閘極頂部部件包含沿第二方向的第二長度，且第一長度和第二長度大致相等。在一些實施例中，複數個第一下方閘極部件的每一者包含沿第一方向的第三長度，複數個第二下方閘極部件的每一者包含沿第二方向的第四長度，且第三長度大於第四長度。在一些實施例中，第四長度大致等於第一長度。在一些實施例中，第三長度在約6nm與約30nm之間，其中第四長度在約5nm與約20nm之間。在一些實施例中，第一複數個全繞式閘極裝置的每一者更包含沿第一閘極頂部部件設置的第一閘極間隙壁，且第二複數個全繞式閘極裝置的每一者更包含沿第二閘極頂部部件設置的第二閘極間隙壁。在這些實施例中，第一閘極間隙壁包含第一厚度，且第二閘極間隙壁包含小於第一厚度的第二厚度。在一些範例中，第一厚度與第二厚度之間的差異在約0.5nm與約5nm之間。在一些範例中，第一複數個全繞式閘極裝置包含第一閘極間距，第二複數個全繞式閘極裝置包含與第一閘極間距相等的第二閘極間距。在一些實施例中，第一複數個全繞式閘極裝置的每一者包含第一源極/汲極部件，第二複數個全繞式閘極裝置的每一者包含第二源極/汲極部件，且第一源極/汲極部件沿第一方向的厚度小於第二源極/汲極部件的厚度。在一些實施例中，第一複數個全繞式閘極裝置的每一者包含第一臨界電壓，第二複數個全繞式閘極裝置的每一者包含小於第一臨界電壓的第二臨界電壓。
在另一例示性方面，本發明實施例為有關於半導體裝置。半導體裝置包含在第一裝置區中的第一複數個全繞式閘極(GAA)裝置以及在第二裝置區中的第二複數個全繞式閘極裝置。第一複數個全繞式閘極裝置的每一者包含沿第一方向延伸的第一垂直堆疊通道元件、設置於第一垂直堆疊通道元件的最頂部通道元件上方的第一閘極頂部部件及設置於第一垂直堆疊通道元件的兩相鄰通道元件之間的複數個第一下方閘極部件。第二複數個全繞式閘極裝置的每一者包含沿第二方向延伸的第二垂直堆疊通道元件、設置於第二垂直堆疊通道元件的最頂部通道元件上方的第二閘極頂部部件及設置於第二垂直堆疊通道元件的兩相鄰通道元件之間的複數個第二下方閘極部件。第一閘極頂部部件包含沿第一方向的第一長度，第二閘極頂部部件包含沿第二方向的第二長度，其中第一長度和第二長度大致相等。在一些實施例中，複數個第一下方閘極部件的每一者包含沿第一方向的第三長度，且複數個第二下方閘極部件的每一者包含沿第二方向的第四長度。第三長度大於第四長度。
在一些實施例中，第四長度大致等於第一長度。在一些實施例中，第一複數個全繞式閘極裝置的每一者更包含沿第一閘極頂部部件設置的第一閘極間隙壁，且第二複數個全繞式閘極裝置的每一者更包含沿第二閘極頂部部件設置的第二閘極間隙壁。第一閘極間隙壁包含第一厚度，且第二閘極間隙壁包含小於第一厚度的第二厚度。在一些實施例中，第一複數個全繞式閘極裝置包含第一閘極間距，第二複數個全繞式閘極裝置包含與第一閘極間距相等的第二閘極間距。在一些實施例中，第一複數個全繞式閘極裝置的每一者包含第一源極/汲極部件，第二複數個全繞式閘極裝置的每一者包含第二源極/汲極部件，且第一源極/汲極部件沿第一方向的厚度小於第二源極/汲極部件的厚度。
在另一例示性方面，本發明實施例為有關於半導體裝置的製造方法。此方法包含在基底上形成堆疊物層，堆疊物層包含交錯的複數個第一半導體層和複數個第二半導體層；從基底的第一區的堆疊物層形成第一複數個鰭元件；從基底的第二區的堆疊物層形成第二複數個鰭元件；在第一複數個鰭元件上方形成第一複數個虛設閘極堆疊物；在第二複數個鰭元件上方形成第二複數個虛設閘極堆疊物；在第一複數個虛設閘極堆疊物和第二複數個虛設閘極堆疊物上方沉積間隔層；在沉積於第一複數個虛設閘極堆疊物上方的間隔層上方選擇性沉積聚合物層，且聚合物層不覆蓋設置於第二複數個虛設閘極堆疊物上方的間隔層；以及蝕刻在第一複數個虛設閘極堆疊物和第二複數個虛設閘極堆疊物上方的間隔層。
在一些實施例中，聚合物層包含碳和氟。在一些實施例中，蝕刻間隔層的步驟包含在第一複數個虛設閘極堆疊物上方形成第一間隔層；以及在第二複數個虛設閘極堆疊物上方形成第二間隔層。第一間隔層包含第一厚度，且第二間隔層包含第二厚度。第一厚度大於第二厚度。在一些範例中，第一厚度與第二厚度之間的差異在約0.5nm與約5nm之間。在一些實施例中，此方法可更包含在第一區中形成第一複數個源極/汲極溝槽，以暴露出第一複數個鰭元件的側壁；在第二區中形成第二複數個源極/汲極溝槽，以暴露出第二複數個鰭元件的側壁；以及在第一複數個鰭元件和第二複數個鰭元件中部分蝕刻複數個第二半導體層，以形成複數個內部間隙壁凹口。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更加了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
10:第一區 20:第二區 30:通道區 40:源極/汲極區 100:方法 102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132:方塊 200:工件 202:基底 204:磊晶堆疊物 206:第一半導體層 208:第二半導體層 210:第一頂部硬遮罩層 211:鰭元件 212:隔離部件 214:虛設介電層 216:虛設閘極材料層 218:閘極頂部硬遮罩 220:虛設閘極堆疊 221:閘極間隔層 222:第一閘極間隔層 222’:第二閘極間隔層 224:圖案層 226-1:第一光阻層 226-2:第二光阻層 227:第一源極/汲極溝槽 227’:第二源極/汲極溝槽 228:內部間隙壁凹口 230:內部間隙壁 232:磊晶源極/汲極部件 234:接觸蝕刻停止層 236:層間介電層 238:閘極溝槽 239:通道元件 239-1:第一通道元件 239-2:第二通道元件 240:界面層 242:閘極介電層 244:閘極堆疊物 244A:第一閘極頂部部件 244B:第一下方閘極部件 244C:第二閘極頂部部件 244D:第二下方閘極部件 250:第一全繞式閘極電晶體 260:第二全繞式閘極電晶體 L1:第一閘極寬度 L2:第二閘極寬度 L3:第三閘極寬度 L4:第四閘極寬度 P:間距 S1:第一間隔 S2:第二間隔 T1:第一厚度 T2:第二厚度 W1:第一寬度 W2:第二寬度 W3:第三寬度 W4:第四寬度
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是，根據本產業的標準慣例，圖示中的各種部件(feature)並未必按照比例繪製。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。 第1A、1B和1C圖共同顯示依據本發明實施例的一個或多個方面，形成具有多裝置區域的方法的流程圖。 第2、3、4A-4B、5A-5B、6A-6B、7A-7B、8A-8B、9A-9B、10A-10B、11A-11B、12A-12B、13A-13B、14A-14B、15、16、17、18、19、20、21和22A-22B圖顯示依據本發明實施例的一個或多個方面，依照第1A-1C圖的方法，在製造過程期間工件的剖面示意圖。
10:第一區
200:工件
202:基底
222:第一閘極間隔層
230:內部間隙壁
232:磊晶源極/汲極部件
234:接觸蝕刻停止層
239-1:第一通道元件
240:界面層
242:閘極介電層
244:閘極堆疊物
244A:第一閘極頂部部件
244B:第一下方閘極部件
250:第一全繞式閘極電晶體
L1:第一閘極寬度
L2:第二閘極寬度
P:間距
T1:第一厚度
W1:第一寬度
W2:第二寬度

Claims (20)

  1. 一種半導體裝置，包括: 一第一複數個全繞式閘極裝置，在一第一裝置區中，其中該第一複數個全繞式閘極裝置的每一者包括: 一第一垂直堆疊通道元件，沿一第一方向延伸；及 一第一閘極結構，在該第一垂直堆疊通道元件上方並圍繞該第一垂直堆疊通道元件；以及 一第二複數個全繞式閘極裝置，在一第二裝置區中，其中該第二複數個全繞式閘極裝置的每一者包括: 一第二垂直堆疊通道元件，沿一第二方向延伸；及 一第二閘極結構，在該第二垂直堆疊通道元件上方並圍繞該第二垂直堆疊通道元件，其中該第一複數個全繞式閘極裝置的每一者包括一第一通道長度，其中該第二複數個全繞式閘極裝置的每一者包括小於該第一通道長度的一第二通道長度。
  2. 如請求項1之半導體裝置， 其中該第一閘極結構包括: 一第一閘極頂部部件，設置於該第一垂直堆疊通道元件的一最頂部通道元件上方；及 複數個第一下方閘極部件，設置於該第一垂直堆疊通道元件的兩相鄰通道元件之間； 其中該第二閘極結構包括: 一第二閘極頂部部件，設置於該第二垂直堆疊通道元件的一最頂部通道元件上方；及 複數個第二下方閘極部件，設置於該第二垂直堆疊通道元件的兩相鄰通道元件之間，其中該第一閘極頂部部件包括沿該第一方向的一第一長度，其中該第二閘極頂部部件包括沿該第二方向的一第二長度，且該第一長度和該第二長度大致相等。
  3. 如請求項2之半導體裝置，其中該複數個第一下方閘極部件的每一者包括沿該第一方向的一第三長度，其中該複數個第二下方閘極部件的每一者包括沿該第二方向的一第四長度，其中該第三長度大於該第四長度。
  4. 如請求項3之半導體裝置，其中該第四長度大致等於該第一長度。
  5. 如請求項3之半導體裝置，其中該第三長度在約6nm與約30nm之間，其中該第四長度在約5nm與約20nm之間。
  6. 如請求項3之半導體裝置，其中該第一複數個全繞式閘極裝置的每一者更包括沿該第一閘極頂部部件設置的一第一閘極間隙壁，其中該第二複數個全繞式閘極裝置的每一者更包括沿該第二閘極頂部部件設置的一第二閘極間隙壁，其中該第一閘極間隙壁包括一第一厚度，其中該第二閘極間隙壁包括小於該第一厚度的一第二厚度。
  7. 如請求項6之半導體裝置，其中該第一厚度與該第二厚度之間的差異在約0.5nm與約5nm之間。
  8. 如請求項1之半導體裝置，其中該第一複數個全繞式閘極裝置包括一第一閘極間距，其中該第二複數個全繞式閘極裝置包括與該第一閘極間距相等的一第二閘極間距。
  9. 如請求項1之半導體裝置，其中該第一複數個全繞式閘極裝置的每一者包括一第一源極/汲極部件，其中該第二複數個全繞式閘極裝置的每一者包括一第二源極/汲極部件，其中該第一源極/汲極部件沿該第一方向的厚度小於該第二源極/汲極部件的厚度。
  10. 如請求項1之半導體裝置，其中該第一複數個全繞式閘極裝置的每一者包括一第一臨界電壓，其中該第二複數個全繞式閘極裝置的每一者包括小於該第一臨界電壓的一第二臨界電壓。
  11. 一種半導體裝置，包括: 一第一複數個全繞式閘極裝置，在一第一裝置區中，其中該第一複數個全繞式閘極裝置的每一者包括: 一第一垂直堆疊通道元件，沿一第一方向延伸； 一第一閘極頂部部件，設置於該第一垂直堆疊通道元件的一最頂部通道元件上方；及 複數個第一下方閘極部件，設置於該第一垂直堆疊通道元件的兩相鄰通道元件之間；以及 一第二複數個全繞式閘極裝置，在一第二裝置區中，其中該第二複數個全繞式閘極裝置的每一者包括: 一第二垂直堆疊通道元件，沿一第二方向延伸； 一第二閘極頂部部件，設置於該第二垂直堆疊通道元件的一最頂部通道元件上方；及 複數個第二下方閘極部件，設置於該第二垂直堆疊通道元件的兩相鄰通道元件之間，其中該第一閘極頂部部件包括沿該第一方向的一第一長度，其中該第二閘極頂部部件包括沿該第二方向的一第二長度，且該第一長度和該第二長度大致相等，其中該複數個第一下方閘極部件的每一者包括沿該第一方向的一第三長度，其中該複數個第二下方閘極部件的每一者包括沿該第二方向的一第四長度，其中該第三長度大於該第四長度。
  12. 如請求項11之半導體裝置，其中該第四長度大致等於該第一長度。
  13. 如請求項11之半導體裝置，其中該第一複數個全繞式閘極裝置的每一者更包括沿該第一閘極頂部部件設置的一第一閘極間隙壁，其中該第二複數個全繞式閘極裝置的每一者更包括沿該第二閘極頂部部件設置的一第二閘極間隙壁，其中該第一閘極間隙壁包括一第一厚度，其中該第二閘極間隙壁包括小於該第一厚度的一第二厚度。
  14. 如請求項11之半導體裝置，其中該第一複數個全繞式閘極裝置包括一第一閘極間距，其中該第二複數個全繞式閘極裝置包括與該第一閘極間距相等的一第二閘極間距。
  15. 如請求項11之半導體裝置，其中該第一複數個全繞式閘極裝置的每一者包括一第一源極/汲極部件，其中該第二複數個全繞式閘極裝置的每一者包括一第二源極/汲極部件，其中該第一源極/汲極部件沿該第一方向的厚度小於該第二源極/汲極部件的厚度。
  16. 一種半導體裝置的製造方法，包括: 在一基底上形成一堆疊物層，該堆疊物層包括交錯的複數個第一半導體層和複數個第二半導體層； 從該基底的一第一區的該堆疊物層形成一第一複數個鰭元件； 從該基底的一第二區的該堆疊物層形成一第二複數個鰭元件； 在該第一複數個鰭元件上方形成一第一複數個虛設閘極堆疊物； 在該第二複數個鰭元件上方形成一第二複數個虛設閘極堆疊物； 在該第一複數個虛設閘極堆疊物和該第二複數個虛設閘極堆疊物上方沉積一間隔層； 在沉積於該第一複數個虛設閘極堆疊物上方的該間隔層上方選擇性沉積一聚合物層，且該聚合物層不覆蓋設置於該第二複數個虛設閘極堆疊物上方的該間隔層；以及 蝕刻在該第一複數個虛設閘極堆疊物和該第二複數個虛設閘極堆疊物上方的該間隔層。
  17. 如請求項16之半導體裝置的製造方法，其中該聚合物層包括碳和氟。
  18. 如請求項16之半導體裝置的製造方法，其中蝕刻該間隔層的步驟包括: 在該第一複數個虛設閘極堆疊物上方形成一第一間隔層；以及 在該第二複數個虛設閘極堆疊物上方形成一第二間隔層，其中該第一間隔層包括一第一厚度，且該第二間隔層包括一第二厚度，其中該第一厚度大於該第二厚度。
  19. 如請求項18之半導體裝置的製造方法，其中該第一厚度與該第二厚度之間的差異在約0.5nm與約5nm之間。
  20. 如請求項16之半導體裝置的製造方法，更包括: 在該第一區中形成一第一複數個源極/汲極溝槽，以暴露出該第一複數個鰭元件的側壁； 在該第二區中形成一第二複數個源極/汲極溝槽，以暴露出該第二複數個鰭元件的側壁；以及 在該第一複數個鰭元件和該第二複數個鰭元件中部分蝕刻該複數個第二半導體層，以形成複數個內部間隙壁凹口。
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