TW202145570A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202145570A
TW202145570A TW110118765A TW110118765A TW202145570A TW 202145570 A TW202145570 A TW 202145570A TW 110118765 A TW110118765 A TW 110118765A TW 110118765 A TW110118765 A TW 110118765A TW 202145570 A TW202145570 A TW 202145570A
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Taiwan
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layer
epitaxial
block
gate
feature
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TW110118765A
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張榮宏
張羅衡
林志昌
陳仕承
江國誠
王志豪
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台灣積體電路製造股份有限公司
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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Abstract

根據本發明實施例的半導體裝置包含基底上的底介電部件，在底介電部件正上方的多個通道構件，包覆環繞每個通道構件的閘極結構，沿著第一方向將底介電部件夾在中間的兩個第一磊晶部件，以及沿著第一方向將多個通道構件夾在中間的兩個第二磊晶部件。

Description

半導體裝置
本發明實施例是關於半導體製造技術，特別是關於半導體裝置。
半導體積體電路（integrated circuit，IC）產業已經歷了指數型成長。積體電路材料和設計上的技術進展已產生了數個世代的積體電路，每一世代皆較前一世代具有更小且更複雜的電路。在積體電路演進的歷程中，當幾何尺寸（亦即使用生產製程可以產生的最小元件（或線））縮減時，功能密度（亦即單位晶片面積的互連裝置數量）通常也增加。這種尺寸微縮製程通常藉由提高生產效率及降低相關成本而提供一些效益。這樣的尺寸微縮也增加了加工和製造上的複雜度。
舉例來說，隨著積體電路技術朝更小的技術節點發展，已經引入多閘極裝置，以藉由增加閘極-通道耦合、降低截止狀態電流和降低短通道效應（short-channel effects，SCEs）來改善閘極控制。多閘極裝置通常是指具有閘極結構或其一部分設置在通道區的多於一側上方的裝置。鰭狀場效電晶體（Fin-like field effect transistors，FinFET）和多橋通道（multi-bridge channel，MBC）電晶體是多閘極裝置的範例，這些裝置已成為高效能和低漏電應用之受歡迎且有希望的候選者。鰭狀場效電晶體具有一側以上被閘極包覆之升高的通道（例如閘極包覆從基底延伸之半導體材料的「鰭片」的頂部和側壁）。多橋通道電晶體的閘極結構可以部分或全部圍繞通道區延伸，以提供對通道區兩側或更多側的連接。由於多橋通道電晶體的閘極結構環繞通道區，多橋通道電晶體也可以稱為環繞閘極電晶體（surrounding gate transistor，SGT）或全繞式閘極（gate-all-around，GAA）電晶體。多橋通道電晶體的通道區可以由奈米線、奈米片、其他奈米結構及/或其他合適的結構形成。通道區的形狀也給多橋通道電晶體替代名稱，例如奈米片電晶體或奈米線電晶體。隨著多閘極裝置中閘極結構與源極/汲極部件之間的間距縮減，閘極結構與源極/汲極部件之間的電容（有時稱為閘極-汲極電容（gate-drain capacitance，Cgd ））可能對裝置效能變得關鍵，特別是在高頻應用。因此，雖然傳統的多閘極結構通常足以滿足其預期目的，但並非在所有面向都令人滿意。
根據一些實施例提供半導體裝置。此半導體裝置包含在基底上的底介電部件；在底介電部件正上方的多個通道構件；包覆環繞每個通道構件的閘極結構；沿著第一方向將底介電部件夾在中間的兩個第一磊晶部件；以及沿著第一方向將多個通道構件夾在中間的兩個第二磊晶部件。
根據另一些實施例提供半導體裝置。此半導體裝置包含在基底上的底介電部件；在底介電部件正上方的多個通道構件；以及包覆環繞多個通道構件中的每一個之閘極結構，其中底介電部件設置在基底與閘極結構的底表面之間，並且其中底介電部件包含接縫。
根據又另一些實施例提供半導體裝置的形成方法。此半導體裝置的形成方法包含在基底上沉積底犧牲層；在底犧牲層上沉積底蓋層；在底蓋層上沉積堆疊，此堆疊由交錯的多個通道層與多個犧牲層形成；由基底、底犧牲層、底蓋層和堆疊形成鰭狀結構；在鰭狀結構的通道區上方形成虛設閘極堆疊；在虛設閘極堆疊上方形成間隔層；凹蝕鰭狀結構的源極/汲極區以暴露出底犧牲層、底蓋層和堆疊的側壁；選擇性地且部分地凹蝕多個犧牲層以形成內間隔凹槽；在內間隔凹槽中形成內間隔部件；以及用底介電部件置換底犧牲層。
以下內容提供許多不同實施例或範例，用於實施本發明實施例的不同部件。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用於限定本發明實施例。舉例來說，敘述中若提及第一部件形成於第二部件上或上方，可能包含形成第一部件和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一部件和第二部件之間，使得第一部件和第二部件不直接接觸的實施例。另外，本發明實施例在不同範例中可重複使用參考標號及/或字母。此重複是為了簡化和清楚之目的，並非代表所討論的不同實施例及/或組態之間有特定的關係。
此外，本文可能使用空間相對用語，例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」及類似的用語，這些空間相對用語係為了便於描述如圖所示之一個（些）元件或部件與另一個（些）元件或部件之間的關係。這些空間相對用語涵蓋使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），則在此所使用的空間相對形容詞也將依轉向後的方位來解釋。另外，當以「約」、「近似」和類似的用語描述數值或數值範圍時，除非另有規定，此用語欲涵蓋所述數值的+/-10%以內的數值。舉例來說，用語「約5 nm」涵蓋4.5 nm至5.5 nm的尺寸範圍。
本發明實施例總體上關於多閘極電晶體和製造方法，並且更具體地關於多閘極電晶體具有底介電層以降低閘極-汲極電容。
多閘極裝置包含在通道區的至少兩側上形成閘極結構的電晶體。多閘極裝置的範例包含具有鰭狀結構的鰭狀場效電晶體和具有多個通道構件的多橋通道電晶體。如前所述，多橋通道電晶體也可以被稱為環繞閘極電晶體、全繞式電晶體、奈米片電晶體或奈米線電晶體。這些多閘極裝置可以是n型或p型。多橋通道電晶體包含在通道區的四側上（例如圍繞通道區的一部分）形成閘極結構或閘極結構的一部分之任何裝置。根據本發明實施例的多橋通道裝置可以具有設置在奈米線通道構件、棒狀通道構件、奈米片通道構件、奈米結構通道構件、橋形通道構件及/或其他合適的通道構造中的通道區。在多橋通道電晶體中，由於通道區鄰近源極/汲極區，所以當磊晶源極/汲極部件延伸至低於閘極結構的底表面的高度時，可以在源極/汲極區中的磊晶源極/汲極部件和通道區中的閘極結構之間形成額外的閘極-汲極電容。另外，在通道區下方的塊狀基底中可能存在雜散摻質（stray dopants），進而產生漏電路徑。額外的閘極-汲極電容和漏電路徑都可能影響多橋通道電晶體的效能。
本發明實施例提供半導體裝置的實施例，其中底介電部件或底氧化物部件使通道區與塊狀基底絕緣。為了形成底介電部件或底氧化物部件，本發明實施例的方法在形成交替的半導體層的堆疊之前在基底上形成底犧牲層和底蓋層。在從基底、底犧牲層、底蓋層和堆疊形成鰭狀結構之後，將底犧牲層圖案化為底犧牲部件。本發明實施例的方法的操作用底介電部件替代底犧牲部件或將底犧牲部件氧化為底氧化物部件。本發明實施例的方法還包含在兩階段中形成磊晶源極/汲極部件的操作。先在源極/汲極凹槽中形成第一磊晶部件，以與底介電部件或底氧化物部件相接，第一磊晶部件可以由未摻雜的半導體材料形成。然後在第一磊晶部件上方形成第二磊晶部件，第二磊晶部件可以用n型或p型摻質重摻雜並且比第一磊晶部件更導電。底介電部件（或底氧化物部件）和磊晶源極/汲極部件的兩階段形成皆降低閘極汲極電容（Cgd ）和漏電。
現在將參照圖式更詳細地描述本發明實施例的各種面向。在這方面，第1圖和第18圖是繪示根據本發明實施例中的一些實施例之從工件形成半導體裝置的方法100和300的流程圖。方法100和300只是範例，並非用於將本發明實施例限制為方法100和300中明確說明的內容。可以在方法100和300之前、期間和之後提供額外的步驟，並且對於方法100的其他實施例，可以移動、替換或消除一些步驟。為了簡化，本文沒有詳細描述所有步驟。以下結合在根據方法100和300的不同製造階段之工件的局部剖面圖來描述方法100和300。以「A」結尾的圖繪示沿著X方向之工件200（或半導體裝置200）之局部剖面圖，X方向是虛設閘極堆疊或閘極結構的長度方向。以「B」結尾的圖繪示沿著Y方向的工件200（或半導體裝置200）的局部剖面圖，Y方向是鰭狀結構的長度方向。
參照第1圖和第2圖，方法100包含方框102，在工件200的基底202上沉積底犧牲層203。在一些實施例中，基底202可以是半導體基底，例如矽基底。基底202也可以包含其他半導體，例如鍺、碳化矽（SiC）、矽鍺（SiGe）或金剛石。或者，基底202可以包含化合物半導體及/或合金半導體。在描繪的實施例中，基底202是矽基底。為了便於參照，可以將基底202和將在基底202上形成的層或部件統稱為工件200。因為一完成生產製程就將工件200製造成半導體裝置200，所以根據內文需求，可以將工件200稱為半導體裝置200。此外，可以由工件200形成的例示性半導體裝置可以包含各種其他裝置和部件，例如其他類型的裝置，包含額外的電晶體、雙極接面電晶體（bipolar junction transistors）、電阻器、電容器、電感器、二極體、熔絲、靜態隨機存取記憶體（SRAM）及/或其他邏輯電路等，但為了更好地理解本發明實施例的發明構想而被簡化。
底犧牲層203可以包含半導體材料，例如矽鍺。在那些實施例中，底犧牲層203可以包含約10%至約50%的第一鍺含量。如將在以下描述的，底犧牲層203的第一鍺濃度允許選擇性地凹蝕具有不同鍺濃度的矽鍺犧牲層（將在以下描述）。在一些實施方式中，使用分子束磊晶（molecular beam epitaxy，MBE）製程、氣相磊晶（vapor-phase epitaxy，VPE）、超高真空化學氣相沉積（ultra-high vacuum CVD，UHV-CVD）、金屬有機化學氣相沉積（metalorganic chemical vapor deposition，MOCVD）製程及/或其他合適的磊晶成長製程在基底202上磊晶沉積底犧牲層203。在一些情況下，底犧牲層203形成為具有約8 nm至約10 nm的厚度。
參照第1圖和第2圖，方法100包含方框104，在底犧牲層203上沉積底蓋層205。底蓋層205包含與形成底犧牲層203的半導體材料不同的半導體材料。在一些實施例中，底蓋層205由矽形成。在一些實施方式中，使用分子束磊晶製程、氣相磊晶製程、超高真空化學氣相沉積製程、金屬有機化學氣相沉積製程及/或其他合適的磊晶成長製程在底犧牲層203上磊晶沉積底蓋層205。如將在以下描述的，底蓋層205用於將底犧牲層203與上覆層（例如堆疊中的犧牲層（將在以下描述））隔離。因此，底蓋層205可能需要約3 nm的最小厚度。同時，因為不打算將底蓋層205形成為通道構件，所以可能期望在後續製程中盡可能地移除底蓋層205。因此，底蓋層205的厚度可以不超過約4 nm，以有助於令人滿意地移除底蓋層205。由於這些原因，在一些實施例中，底蓋層205的厚度可以為約3 nm至約4 nm。
參照第1圖和第2圖，方法100包含方框106，在底蓋層205上沉積犧牲層206和通道層208的堆疊204。如第2圖所示，堆疊204中的犧牲層206和通道層208交替堆疊，使得通道層208交錯插入犧牲層206，反之亦然。犧牲層206和通道層208由不同的半導體材料形成，其被配置以允許選擇性地移除犧牲層206而大致不損傷通道層208。在一實施例中，犧牲層206包含矽鍺而通道層208包含矽。在此實施例中，犧牲層206包含第二鍺含量，其大於底犧牲層203的第一鍺含量。在一些情況下，第二鍺濃度為約30%至約45%。已經觀察到，鍺濃度的差異允許選擇性地且部分地凹蝕犧牲層206以在方框118形成內間隔凹槽228（如第6A圖所示），而僅最小程度地凹蝕底犧牲層203。雖然更高的第二鍺濃度可以進一步提高選擇性，但鍺濃度太高會影響犧牲層206中所得矽鍺的結晶度。作為範例，可以藉由分子束磊晶製程、氣相磊晶製程、超高真空化學氣相沉積製程、金屬有機化學氣相沉積製程及/或其他合適的磊晶成長製程來形成堆疊204中的犧牲層206和通道層208。
完全預想到用於犧牲層206和通道層208的其他半導體材料。在一些替代實施例中，犧牲層206和通道層208可以包含其他材料，例如鍺、化合物半導體，例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦、合金半導體，例如GaAsP、AlInAs、AlGaAs、InGaAs、GaInP及/或GaInAsP、或前述之組合。如所討論的，可以選擇犧牲層206和通道層208的材料，使得可以選擇性地移除或凹蝕犧牲層206，而大致不損傷通道層208。
應注意的是，如第2圖所示之交替設置三層犧牲層206和三層通道層208僅用於說明的目的，而非用於將本發明實施力限制於超出申請專利範圍具體引述的範圍。可以理解的是，可以在堆疊204中形成任何數量的犧牲層和通道層。這些層的數量取決於半導體裝置200之期望的通道構件的數量。在一些實施例中，通道層208的數量為2至10。在一些實施例中，所有犧牲層206可以具有大致均勻的第一厚度，並且所有通道層208可以具有大致均勻的第二厚度。第一厚度和第二厚度可以相同或不同。通道層208或通道層208的一部分可以作為後續形成的多閘極裝置的通道構件，並基於裝置效能考量來選擇每個通道層208的厚度。犧牲層206可以最終被移除並用於界定後續形成的多閘極裝置的相鄰通道區之間的垂直距離，並基於裝置效能考量來選擇每個犧牲層206的厚度。
參照第1圖和第3圖，方法100包含方框108，由堆疊204、底蓋層205、底犧牲層203和基底202形成鰭狀結構210。在方框108，使用微影製程和蝕刻製程來圖案化堆疊204、底蓋層205、底犧牲層203和基底202的一部分。微影製程可以包含塗佈光阻（例如旋轉塗佈（spin-on coating））、軟烘烤、遮罩對準、曝光、曝光後烘烤、顯影光阻、清洗（rinsing）、乾燥（例如旋轉乾燥及/或硬烘烤）、其他合適的微影製程及/或前述之組合。雖然未明確繪示，但可以在堆疊204上方形成一或多個硬遮罩層以促進光學微影製程。在一些實施方式中，可以在堆疊204上方沉積含氮硬遮罩層和含氧硬遮罩層。含氮硬遮罩層可以包含氮化矽或氮碳化矽。含氧硬遮罩層可以包含氧化矽或碳氧化矽。蝕刻製程可以包含乾式蝕刻（例如反應離子蝕刻（reactive ion etching，RIE））、濕式蝕刻及/或其他蝕刻方法。在一些實施方式中，可以使用雙重圖案化或多重圖案化製程來界定鰭狀結構，鰭狀結構的例如節距小於使用單一、直接光學微影製程可獲得的節距。舉例來說，在一實施例中，在基底上方形成材料層並使用光學微影製程將材料層圖案化。使用自對準製程在圖案化的材料層旁邊形成間隔物。然後，移除圖案化的材料層，接著可以使用剩餘的間隔物或心軸（mandrels），藉由蝕刻堆疊204、底蓋層205、底犧牲層203和基底202的一部分來圖案化鰭狀結構210。
參照第1圖和第3圖，方法100包含方框110，在鰭狀結構210之間的隔離部件212。在一些實施例中，可以在相鄰鰭狀結構210之間的溝槽211中沉積隔離部件212，以將鰭狀結構210彼此隔離。隔離部件212也可以稱為淺溝槽隔離（shallow trench isolation，STI）部件212。作為範例，在一些實施例中，先在基底202上方沉積用於隔離部件212的介電材料，以介電材料填充溝槽211。在一些實施例中，介電材料可以包含氧化矽、氮化矽、氮氧化矽、摻雜氟的矽酸鹽玻璃（fluorine-doped silicate glass，FSG）、低介電常數介電質、前述之組合及/或其他合適的材料。在各種範例中，可以藉由旋轉塗佈製程、化學氣相沉積製程、次常壓化學氣相沉積（subatmospheric CVD，SACVD）製程、可流動式化學氣相沉積（flowable CVD）製程、原子層沉積製程、物理氣相沉積（physical vapor deposition，PVD）製程及/或其他合適的製程來沉積介電層。然後，例如藉由化學機械研磨（chemical mechanical polishing，CMP）製程來薄化並平坦化沉積的介電材料。藉由乾式蝕刻製程、濕式蝕刻製程及/或前述之組合進一步凹蝕或拉回平坦化的介電層，以形成淺溝槽隔離部件212。在凹蝕之後，鰭狀結構210在淺溝槽隔離部件212上方升高。
參照第1圖、第3圖、第4A和4B圖，方法100包含方框112，在鰭狀結構210上方形成虛設閘極堆疊220。在第3、4A和4B圖所示之一些實施例中，虛設閘極堆疊220包含虛設介電層214和虛設電極層216。在那些實施例中，用於圖案化虛設閘極堆疊220的閘極頂部硬遮罩層218可以留在虛設電極層216的頂部上以保護虛設電極層216。在描繪的實施例中，閘極頂部硬遮罩層218可以包含氮化物硬遮罩層217和在氮化物硬遮罩層217上方的氧化物硬遮罩層219。在一些實施方式中，虛設介電層214可以包含氧化矽，虛設電極層216可以包含多晶矽，氮化物硬遮罩層217可以包含氮化矽或氮氧化矽，並且氧化物硬遮罩層219可以包含氧化矽。為了便於參照，虛設閘極堆疊220可以不僅用於指虛設介電層214、虛設電極層216，還可以指閘極頂硬遮罩層218（包含氮化物硬遮罩層217和氧化物硬遮罩層219）。虛設閘極堆疊220用作佔位元件以經歷各種製程，並在隨後的步驟中將被移除並由功能閘極結構取代。如第4A圖所示，虛設閘極堆疊220設置在鰭狀結構210的通道區10上方。每個通道區10沿著對準Y方向之鰭狀結構210的長度方向設置在兩個源極/汲極區20之間。可以使用化學氣相沉積製程、原子層沉積製程或合適的沉積製程來沉積虛設介電層214、虛設電極層216和閘極頂硬遮罩層218中的每一個。類似於鰭狀結構210，可以使用光學微影和蝕刻製程來圖案化虛設閘極堆疊220。
在第4A和4B圖所示之一些實施例中，在形成虛設閘極堆疊220之後，從鰭狀結構210的源極/汲極區20移除虛設介電層214。亦即，移除未被虛設電極層216覆蓋的虛設介電層214。移除製程可以包含濕式蝕刻、乾式蝕刻及/或前述之組合。選擇蝕刻製程以選擇性地蝕刻虛設介電層214，而大致上不蝕刻鰭狀結構210、閘極頂部硬遮罩層218和虛設電極層216。
參照第1圖、第4A和4B圖，方法100包含方框114，在工件200上方沉積閘極間隔層223。閘極間隔層223可以是單層或多層結構。第4A和4B圖繪示多層的範例，其中閘極間隔層223包含第一間隔層222和第二間隔層224。第一間隔層222和第二間隔層224順應性地（conformally）沉積在工件200上方，包含在虛設閘極堆疊220的頂表面和側壁。在本文中可以使用用語「順應性地」以方便描述在各個區域上方具有大致均勻厚度的層。第一間隔層222的介電常數低於第二間隔層224的介電常數，並且第二間隔層224比第一間隔層222更耐蝕刻。在一些實施例中，第一間隔層222可以包含氧化矽、碳氧化矽或合適的低介電常數介電材料。第二間隔層224可以包含氮碳化矽、氮化矽、氧化鋯、氧化鋁或合適的介電材料。可以使用例如化學氣相沉積製程、次常壓化學氣相沉積（SACVD）製程、可流動式化學氣相沉積製程、原子層沉積製程、物理氣相沉積製程或其他合適的製程在虛設閘極堆疊220上方沉積第一間隔層222和第二間隔層224。如第4B圖所示，閘極間隔層223不僅設置在通道區10中的虛設閘極堆疊220的側壁和頂表面上方，而且還設置在源極/汲極區20中的鰭狀結構210的側壁和頂表面上方。雖然未明確繪示於第4A和4B圖中，可以在非等向性蝕刻製程中回蝕刻閘極間隔層223，以從鰭狀結構210的頂表面之未被虛設閘極堆疊220覆蓋的部分移除閘極間隔層223，藉此暴露出源極/汲極區20。可以藉由這個非等向性蝕刻製程完全移除設置在虛設閘極堆疊220正上方之閘極間隔層223的部分，而閘極間隔層223保留在虛設閘極堆疊220的側壁上。
參照第1圖、第5A和5B圖，方法100包含方框116，凹蝕鰭狀結構210的源極/汲極區20。雖然未明確繪示，但可以使用光學微影製程和至少一個硬遮罩來進行方框116的操作。在一些實施例中，藉由乾式蝕刻或適當的蝕刻製程來蝕刻未被虛設閘極堆疊220和閘極間隔層223覆蓋之鰭狀結構210的源極/汲極區20，以形成源極/汲極凹槽226。舉例來說，乾式蝕刻製程可以實施含氧氣體、含氟氣體（例如CF4 、SF6 、CH2 F2 、CHF3 及/或C2 F6 ）、含氯氣體（例如Cl2 、CHCl3 、CCl4 及/或BCl3 ）、含溴氣體（例如HBr及/或CHBr3 ）、含碘氣體、其他合適的氣體及/或電漿、及/或前述之組合。在第5A和5B圖所示之一些實施例中，凹蝕鰭狀結構210的源極/汲極區20以暴露出犧牲層206和通道層208在源極/汲極凹槽226中的側壁。如第5A圖所示，在方框116的凹蝕繼續向下穿過底犧牲層203並延伸到基底202的一部分中。在這一點上，連續的底犧牲層203和底蓋層205在鰭狀結構210的通道區10中被劃分為底犧牲部件203和底蓋部件205。
參照第1圖、第6A和6B圖，方法100包含方框118，選擇性地且部分地蝕刻犧牲層206以形成內間隔凹槽228。在方框118，沿著Y方向選擇性地且部分地凹蝕暴露於源極/汲極凹槽226中的犧牲層206以形成內間隔凹槽228，而大致上不蝕刻閘極間隔層223、通道層208和底蓋部件205。在底犧牲部件203和犧牲層206都由矽鍺形成的實施例中，也可以凹蝕底犧牲部件203，雖然因為較低的鍺濃度而不過度凹蝕。如前所述，底犧牲部件203中較低的第一鍺濃度使其比具有較高第二鍺濃度的犧牲層206更慢地被蝕刻。在第6A圖所示之一些實施方式中，底犧牲部件203可以被凹蝕第一深度D1，並且每個犧牲層206可以被凹蝕第二深度D2。第二深度D2大於第一深度D1。在一些情況下，第一深度D1可以小於約1 nm，第二深度D2可以為約5 nm至約9 nm。第二深度D2是內間隔凹槽228的Y方向尺寸。在通道層208大致由Si組成且犧牲層206大致由SiGe組成的實施例中，犧牲層206的選擇性凹蝕可以包含SiGe氧化製程，然後是SiGe氧化物移除。在那些實施例中，SiGe氧化製程可以包含使用臭氧。在一些實施例中，選擇性凹蝕可以是選擇性等向蝕刻製程（例如選擇性乾式蝕刻製程或選擇性濕式蝕刻製程），並由蝕刻製程的持續時間來控制凹蝕犧牲層206的程度。在一些實施例中，選擇性乾式蝕刻製程可以包含使用一或多種基於氟的蝕刻劑，例如氟氣或氫氟碳化物（hydrofluorocarbons）。在一些實施例中，選擇性濕式蝕刻製程可以包含氟化氫（HF）或NH4 OH蝕刻劑。
參照第1圖、第7A和7B圖，方法100包含方框120，在內間隔凹槽228中形成內間隔部件230。在一些實施例中，在方框120的操作可以包含在工件200上方毯覆式沉積內間隔材料層，並回蝕刻內間隔材料層以內間隔部件230。內間隔材料層可以是單層或多層結構。在一些實施方式中，內間隔材料層的沉積可以使用化學氣相沉積、電漿輔助化學氣相沉積、低壓化學氣相沉積、原子層沉積或其他合適的方法。內間隔材料層可以包含金屬氧化物、氧化矽、氮碳氧化矽、氮化矽、氮氧化矽、富碳的氮碳化矽或低介電常數介電材料。這裡的金屬氧化物可以包含氧化鋁、氧化鋯、氧化鉭、氧化釔、氧化鈦、氧化鑭或其他合適的金屬氧化物。
然後，回蝕刻沉積的內間隔材料層，以從通道層208的側壁移除內間隔材料層，以獲得在內間隔凹槽228中的內間隔部件230。在方框120，還可以從虛設閘極堆疊220、閘極間隔層223和隔離部件212的頂表面移除內間隔材料層。在一些實施例中，選擇內間隔材料層的成分，使得可以在大致不蝕刻閘極間隔層223的情況下選擇性地移除內間隔材料層。在一些實施方式中，在方框120進行的回蝕刻操作可以包含使用氟化氫（HF）、氟氣（F2 ）、氫（H2 ）、氨（NH3 ）、三氟化氮（NF3 ）或其他基於氟的蝕刻劑。如第7A圖所示，每個內間隔部件230直接接觸凹蝕的犧牲層206並設置在兩個相鄰的通道層208之間。在一些實施方式中，因為底犧牲部件203中的第一深度D1是淺的（即，沿Y方向小於1 nm），回蝕刻可以移除沉積在底犧牲部件203的側壁上的內間隔材料層。缺少覆蓋底犧牲部件203的側壁之內間隔部件230有助於方框122的置換操作。
參照第1圖、第8A、8B、9、10A和10B圖，方法100包含方框122，用底介電部件234置換底犧牲部件203。為了本發明實施例的目的，置換一層可以指移除此層並沉積一置換層來取代移除的層或將此層化學轉化為具有不同電性效能的層。方法100的方框122的置換操作與前者更一致，並且方法300的方框322的氧化操作與後者更一致。參照第8A圖，方框122的操作可以從選擇性地移除底犧牲部件203開始。在底犧牲部件203由矽鍺形成的實施例中，選擇性移除底犧牲部件203可以類似於選擇性蝕刻犧牲層206。注意，在方框122，內間隔部件230和底蓋部件205覆蓋並保護犧牲層206，這兩者均防止在方框122之選擇性蝕刻對犧牲層206的損傷。第8A圖也顯示底蓋部件205的主要功能，是將最底部的犧牲層206與要被移除的底犧牲部件203隔離。在方框122之選擇性移除底犧牲部件203可能不能完全移除底蓋部件205，其可以降低底蓋部件205的厚度，這可以有助於完全移除在方框132之完全移除底蓋部件205。在移除底犧牲部件203之後，形成底空缺232。
在方法100的方框122中，當移除底犧牲部件203時，虛設閘極堆疊220保持結構完整性。第9圖是沿著鄰近源極/汲極區20和通道區10之間的邊界之鰭狀結構210的長度方向（Y方向）之工件200的局部剖面圖。當從汲極/汲極凹槽226觀之，通道層208的側壁被暴露出來，並且犧牲層206的側壁被內間隔部件230覆蓋。虛設閘極堆疊220至少部分地包覆環繞鰭狀結構210並由隔離部件212支撐。如此一來，當移除底犧牲部件203以形成底空缺232時，可以保持第8A圖所示之結構的結構完整性。
然後，使用具有良好孔洞填充能力的沉積製程，將介電材料沉積在工件200上方，包含沉積到底空缺232中。在一些實施例中，介電材料可以包含氧化矽、氮化矽、碳氧化矽、氮碳氧化矽或合適的介電材料。此處的沉積製程可以是原子層沉積（atomic layer deposition，ALD）製程。在沉積介電材料之後，可以進行等向性和選擇性蝕刻製程以移除底空缺232之外的介電材料，藉此形成底介電部件234。雖然原子層沉積製程具有良好的孔洞填充能力，但可能出現接縫236。接縫236可以是大致在X-Y平面上延伸之片狀氣隙或空隙。在一些情況下，接縫236的厚度（即，沿Z方向的尺寸）可以為0.1 nm至約1.5 nm。在一些範例中，底介電部件234可以缺少接縫。在一些實施方式中，可以選擇用於底介電部件234的介電材料，使等向性製程具有高度選擇性，使得方框122之等向性蝕刻製程不損傷基底202、通道層208及內間隔部件230。
參照第1圖、第11A和11B圖，方法100包含方框124，在工件200上方有襯墊240。在一些實施例中，襯墊240可以包含氧化矽或碳氧化矽。可以使用化學氣相沉積、原子層沉積或合適的沉積技術在工件200上方順應性地沉積襯墊240。在一些情況下，襯墊240可以形成為具有3 nm至約5 nm的厚度。
參照第1圖、第12A和12B圖，方法100包含方框126，回蝕刻襯墊240以暴露出基底202。為了便於在方框128沉積第一磊晶部件242，非等向性蝕刻襯墊240以從面頂的表面（top-facing surfaces）移除襯墊240的部分，例如鰭狀結構210的源極/汲極區20的頂部表面（如第12A圖所示）、虛設閘極堆疊220的頂部表面（如第12A圖所示）、第一間隔層222和第二間隔層224的頂表面（如第12B圖所示）、隔離部件212的頂表面（如第12B圖所示）。在一些實施例中，在方框126的非等向性蝕刻可以包含乾式蝕刻製程。在一些情況下，在方框126的回蝕刻之後，剩餘的襯墊240可以具有約1 nm至約2 nm的厚度。
參照第1圖、第13A和13B圖，方法100包含方框128，在基底202的露出部分上沉積第一磊晶部件242。可以從基底202之露出的頂表面磊晶並選擇性地形成第一磊晶部件242。確切地說，如第13B圖所示，基底202的露出部分是源極/汲極區20中的鰭狀結構210的底部部分。因為襯墊240的表面不利於第一磊晶部件242的磊晶沉積，所以第一磊晶部件242以自底向上的方式從基底202的露出表面形成。在一些實施方式中，第一磊晶部件242可以由矽、矽鍺或摻雜砷的矽（即，砷化矽）形成。當想要n型裝置時，第一磊晶部件242可以由矽或摻雜砷的矽形成。當想要p型裝置時，第一磊晶部件242可以由矽鍺形成。在第13A圖所示之實施例中，第一磊晶部件242由矽形成。方框128之合適的磊晶製程包含分子束磊晶製程、氣相磊晶、超高真空化學氣相沉積、金屬有機化學氣相沉積製程及/或其他合適的磊晶成長製程。
在一些實施例中，第一磊晶層242沿Z方向具有從源極/汲極區20測量之約15 nm至約30 nm的厚度。換句話說，第一磊晶結構242的頂表面高於（即，沿Z方向遠離基底202）底介電部件234的頂表面和底蓋部件205的頂表面。第一磊晶部件242具有多種功能。舉例來說，因為第一磊晶部件242未被摻雜或者被摻雜具有較小擴散率的摻質（例如砷（As）），所以第一磊晶部件242不提供任何源極/汲極功能，並且更像是作為防止在第二磊晶部件244（將在以下描述）中的摻質的向下擴散之擴散阻障。對於另一範例，第一磊晶部件242呈現出升高的結晶層（crystalline floor）以利於形成第二磊晶部件244。在沒有第一磊晶部件242的情況下，第二磊晶部件244將必須從源極/汲極區20至少到達最頂通道層208的頂表面高度。也​​就是說，在沒有第一磊晶部件242的情況下，令人滿意的第二磊晶部件244將具有大的長寬比，這可能導致降低的製程寬裕度和增加的缺陷數量。
參照第1圖、第14A和14B圖，方法100包含方框130，在第一磊晶部件242上方沉積第二磊晶部件244。在沉積第一磊晶部件242之後，可以進行預清潔製程（例如化學氧化物移除製程）以移除襯墊240之未被第一磊晶部件242覆蓋的部分。例示性的化學氧化物移除製程可以包含使用氟化氫（HF）和氨（NH3 ）的乾式蝕刻製程。在藉由昇華移除化學氧化物移除製程的副產物之後，可以使用分子束磊晶製程、氣相磊晶、超高真空化學氣相沉積、金屬有機化學氣相沉積製程來沉積第二磊晶部件244。可以原位（in-situ）摻雜第二磊晶部件244。在第14A和14B圖所示之實施例中，第二磊晶部件244包含摻雜有p型摻質（例如硼（B））的矽鍺。在一些實施方式中，第二磊晶部件244的沉積對於半導體表面是選擇性的。在第14A和14B圖所示之範例中，從第一磊晶部件242的頂表面和通道層208之露出的側壁沉積或成長第二磊晶部件244。雖然第二磊晶部件244在襯墊240、內間隔部件230和第二間隔層224上的沉積被抑制，但如第14A圖所示，第二磊晶部件244的過度成長可以合併並最終覆蓋這些元件的表面或其一部分。在一些實施例中，在方框128和方框130的操作可以在相同的製程腔室中進行而不破真空。為了活化第二磊晶部件244中的摻質，方框130可以包含退火製程以將第二磊晶部件244退火。在一些實施方式中，退火製程可以包含快速熱退火（rapid thermal anneal，RTA）製程、雷射尖波退火（laser spike anneal）製程、閃光退火（flash anneal）製程或爐退火製程。在一些情況下，退火製程包含在約900°C至約1100°C之峰值退火溫度。
第15圖繪示n型裝置區中的工件200的局部剖面圖。在第15圖中，可以在n型裝置區中形成n型第三磊晶部件246，而非p型第二磊晶部件244。在一些實施例中，第三磊晶部件246包含用n型摻質（例如磷（P））原位摻雜的矽。由於製程上的相似，將不重複形成第三磊晶部件246的詳細描述。
參照第1圖、第16和17圖，方法100包含方框132，用閘極結構代替虛設閘極堆疊220。方框132的操作可以包含形成接觸蝕刻停止層（contact etch stop layer，CESL）248、在接觸蝕刻停止層248上方沉積層間介電（interlayer dielectric，ILD）層250、平坦化製程以暴露出虛設電極層216、移除虛設閘極堆疊220、選擇性移除犧牲層206以釋放通道層208作為通道構件208、以及沉積閘極結構。現在參照第16和17圖，在形成層間介電層250之前形成接觸蝕刻停止層248。在一些範例中，接觸蝕刻停止層248可以包含氮化矽、氮氧化矽及/或本技術領域已知的其他材料。接觸蝕刻停止層248的形成可以藉由原子層沉積、電漿輔助化學氣相沉積（plasma-enhanced chemical vapor deposition，PECVD）製程及/或其他合適的沉積或氧化製程。然後，在接觸蝕刻停止層248上方沉積層間介電層250。在一些實施例中，層間介電層250的材料包含例如四乙氧基矽烷（tetraethylorthosilicate，TEOS）氧化物、未摻雜的矽酸鹽玻璃、或摻雜的氧化矽，例如硼磷矽酸鹽玻璃（borophosphosilicate glass，BPSG）、熔融石英玻璃（fused silica glass，FSG）、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、摻雜硼的矽玻璃（boron doped silicon glass，BSG）及/或其他合適的介電材料。層間介電層250的沉積可以藉由電漿輔助化學氣相沉積製程或其他合適的沉積技術。在一些實施例中，在形成層間介電層250之後，可以將工件200退火以改善層間介電層250的完整性。
仍然參照第16和17圖，在沉積接觸蝕刻停止層248和層間介電層250之後，可以藉由平坦化製程來平坦化工件200以暴露出虛設電極層216。舉例來說，平坦化製程可以包含化學機械研磨製程。暴露出虛設電極層216允許移除虛設電極層216、移除虛設介電層214以及釋放通道層208。在一些實施例中，移除虛設電極層216和虛設介電層214在通道區10上方產生閘極溝槽。虛設電極層216和虛設介電層214的移除可以包含對虛設電極層216和虛設介電層214中的材料具有選擇性的一或多種蝕刻製程。舉例來說，可以使用對虛設電極層216和虛設介電層214具有選擇性的選擇性濕式蝕刻、選擇性乾式蝕刻或前述之組合來進行虛設電極層216和虛設介電層214的移除。在選擇性移除虛設電極層216和虛設介電層214之後，通道層208和犧牲層206的表面在通道區10中的閘極溝槽中暴露出來。然後，選擇性地移除犧牲層206以釋放通道層208作為通道構件208。可以藉由選擇性乾式蝕刻、選擇性濕式蝕刻或其他選擇性蝕刻製程來實現犧牲層206的選擇性移除。在一些實施例中，選擇性濕式蝕刻包含APM蝕刻（例如氫氧化銨－過氧化氫－水的混合物）。在一些實施例中，選擇性移除包含SiGe氧化，然後是SiGeOx移除。舉例來說，氧化的提供可以藉由臭氧清潔，然後藉由例如NH4 OH的蝕刻劑來移除SiGeOx。在第16圖所示之一些實施例中，剩餘的底蓋部件205（在第14A和15圖中繪示）相當薄，並且可以與犧牲層206一起被移除。
在第16和17圖所示之一些實施例中，半導體裝置200或工件200包含第一裝置區1000和第二裝置區2000。在第16和17圖中，第一裝置區1000是p型裝置區且第二裝置區2000是n型裝置區。在第一裝置區1000中形成p型第二磊晶部件244。在第二裝置區2000中形成n型第三磊晶部件246。在釋放通道構件208之後，在第一裝置區1000中形成第一閘極結構252，並在第二裝置區2000中形成第二閘極結構254。第一閘極結構252和第二閘極結構254中的每一個包覆環繞由通道層208形成之每一個通道構件208。第一閘極結構252和第二閘極結構254中的每一個可以是高介電常數金屬閘極結構。在此，高介電常數介電材料指的是介電常數大於二氧化矽的介電常數（為約3.9）的介電材料。在各種實施例中，第一閘極結構252和第二閘極結構254中的每一個包含界面層、在界面層上方形成的高介電常數閘極介電層及/或在高介電常數閘極介電層上方形成的閘極電極層。界面層可以包含介電材料，例如氧化矽、矽酸鉿或氮氧化矽。界面層的形成可以藉由化學氧化、熱氧化、原子層沉積、化學氣相沉積（chemical vapor deposition，CVD）及/或其他合適的方法。高介電常數閘極介電層可以包含高介電常數介電層，例如氧化鉿。或者，高介電常數閘極介電層可以包含其他高介電常數介電質，例如TiO2 、HfZrO、Ta2 O3 、HfSiO4 、ZrO2 、ZrSiO2 、LaO、AlO、ZrO、TiO、Ta2 O5 、Y2 O3 、SrTiO3 （STO）、BaTiO3 （BTO）、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3 （BST）、Al2 O3 、Si3 N4 、氮氧化矽（SiON）、前述之組合或其他合適的材料。高介電常數閘極介電層的形成可以藉由原子層沉積、物理氣相沉積、化學氣相沉積、氧化及/或其他合適的方法。
閘極電極層可以包含單層或多層結構，例如具有選擇的功函數之金屬層以增強裝置效能（功函數金屬層）、襯層、潤濕層、黏著層、金屬合金或金屬矽化物的各種組合。作為範例，閘極電極層可以包含Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、Re、Ir、Co、Ni、其他合適的金屬材料或前述之組合。在各種實施例中，閘極電極層的形成可以藉由原子層沉積、物理氣相沉積、化學氣相沉積、電子束蒸鍍或其他合適的製程。在一些實施例中，第一閘極結構252和第二閘極結構254可以具有不同的組成並且可以分開形成。舉例來說，第一閘極結構252可以包含p型功函數金屬層，而第二閘極結構254可以包含n型功函數金屬層。在各種實施例中，可以進行化學機械研磨製程以從工件200移除過量的金屬，藉此提供第一閘極結構252和第二閘極結構254之大致平坦的頂表面。
一結束方框132的操作，就在第一裝置區1000和第二裝置區2000中分別形成p型MBC電晶體260和n型MBC電晶體262。如第16圖所示，在第一裝置區1000中，第一閘極結構252包覆環繞在通道區10中的每一個通道構件208。第一閘極結構252的最底表面設置在底介電部件234上，底介電部件234可以包含接縫236。底介電部件234與第一磊晶部件242由襯墊240隔開。換句話說，兩個相鄰的底介電部件234將第一磊晶部件242夾在中間。每個第一磊晶部件242與底介電部件234由襯墊240隔開。在第一磊晶部件242的頂表面上設置第二磊晶部件244。第二磊晶部件244接觸通道構件208的側壁。
參照第1圖，方法100包含方框134，進行進一步製程。這樣的進一步製程可以包含沉積閘極蓋層、在閘極蓋層上方沉積另外的層間介電層、形成閘極接觸件、形成源極/汲極接觸件、以及形成另外的互連結構。由於閘極蓋層和另外的層間介電層的組成和形成製程可以類似於接觸蝕刻停止層248和層間介電層250的組成和形成製程，為了簡化，省略閘極蓋層和另外的層間介電層的詳細描述。
現在將結合第19、20、21A、21B、22A、22B、23A、23B、24A、24B、25A、25B、26A、26B、27A、27B、28A、28B、29A、29B、30、31和32圖的局部剖面圖來描述第18圖的方法300。注意，在整個本發明實施例中，相似的部件可以共享相似的參考標號。除非另有說明，否則具有相同參考標號的部件可以共享大致相同的形成製程和材料。
參照第18和19圖，方法300包含方框302，在工件200的基底202上沉積底犧牲層203。因為方框302的操作和裝置結構與方法100的方框102之操作和裝置結構大致相似，所以為了簡化而省略方框302的詳細描述。
參照第18和19圖，方法300包含方框304，在底犧牲層203上沉積底蓋部件205。因為方框304的操作和裝置結構與方法100的方框104之操作和裝置結構大致相似，所以為了簡化而省略方框304的詳細描述。
參照第18和19圖，方法300包含方框306，在底蓋部件205上沉積犧牲層206和通道層208的堆疊204。因為方框306的操作和裝置結構與方法100的方框106之操作和裝置結構大致相似，所以為了簡化而省略方框302的詳細描述。
參照第18和20圖，方法300包含方框308，由堆疊204、底蓋部件205、底犧牲層203和基底202形成鰭狀結構210。因為方框308的操作和裝置結構與方法100的方框108之操作和裝置結構大致相似，所以為了簡化而省略方框308的詳細描述。
參照第18和20圖，方法300包含方框310，鰭狀結構210之間的隔離部件212。因為方框310的操作和裝置結構與方法100的方框110之操作和裝置結構大致相似，所以為了簡化而省略方框310的詳細描述。
參照第18、20、21A和21B圖，方法100包含方框312，在鰭狀結構210上方形成虛設閘極堆疊220。因為方框312的操作和裝置結構與方法100的方框112之操作和裝置結構大致相似，所以為了簡化而省略方框312的詳細描述。
參照第18、21A和21B圖，方法300包含方框314，在工件200上方沉積閘極間隔層223。因為方框314的操作和裝置結構與方法100的方框114之操作和裝置結構大致相似，所以為了簡化而省略方框314的詳細描述。
參照第18、22A和22B圖，方法300包含方框316，凹蝕鰭狀結構210的源極/汲極區20。因為方框316的操作和裝置結構與方法100的方框116之操作和裝置結構大致相似，所以為了簡化而省略方框316的詳細描述。
參照第18、23A和23B圖，方法300包含方框318，選擇性地且部分地蝕刻犧牲層206以形成內間隔凹槽228。因為方框318的操作和裝置結構與方法100的方框118之操作和裝置結構大致相似，所以為了簡化而省略方框318的詳細描述。
參照第18、24A和24B圖，方法300包含方框320，在內間隔凹槽228中形成內間隔部件230。因為方框320的操作和裝置結構與方法100的方框120之操作和裝置結構大致相似，所以為了簡化而省略方框320的詳細描述。
參照第18、25A和25B圖，方法300包含方框322，氧化底犧牲部件203以形成底氧化物部件2030。不同於方法100的方框122的操作，在方框322不移除底犧牲部件203。反之，底犧牲部件203被氧化以轉化為底氧化物部件2030。在一些實施例中，在方框320的氧化底犧牲部件203可以藉由使用氧化劑（例如氧氣（O2 ）、水（H2 O）、過氧化氫（H2 O2 ）或臭氧（O3 ））來進行。在一些前述實施方式中，可以使用電漿形式的氧化劑。舉例來說，氧電漿、水電漿、過氧化氫電漿、臭氧電漿或前述之組合。在一實施例中，可以使用臭氧來進行方框322的氧化。在底犧牲部件203由矽鍺形成的實施例中，底氧化物部件2030可以由氧化矽鍺形成或者可以包含氧化矽和氧化鍺。因為氧化矽鍺、氧化矽和氧化鍺是介電材料，所以底氧化物部件2030以類似於底介電部件234之方式作用，兩者皆為堆疊204下方的介電部件。在此，由於底犧牲部件203被轉化為底氧化物部件2030，可以說底犧牲部件203被底氧化物部件2030置換。應注意的是，在方框322，內間隔部件230和底蓋部件205覆蓋並保護犧牲層206，內間隔部件230和底蓋部件205中的每一個均防止氧化劑氧化犧牲層206。第25A圖也顯示底蓋部件205的主要功能，其是將最底部的犧牲層206與要被氧化的底犧牲部件203隔離。如果沒有底蓋部件205，則最底部的犧牲層206將被氧化，對後續製程（例如移除犧牲層206）造成製程變異。
參照第18、26A和26B圖，方法300包含方框324，在工件200上方的襯墊240。因為方框324的操作和裝置結構與方法100的方框124之操作和裝置結構大致相似，所以為了簡化而省略方框324的詳細描述。
參照第18、27A和27B圖，方法300包含方框326，回蝕刻襯墊240以暴露出基底202。因為方框326的操作和裝置結構與方法100的方框126之操作和裝置結構大致相似，所以為了簡化而省略方框326的詳細描述。
參照第18、28A和28B圖，方法300包含方框328，在基底202的露出部分上沉積第一磊晶部件242。可以從基底202之露出的頂表面磊晶並選擇性地形成第一磊晶部件242。確切地說，如第28B圖所示，基底202的露出部分是源極/汲極區20中的鰭狀結構210的底部部分。因為襯墊240的表面不利於第一磊晶部件242的磊晶沉積，所以第一磊晶部件242以自底向上的方式從基底202的露出表面形成。在一些實施方式中，第一磊晶部件242可以由矽、矽鍺或摻雜砷的矽（即，砷化矽）形成。當想要n型裝置時，第一磊晶部件242可以由矽或摻雜砷的矽形成。當想要p型裝置時，第一磊晶部件242可以由矽鍺形成。在第28A和28B圖所示之實施例中，第一磊晶部件242由矽形成。方框328之合適的磊晶製程包含分子束磊晶製程、氣相磊晶、超高真空化學氣相沉積、金屬有機化學氣相沉積製程及/或其他合適的磊晶成長製程。
在一些實施例中，第一磊晶層242沿Z方向具有從源極/汲極區20測量之約15 nm至約30的厚度。換句話說，第一磊晶結構242的頂表面高於（即，沿Z方向遠離基底202）底氧化物部件2030的頂表面和底蓋部件205的頂表面。第一磊晶部件242具有多種功能。舉例來說，因為第一磊晶部件242未被摻雜或者被摻雜具有較小擴散率的摻質（例如砷（As）），所以第一磊晶部件242不提供任何源極/汲極功能，並且更像是作為防止在第二磊晶部件244（將在以下描述）中的摻質的向下擴散之擴散阻障。對於另一範例，第一磊晶部件242呈現出升高的結晶層以利於形成第二磊晶部件244。在沒有第一磊晶部件242的情況下，第二磊晶部件244將必須從源極/汲極區20至少到達最頂通道層208的頂表面高度。也​​就是說，在沒有第一磊晶部件242的情況下，令人滿意的第二磊晶部件244將具有大的長寬比，這可能導致降低的製程寬裕度和增加的缺陷數量。
參照第18、29A和29B圖，方法300包含方框330，在第一磊晶部件242上方沉積第二磊晶部件244。因為方框330的操作和裝置結構與方法100的方框130之操作和裝置結構大致相似，所以為了簡化而省略方框330的詳細描述。
第30圖繪示n型裝置區中的工件200的局部剖面圖。在第30圖中，可以在n型裝置區中形成n型第三磊晶部件246，而非p型第二磊晶部件244。在一些實施例中，第三磊晶部件246包含用n型摻質（例如磷（P））原位摻雜的矽。由於製程上的相似，將不重複形成第三磊晶部件246的詳細描述。
參照第18、31和32圖，方法300包含方框332，用閘極結構置換虛設閘極堆疊220。因為方框332的操作和裝置結構與方法100的方框132之操作和裝置結構大致相似，所以為了簡化而省略方框332的詳細描述。
在第31和32圖所示之一些實施例中，半導體裝置200或工件200包含第一裝置區1000和第二裝置區2000。在第31和32圖描繪的實施例中，第一裝置區1000是p型裝置區且第二裝置區2000是n型裝置區。在第一裝置區1000中形成p型第二磊晶部件244。在第二裝置區2000中形成n型第三磊晶部件246。在釋放通道構件208之後，在第一裝置區1000中形成第一閘極結構252，並在第二裝置區2000中形成第二閘極結構254。第一閘極結構252和第二閘極結構254中的每一個包覆環繞由通道層208形成之每一個通道構件208。第一閘極結構252和第二閘極結構254中的每一個可以是高介電常數金屬閘極結構。因為方框332的操作和裝置結構與方法100的方框132之操作和裝置結構大致相似，所以為了簡化而省略方框332的詳細描述。
一結束方框332的操作，就在第一裝置區1000和第二裝置區2000中分別形成p型MBC電晶體260和n型MBC電晶體262。如第31圖所示，在第一裝置區1000中，第一閘極結構252包覆環繞通道區10中的每一個通道構件208。第一閘極結構252的最底表面設置在底蓋部件205上，底蓋部件205設置在底氧化物部件2030上。不同於底介電部件234，底氧化物部件2030是藉由氧化而非沉積形成的，並且不含任何接縫或空隙。底氧化物部件2030與第一磊晶部件242由襯墊240隔開。換句話說，兩個相鄰的底氧化物部件2030將第一磊晶部件242夾在中間。類似地，底蓋部件205與第一磊晶部件242由襯墊240隔開。在兩個相鄰的通道區中的兩個相鄰的底蓋部件205將第一磊晶部件242夾在中間。每一個第一磊晶部件242與底蓋部件205由襯墊240隔開。在第一磊晶部件242的頂表面上設置第二磊晶部件244。第二磊晶部件244接觸通道構件208的側壁。
參照第18圖，方法300包含方框334，進行進一步的處理。因為方框334的操作和裝置結構與方法100的方框134之操作和裝置結構大致相似，所以為了簡化而省略方框334的詳細描述。
雖然並非用於限制，但本發明實施例中的一或多個實施例為半導體裝置及其形成提供一些益處。舉例來說，本發明實施例中的一些實施例在垂直堆疊的通道構件下方提供底介電部件（或底氧化物部件），並且底介電部件（或底氧化物部件）接觸圍繞每一個垂直堆疊的通道構件之閘極結構的底表面。底介電部件（或底氧化物部件）被未摻雜或導電性較小的第一磊晶部件覆蓋，第一磊晶部件不接觸通道構件。第二磊晶部件設置在第一磊晶部件上並接觸通道構件的側壁。本發明實施例的底介電部件（或底氧化物部件）以及第一磊晶部件可以降低閘極-汲極電容（Cgd ）和經由塊狀基底的漏電。使用底介電部件（或底氧化物部件）可以使得不必要實施其他防漏電部件，例如在通道構件下方的抗衝穿（anti-punch-through，APT）區。
在一例示性面向，本發明實施例針對一半導體裝置。此半導體裝置包含在基底上的底介電部件，在底介電部件正上方的多個通道構件，包覆環繞每個通道構件的閘極結構，沿著第一方向將底介電部件夾在中間的兩個第一磊晶部件，以及沿著第一方向將多個通道構件夾在中間的兩個第二磊晶部件。
在一些實施例中，底介電部件包含接縫。在一些實施例中，底介電部件包含氧化矽、氮化矽、碳氧化矽或氮碳氧化矽。在一些實施方式中，底介電部件大致上由氧化矽鍺組成。在一些情況下，兩個第一磊晶部件包含矽、矽鍺或砷化矽。在一些實施例中，兩個第二磊晶部件包含磷摻雜的矽或硼摻雜的矽鍺。在一些實施方式中，兩個第一磊晶部件與底介電部件由襯墊隔開，並且襯墊的組成不同於底介電部件的組成。在一些情況下，底介電部件包含在基底與閘極結構的底表面之間量測的厚度，並且厚度為約8 nm至約10 nm。
在另一例示性面向，本發明實施例針對一半導體裝置。此半導體裝置包含在基底上的底介電部件，在底介電部件正上方的多個通道構件，以及包覆環繞多個通道構件中的每一個之閘極結構。底介電部件設置在基底與閘極結構的底表面之間，並且底介電部件包含接縫。在一些實施方式中，底介電部件包含氧化矽、氮化矽、碳氧化矽或氮碳氧化矽。在一些實施例中，底介電部件大致上由氧化矽鍺組成。在一些實施方式中，半導體裝置可以更包含沿著第一方向將底介電部件夾在中間的兩個第一磊晶部件，以及沿著第一方向將多個通道構件夾在中間的兩個第二磊晶部件。在一些情況下，兩個第一磊晶部件包含矽、矽鍺或砷化矽，並且兩個第二磊晶部件包含磷摻雜的矽或硼摻雜的矽鍺。
在又一例示性面向，本發明實施例針對一方法。此方法包含在基底上沉積底犧牲層，在底犧牲層上沉積底蓋層，在底蓋層上沉積堆疊，堆疊由交錯的多個通道層與多個犧牲層形成，由基底、底犧牲層、底蓋層和堆疊形成鰭狀結構，在鰭狀結構的通道區上方形成虛設閘極堆疊，在虛設閘極堆疊上方形成間隔層，凹蝕鰭狀結構的源極/汲極區以暴露出底犧牲層、底蓋層和堆疊的側壁，選擇性地且部分地凹蝕多個犧牲層以形成內間隔凹槽，在內間隔凹槽中形成內間隔部件，以及用底介電部件置換底犧牲層。
在一些實施例中，底犧牲層的置換包含選擇性地移除底犧牲層以形成底部開口並在底部開口中形成底介電部件。在一些實施方式中，底犧牲層的置換包含氧化底犧牲層以形成氧化矽鍺。在一些情況下，底犧牲層和多個犧牲層包含矽鍺，底犧牲層包含第一鍺濃度，並且多個犧牲層包含大於第一鍺濃度的第二鍺濃度。在一些實施例中，第一鍺濃度為約10%至約25%，並且第二鍺濃度為約30%至約45%。在一些實施方式中，此方法可以更包含在基底和虛設閘極堆疊上方沉積襯墊，非等向性地蝕刻襯墊以在鰭狀結構的源極/汲極區中暴露出基底，在源極/汲極區中形成第一磊晶部件，移除未被第一磊晶部件覆蓋的襯墊，以及在第一磊晶部件上形成第二磊晶部件。在一些情況下，第一磊晶部件包含矽、矽鍺或砷化矽，並且第二磊晶部件包含磷摻雜的矽或硼摻雜的矽鍺。
以上概述數個實施例之部件，使得本技術領域中具有通常知識者可以更加理解本發明實施例的面向。本技術領域中具有通常知識者應該理解，他們能輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與本文介紹的實施例之相同目的及/或優點。本技術領域中具有通常知識者也應理解，此類等效的結構並未悖離本發明實施例的精神與範圍，並且他們能在不違背本發明實施例的精神和範圍下，做各式各樣的改變、取代和調整。
10:通道區 20:源極/汲極區 100,300:方法 102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,302,304,306,308,310,312,314,316,318,320,322,324,326,328,330,332,334:方框 200:工件 202:基底 203:底犧牲層 204:堆疊 205:底蓋層 206:犧牲層 208:通道層 210:鰭狀結構 211:溝槽 212:隔離部件 214:虛設介電層 216:虛設電極層 217:氮化物硬遮罩層 218:閘極頂部硬遮罩層 219:氧化物硬遮罩層 220:虛設閘極堆疊 222:第一間隔層 223:閘極間隔層 224:第二間隔層 226:源極/汲極凹槽 228:內間隔凹槽 230:內間隔部件 232:底空缺 234:底介電部件 236:接縫 240:襯墊 242:第一磊晶部件 244:第二磊晶部件 246:第三磊晶部件 248:接觸蝕刻停止層 250:層間介電層 252:第一閘極結構 254:第二閘極結構 260:p型MBC電晶體 262:n型MBC電晶體 1000:第一裝置區 2000:第二裝置區 2030:底氧化物部件 D1:第一深度 D2:第二深度 X,Y,Z:方向
藉由以下的詳細描述配合所附圖式，可以更加理解本發明實施例的內容。需強調的是，根據產業上的標準慣例，許多部件並未按照比例繪製。事實上，為了能清楚地討論，各種部件的尺寸可能被任意地增加或減少。 第1圖根據本發明實施例的一或多個面向繪示具有底介電層之半導體裝置的形成方法的流程圖。 第2、3、4A、4B、5A、5B、6A、6B、7A、7B、8A、8B、9、10A、10B、11A、11B、12A、12B、13A、13B、14A、14B、15、16和17圖根據本發明實施例的一或多個面向繪示在根據第1圖的方法之生產製程期間的工件的局部剖面圖。 第18圖根據本發明實施例的一或多個面向繪示具有底氧化物層之半導體裝置的形成方法的流程圖。 第19、20、21A、21B、22A、22B、23A、23B、24A、24B、25A、25B、26A、26B、27A、27B、28A、28B、29A、29B、30、31和32圖根據本發明實施例的一或多個面向繪示在根據第18圖的方法之生產製程期間的工件的局部剖面圖。
10:通道區
20:源極/汲極區
200:工件
202:基底
208:通道層
222:第一間隔層
224:第二間隔層
230:內間隔部件
234:底介電部件
236:接縫
240:襯墊
242:第一磊晶部件
244:第二磊晶部件
246:第三磊晶部件
248:接觸蝕刻停止層
250:層間介電層
252:第一閘極結構
254:第二閘極結構
260:p型MBC電晶體
262:n型MBC電晶體
1000:第一裝置區
2000:第二裝置區
X,Y,Z:方向

Claims (1)

  1. 一種半導體裝置，包括： 一底介電部件，在一基底上； 複數個通道構件，在該底介電部件正上方； 一閘極結構，包覆環繞該些通道構件； 兩個第一磊晶部件，沿著一第一方向將該底介電部件夾在中間；以及 兩個第二磊晶部件，沿著該第一方向將該些通道構件夾在中間。
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