TW201733017A - 半導體裝置的製造方法 - Google Patents
半導體裝置的製造方法 Download PDFInfo
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- TW201733017A TW201733017A TW105139208A TW105139208A TW201733017A TW 201733017 A TW201733017 A TW 201733017A TW 105139208 A TW105139208 A TW 105139208A TW 105139208 A TW105139208 A TW 105139208A TW 201733017 A TW201733017 A TW 201733017A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66515—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned selective metal deposition simultaneously on the gate and on source or drain
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本揭露之實施例提供一種製造半導體裝置的方法。該方法包括:形成第一閘極堆疊於基底上方。第一閘極堆疊包括閘極電極、設置於閘極電極上方的第一硬罩幕(HM)及沿著第一閘極堆疊的側壁之側壁間隔物。該方法亦包括:形成第一介電層於第一閘極堆疊上方;形成第二硬罩幕於第一硬罩幕及側壁間隔物之頂表面上方;形成第二介電層於第二硬罩幕及第一介電層上方;及移除第二介電層及第一介電層以形成溝槽並暴露基底的一部份,而第二硬罩幕設置於第一閘極堆疊上方。
Description
本揭露係關於半導體裝置的製造方法。
半導體積體電路(IC)產業歷經了快速成長。IC材料及設計上的技術進步已產生了數代的IC,其中每一代皆比前一代具有體積更小且更精密的電路。在IC發展的進程上,功能密度(即,每一晶片之內連線裝置的數量)逐漸增加的同時,幾何尺寸(即,利用製程步驟可以產生之最小元件(或線))逐漸縮小。
此微縮化(scaling down)製程通常可提供增加產率及降低相關成本之益處。此微縮化亦增加了IC處理及製造的複雜度。為了實現這些進步,需要IC處理及製造的類似發展。其中一方面為介於電晶體與其他裝置之間的導線或互連結構。儘管現存之製造IC裝置的方法通常已足以應付其需求,但仍未在所有方面皆完全地滿足。例如,在形成接觸窗之方面仍存在許多挑戰。
本揭露提供許多製造半導體裝置之不同的實施例,其提供一或多個對於現存方法之改良。在一實施例中,製造半導體裝置的方法包括:形成第一閘極堆疊於基底上方。第一閘極堆疊包括閘極電極、設置於閘極電極上方的第一硬罩幕
(HM)及沿著該第一閘極堆疊的側壁之側壁間隔物。該方法亦包括:形成第一介電層於第一閘極堆疊上方;形成第二硬罩幕於第一硬罩幕及側壁間隔物之頂表面上方;形成第二介電層於第二硬罩幕及第一介電層上方;及移除第二介電層及第一介電層以形成溝槽並暴露基底的一部份,而第二硬罩幕設置於第一閘極堆疊上方。
於另一實施例中,方法包括提供初始結構。初始結構包括形成閘極結構於基底上方。閘極結構包括第一硬罩幕(HM)及沿著閘極結構側壁之側壁間隔物。方法亦包括形成源極/汲極(S/D)特徵於鄰近閘極結構的基底中;形成第一介電層於閘極結構上方,其中其中源極/汲極(S/D)特徵埋置於第一介電層中;形成第二硬罩幕於第一硬罩幕極側壁間隔物的頂表面上方;形成第二介電層於閘極結構上方;移除第二及第一介電層以形成溝槽,而閘極結構被第二硬罩幕所保護;及形成導電特徵於溝槽中。
在又一實施例中,半導體裝置包括:形成第一閘極結構及第二閘極結構於基底上方。第一閘極結構包括第一硬罩幕(HM)層及沿著第一閘極結構的側壁之側壁間隔物,且第二閘極結構包括包括第一硬罩幕(HM)層及沿著第二閘極結構的側壁之側壁間隔物。方法亦包括形成源極/汲極(S/D)特徵於基底中;形成第一介電層於第一及第二閘極結構上方;形成第二介電層於第二硬罩幕上方;移除第二及第一介電層以形成溝槽,而閘極結構被第二硬罩幕所保護;及形成導電特徵於溝槽中。
100‧‧‧方法
102‧‧‧步驟
104‧‧‧步驟
106‧‧‧步驟
108‧‧‧步驟
110‧‧‧步驟
112‧‧‧步驟
114‧‧‧步驟
200‧‧‧半導體裝置
205‧‧‧初始結構
210‧‧‧基底
220‧‧‧隔離特徵
230‧‧‧第一導電特徵
230‧‧‧高介電常數材料/金屬閘極
235‧‧‧第一硬罩幕
240‧‧‧側壁間隔物
250‧‧‧第二導電特徵
260‧‧‧第一介電層
310‧‧‧第二硬罩幕
410‧‧‧第二介電層
510‧‧‧第三硬罩幕
520‧‧‧開口
530‧‧‧子集
540‧‧‧子集
610‧‧‧溝槽
710‧‧‧導電層
715‧‧‧導電特徵
以下將配合所附圖式詳述本揭露之實施例,應注意的是,依照工業上的標準實施,以下圖示並未按照比例繪製,事實上,可能任意的放大或縮小元件的尺寸以便清楚表現出本揭露的特徵。而在說明書及圖式中,除了特別說明外,同樣或類似的元件將以類似的符號表示。
第1圖係根據一些實施例,製造半導體裝置之例示方法的流程圖。
第2-8圖係根據一些實施例,例示製造半導體裝置的剖面圖。
以下公開許多不同的實施方法或是例子來實行本發明之不同特徵,以下描述具體的元件及其排列的例子以闡述本發明。當然這些僅是例子且不該以此限定本發明的範圍。例如,在描述中提及第一個元件形成一第二個元件上時,其可以包括第一個元件與第二個元件直接接觸的實施例,也可以包括有其他元件形成於第一個與第二個元件之間的實施例,其中第一個元件與第二個元件並未直接接觸。此外,在不同實施例中可能使用重複的標號或標示,這些重複僅為了簡單清楚地敘述本揭露,不代表所討論的不同實施例及/或結構之間有特定的關係。
此外,其中可能用到與空間相關的用詞,像是“在…下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞,這些關係詞係為了便於描述圖示中一個(些)元
件或特徵與另一個(些)元件或特徵之間的關係。這些空間關係詞包括使用中或操作中的裝置之不同方位,以及圖示中所描述的方位。裝置可能被轉向不同方位(旋轉90度或其他方位),則其中使用的空間相關形容詞也可相同地照著解釋。
第1圖係根據一些實施例,製造一或多個半導體裝置之方法100的流程圖。下方將參照如第2-8圖所示之半導體裝置200以詳細地討論方法100。
請參照第1及2圖,方法100開始於步驟102,接收半導體裝置200的初始結構205。初始結構205包括基底210。基底210可為塊狀矽基底。或者,基底210可包括元素半導體,例如具晶體結構之矽或鍺;化合物半導體,例如鍺化矽、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;或上述之組合。可能的基底210亦包括絕緣體上半導體(semiconductor-on-insulator,SOI)基底。藉由氧離子植入矽晶隔離法(separation by implanted oxygen,SIMOX)、晶圓接合及/或其它合適方法之分離以製造絕緣體上半導體基底。
一些例示性基底210亦包括絕緣層。絕緣層包括含有氧化矽、藍寶石及/或其組合之任何合適的材料。例示性絕緣層可為埋藏氧化物層(buried oxide layer,BOX)。可藉由任何合適製程來形成絕緣層,例如佈植(例如SIMOX)、氧化、沉積及/或其它合適製程。在一些例示性半導體裝置200中,絕緣層為絕緣體上半導體基底之元件(例如層)。
基底210亦可包括各種摻雜區。摻雜區可摻雜有p型摻雜物,例如硼或BF2;n型摻雜物,例如磷或砷;或上述之
組合。摻雜區可直接形成於基底210上,於P井結構、N井結構、雙井結構中,或使用凸起結構。基底210更可包括各種主動區,例如配置用於N型金屬氧化半導體電晶體裝置之區域及配置用於N型金屬氧化半導體電晶體裝置之區域。
基底210亦可包括各種隔離特徵220。隔離特徵220分離基底210中之各種裝置區。隔離特徵220包括藉由使用不同製程技術所形成之不同結構。例如,隔離特徵220可包括淺溝槽隔離(shallow trench isolation,STI)特徵。淺溝槽隔離之形成可包括蝕刻溝槽於基底210中,並將諸如氧化矽、氮化矽或氮氧化矽之絕緣材料填入溝槽中。被填充的溝槽可具有多層結構,例如以氮化矽填充溝槽之熱氧化襯層。可實行化學機械拋光(chemical mechanical polishing,CMP)以回拋(polish back)過多的絕緣材料並平坦化隔離特徵220的頂表面。
初始結構205亦包括複數個第一導電特徵230於基底210上方。在一些實施例中,第一導電特徵230可為包含高介電常數材料/金屬閘極(high-k/metal gate,HK/MG)之閘極堆疊。高介電常數材料/金屬閘極230可包括閘極介電層及金屬閘極(MG)。閘極介電層可包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物(oxynitrides)(SiON)或其它合適材料。金屬閘極可包括單層或多層,例如金屬層、襯層、潤濕層及黏合層。金屬閘極可包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W或任何合適
材料。可藉由合適的方法來沉積閘極介電層,例如化學氣相沉積(chemical vapor deposition,CVD)、原子層沉積(atomic layer deposition,ALD)、熱氧化或臭氧氧化、其它合適技術或上述之組合。可藉由原子層沉積、物理氣相沉積(physical vapor deposition,PVD)、化學氣相沉積或其它合適製程來形成金屬閘極。
在一些實施例中,先形成虛設閘極堆疊,接著在實行高熱溫度製程之後將其取代成高介電常數材料/金屬閘極230,例如源極/汲極形成期間之熱製程。虛設閘極堆疊可包括虛設閘極介電層及多晶矽層,並可藉由沉積、圖案化及蝕刻製程來形成。
在本實施例中,第一硬罩幕(hard mask,HM)235形成於每個高介電常數材料/金屬閘極230之頂部上。第一硬罩幕235可包括氮化鈦、氮化矽、碳化矽、氮化矽碳(silicon carbide nitride)或其他合適材料。可藉由沉積、微影圖案化及蝕刻製程來形成第一硬罩幕235。
在一些實施例中,可沿著高介電常數材料/金屬閘極230的側壁來形成側壁間隔物240。側壁間隔物240可包括諸如氮化矽之介電材料。或者,側壁間隔物240可包括碳化矽、氮氧化矽或其它合適材料。可藉由沉積閘極側壁間隔物層並接著各向異性乾蝕刻該閘極側壁間隔物層以形成側壁間隔物240。為了簡化及清楚之目的,本實施例之第一導電特徵230在下文中為具有第一硬罩幕235及側壁間隔物240之高介電常數材料/金屬閘極230。
此外,在一些實施例中,第一導電特徵230亦可包括內連線結構的一部分,例如接點、金屬導孔及/或金屬導線。在一實施例中,第一導電特徵230包括電極、電容、電阻或電阻的一部分。形成第一硬罩幕235以覆蓋第一導電特徵230的頂表面。第一硬罩幕235可包括鉭(Ta)、鈦(Ti)、錳(Mn)、鈷(Co)、釕(Ru)、錫、鉭、TiN、TaN、WN、TiSiN、TaSiN、氮化鋁、氧化鋁及/或其他合適材料。可藉由諸如沉積、微影及蝕刻之製程來形成第一硬罩幕235及第一導電特徵230。
初始結構205亦可包括第二導電特徵250於基底210上方。第二導電特徵250的頂表面可能不會與第一導電特徵230在同一水平面上。例如,第二導電特徵250的頂表面係在第一導電特徵230的頂表面下方。也就是說,如圖所示,第二導電特徵250的頂表面相對於第一導電特徵230的頂表面為非共面的。可藉由諸如沉積、微影及蝕刻之製程來形成第二導電特徵250。
在一些實施例中,第二導電特徵250為源極/汲極(S/D)特徵,位於高介電常數材料/金屬閘極230旁邊且被高介電常數材料/金屬閘極230分離。在一實施例中,位於高介電常數材料/金屬閘極230旁邊之基底210的一部分凹陷以形成源極/汲極凹槽,接著藉由諸如化學氣相、氣相磊晶(vapor phase epitaxy,VPE)及/或超高真空化學氣相沉積(Ultrahigh vacuum CVD,UHV-CVD)之磊晶成長製程及/或其它合適製程以形成源極/汲極特徵250於源極/汲極凹槽上方。
源極/汲極特徵250可包括鍺(Ge)、矽(Si)、砷化鎵
(GaAs)、砷化鋁鎵(AlGaAs)、鍺化矽(SiGe),磷化鎵砷(GaAsP)、銻化鎵(GaSb)、銻化銦(InSb)、砷化銦鎵(InGaAs)、砷化銦(InAs)及/或其它合適材料。
可藉由諸如化學氣相沉積技術(例如:氣相磊晶(phase epitaxy,VPE)及/或超高真空化學氣相沉積(Ultrahigh vacuum CVD,UHV-CVD))之磊晶成長製程、分子束磊晶及/或其它合適製程以形成源極/汲極特徵250。在源極/汲極凹槽以源極/汲極特徵250填充之後,進一步將源極/汲極特徵250之頂層的磊晶成長以水平方向擴展,且可開始形成諸如鑽石型之刻面(facets)。於磊晶製程期間,源極/汲極特徵250可為原位摻雜。例如,在一實施例中,源極/汲極特徵250包括摻雜硼的磊晶成長SiGe層。在另一實施例中,源極/汲極特徵250包括摻雜碳的磊晶成長Si磊晶層。在又一實施例中,源極/汲極特徵250包括摻雜磷的磊晶成長Si磊晶層。在一實施例中,源極/汲極特徵250不是原位摻雜,因此實行佈植製程(即:接合佈植製程)以摻雜源極/汲極特徵250。可實行一或多個退火製程以活化摻雜物。一或多個退火製程包括快速熱退火(rapid thermal annealing,RTA)及/或雷射退火製程。為了簡化及清楚之目的,本實施例之第二導電特徵250為源極/汲極特徵250並以此表示。
此外,在一些實施例中,第二導電特徵250亦可包括內連線結構的一部分,例如接點、金屬導孔及/或金屬導線。在一實施例中,第二導電特徵250包括電極、電容、電阻或電阻的一部分。形成第一硬罩幕235以覆蓋第一導電特徵230的頂表面。
在本實施例中,初始結構205包括第一介電層260沉積於基底210上方,包括位於每個高介電常數材料/金屬閘極230之間/上方及位於源極/汲極特徵250上方。源極/汲極特徵250埋置於第一介電層260中。第一介電層260可包括氧化矽、具有低於熱氧化矽之介電常數(k)之介電材料(故稱為低介電常數(low-k)介電材料層)及/或其他合適的介電材料層。第一介電層260可包括單層或多層。可藉由化學氣相、原子層沉積或旋轉塗佈來沉積第一介電層260。
在本實施例中,第一介電層260不同於第一硬罩幕235,亦不同於側壁間隔物240,以於隨後的沉積製程期間達成選擇性沉積,其將於下方詳細描述。在一實施例中,第一介電層260包括氧化矽,而側壁間隔物240及第一硬罩幕235皆包括氮化矽。在另一實施例中,第一介電層260包括氧化矽,而第一硬罩幕235包括氮化鈦,且側壁間隔物240包括氮化矽。
請參照第1及3圖,一旦初始結構205被接收,方法100繼續至步驟104,藉由在基底210上方選擇性沉積以形成第二硬罩幕(HM)310(或保險(insurance)-HM)。選擇第二硬罩幕310的材料以抵擋隨後的溝槽蝕刻製程,其蝕刻第一介電層260。在本實施例中,適當地選擇沉積製程以選擇性地沉積第二硬罩幕310於第一硬罩幕235及側壁間隔物240上方,而避免沉積於第一介電層260上方。藉由此選擇性沉積,第二硬罩幕310以自對準之方式形成於第一硬罩幕235上方。
在本實施例中,施行化學氣相硼沉積製程以選擇性地形成第二硬罩幕310於第一硬罩幕235及側壁間隔物240上
方。在一實施例中,於化學氣相硼沉積製程中,B2H6氣體的氣體流量為約100sccm至400sccm;Ar的氣體流量為約100sccm至400sccm;H2的氣體流量為約100sccm至400sccm;製程壓力(腔室壓力)為約15托(torr)至50托,且製程溫度(基底溫度)為約300℃至400℃。
在一實施例中,第二硬罩幕310選擇性地形成於氮化矽第一硬罩幕235及氮化矽側壁間隔物240上方並與其物理接觸。在另一實施例中,第二硬罩幕310選擇性地形成於氮化鈦第一硬罩幕235及氮化矽側壁間隔物240上方並與其物理接觸。
請參照第1及4圖,方法100繼續至步驟106,沉積第二介電層410於第一介電層260及第二硬罩幕310上方。第二介電層410可包括氧化矽、低介電常數(low-k)介電材料及/或其他合適的介電材料層。第二介電層410可包括單層或多層。在本實施例中,第二介電層410不同於第二硬罩幕310、第一硬罩幕235及側壁間隔物240,以於隨後的溝槽蝕刻期間達成蝕刻選擇性,其將於下方詳細描述。第二介電層410之形成在許多方面相似於如上所討論於第2圖所示之第一介電層260。
請參照第1及5圖,方法100繼續至步驟108,形成具有開口520的第三硬罩幕510於第二介電層410上方。在本實施例中,高介電常數材料/金屬閘極230之子集(subset)530及源極/汲極特徵250之子集540位於開口520之中。在一實施例中,第三硬罩幕510為經圖案化之光阻層。在另一實施例中,第三硬罩幕510係藉由以下步驟所形成:將子硬罩幕層(sub-HM
layer)沉積於第二介電層410上方,將光阻層沉積於子硬罩幕層上方,將光阻層圖案化,接著透過圖案化的光阻層來蝕刻子硬罩幕層以將子硬罩幕層圖案化,接著透過圖案化的子硬罩幕層來蝕刻第三硬罩幕510以形成開口520於第三硬罩幕510之中。
請參照第1及6圖,方法100繼續至步驟110,透過開口520來蝕刻第二介電層410及第一介電層260以形成溝槽610。如圖所示,將介於一些高介電常數材料/金屬閘極230(例如高介電常數材料/金屬閘極230之子集530)之間的第二介電層410及第一介電層260移除,以暴露一些源極/汲極特徵250(例如源極/汲極特徵250之子集540)。因此,溝槽610有時被稱為源極/汲極接觸溝槽。如上所討論,適當地選擇溝槽蝕刻製程以選擇性地移除第二介電層410及第一介電層260,但基本上並未蝕刻第二硬罩幕310、第一硬罩幕235及側壁間隔物240。由於足夠的蝕刻選擇性,故所形成之溝槽610具有自對準之性質,其放寬了製程限制,例如:微影製程中之未對準及/或重疊問題、圖案負載效應及蝕刻製程寬裕度(process window)。
於此自對準溝槽蝕刻製程期間,通常使用第一硬罩幕235而不用第二硬罩幕310,以保護高介電常數材料/金屬閘極(或第一導電特徵)230。然而,有時候第一硬罩幕235的蝕刻速率不夠低,使得第一硬罩幕235於形成溝槽610期間被蝕刻掉,從而暴露高介電常數材料/金屬閘極230的一部分。當形成導電特徵於源極/汲極特徵上方時,這將導致短路的問題。在本實施例中,於蝕刻第二介電層410及第一介電層260期間,蝕刻第二硬罩幕310之速率較蝕刻第一硬罩幕235及側壁間隔物
240之速率慢得多。因此,第二硬罩幕310提高了對於高介電常數材料/金屬閘極230之保護,從而防止高介電常數材料/金屬閘極230暴露於蝕刻製程期間,並防止隨後所產生之短路問題。
溝槽蝕刻可包括選擇性濕蝕刻、選擇性乾蝕刻及/或其組合。可以各種蝕刻參數調整各個蝕刻製程,例如:所使用之蝕刻劑、蝕刻溫度、蝕刻溶液濃度、蝕刻壓力、蝕刻劑流速及/或其他合適的參數。
舉例來說,第二硬罩幕310包括硼,且第一硬罩幕235及側壁間隔物240接包括氮化矽。溝槽蝕刻包括電漿乾蝕刻製程,其使用諸如CF4、SF6、CH2F2、CHF3及/或C2F6之氟基化學物質。第一介電層260及第二介電層410之蝕刻速率較第一硬罩幕235之蝕刻速率高三倍,且較第二硬罩幕310之蝕刻速率高十倍。
在形成溝槽610之後,藉由適當的蝕刻製程來移除第三硬罩幕510。在第三硬罩幕510為光阻圖案的一實例中,在形成溝槽610之後,係藉由濕剝離及/或電漿灰化來移除第三硬罩幕510。
請參照第1及7圖,方法100繼續至步驟112,沉積導電層710於溝槽610中,以向下延伸並與源極/汲極特徵250之子集540物理接觸。導電層170可包括金屬層,例如銅(Cu)、鋁(Al)、鎢(W)、銅錳(CuMn)、銅鋁(CuAl)或銅矽(CuSi)或其他合適的導電材料。可藉由物理氣相沉積、化學氣相沉積、金屬有機化學氣相沉積(metal-organic chemical vapor deposition,MOCVD)或電鍍來沉積導電層710。
請參照第1及8圖,方法100繼續至步驟114,使導電層710凹陷。在一些實施例中,實行化學機械拋光製程以移除過多的導電層710,以及第二硬罩幕310及第一硬罩幕235。剩下的導電層710形成導電特徵715,其物理接觸源極/汲極特徵250,而高介電常數材料/金屬閘極230藉由被側壁間隔物240包圍而與導電特徵715隔離。
可以於方法100之前、期間及之後提供額外的步驟,且方法100之額外的實施例所描述的一些步驟可以被置換、刪除或移動。
半導體裝置200可包括額外的特徵,其可藉由隨後的製程來形成。舉例來說,各種介層窗/導線及多層互連特徵(例如金屬層及介層介電質)形成於基底210上方。例如,多層互連結構包括諸如傳統的介層窗或接觸窗之垂直的金屬互連線,及諸如金屬導線之水平的金屬互連線。各種互連特徵可執行包括銅、鎢及/或矽化物之各種導電材料。在一實施例中,使用金屬鑲嵌及/或雙重金屬鑲嵌製程以形成銅相關的多層互連結構。
基於上述,可以看出本揭露提供形成自對準接觸溝槽的方法。該方法選擇性地形成保險-硬罩幕以於接觸溝槽形成期間保護高介電常數材料/金屬閘極,其中高介電常數材料/金屬閘極暴露於溝槽蝕刻製程。該方法顯示了能夠於源極/汲極接觸溝槽形成期間防止金屬閘極之損耗,以避免金屬閘極之電路短路。該方法提供強健的自對準接觸形成製程且具有放寬的製程限制。
本揭露提供許多製造半導體裝置之不同的實施例,其提供一或多個對於現存方法之改良。在一實施例中,製造半導體裝置的方法包括:形成第一閘極堆疊於基底上方。第一閘極堆疊包括閘極電極、設置於閘極電極上方的第一硬罩幕(HM)及沿著該第一閘極堆疊的側壁之側壁間隔物。該方法亦包括:形成第一介電層於第一閘極堆疊上方;形成第二硬罩幕於第一硬罩幕及側壁間隔物之頂表面上方;形成第二介電層於第二硬罩幕及第一介電層上方;及移除第二介電層及第一介電層以形成溝槽並暴露基底的一部份,而第二硬罩幕設置於第一閘極堆疊上方。
於另一實施例中,方法包括提供初始結構。初始結構包括形成閘極結構於基底上方。閘極結構包括第一硬罩幕(HM)及沿著閘極結構側壁之側壁間隔物。方法亦包括形成源極/汲極(S/D)特徵於鄰近閘極結構的基底中;形成第一介電層於閘極結構上方,其中其中源極/汲極(S/D)特徵埋置於第一介電層中;形成第二硬罩幕於第一硬罩幕極側壁間隔物的頂表面上方;形成第二介電層於閘極結構上方;移除第二及第一介電層以形成溝槽,而閘極結構被第二硬罩幕所保護;及形成導電特徵於溝槽中。
在又一實施例中,半導體裝置包括:形成第一閘極結構及第二閘極結構於基底上方。第一閘極結構包括第一硬罩幕(HM)層及沿著第一閘極結構的側壁之側壁間隔物,且第二閘極結構包括包括第一硬罩幕(HM)層及沿著第二閘極結構的側壁之側壁間隔物。方法亦包括形成源極/汲極(S/D)特徵於基
底中;形成第一介電層於第一及第二閘極結構上方;形成第二介電層於第二硬罩幕上方;移除第二及第一介電層以形成溝槽,而閘極結構被第二硬罩幕所保護;及形成導電特徵於溝槽中。
前述內文概述了許多實施例的特徵,使本技術領域中具有通常知識者可以更佳的了解本揭露的各個方面。本技術領域中具有通常知識者應該可理解,他們可以很容易的以本揭露為基礎來設計或修飾其它製程及結構,並以此達到相同的目的及/或達到與本揭露介紹的實施例相同的優點。本技術領域中具有通常知識者也應該了解這些相等的結構並不會背離本揭露的發明精神與範圍。本揭露可以作各種改變、置換、修改而不會背離本揭露的發明精神與範圍。
200‧‧‧半導體裝置
210‧‧‧基底
220‧‧‧隔離特徵
230‧‧‧第一導電特徵
240‧‧‧側壁間隔物
250‧‧‧第二導電特徵
260‧‧‧第一介電層
530‧‧‧子集
540‧‧‧子集
710‧‧‧導電層
715‧‧‧導電特徵
Claims (1)
- 一種半導體裝置的製造方法,包括:形成一第一閘極堆疊於一基底上方,其中該第一閘極堆疊包括一閘極電極、設置於該閘極電極上方的一第一硬罩幕(hard mask,HM)及沿著該第一閘極堆疊的側壁之側壁間隔物;形成一第一介電層於該第一閘極堆疊上方;形成一第二硬罩幕於該第一硬罩幕及側壁間隔物之頂表面上方;形成一第二介電層於該第二硬罩幕及該第一介電層上方;及移除該第二介電層及該第一介電層以形成一溝槽並暴露該基底的一部份,而該第二硬罩幕設置於該第一閘極堆疊上方。
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