CN106463529A - 半导体装置以及半导体装置的制造方法 - Google Patents

半导体装置以及半导体装置的制造方法 Download PDF

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CN106463529A
CN106463529A CN201580023346.6A CN201580023346A CN106463529A CN 106463529 A CN106463529 A CN 106463529A CN 201580023346 A CN201580023346 A CN 201580023346A CN 106463529 A CN106463529 A CN 106463529A
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CN106463529B (zh
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平林康弘
町田悟
山下侑佑
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Denso Corp
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Abstract

本发明提供一种能够抑制回扫的半导体装置。该半导体装置具有半导体基板，半导体基板具有IGBT区和二极管区。在对从表面朝向背面的方向上的n型杂质浓度分布进行观察时，在阴极区与缓冲区的边界处形成有n型杂质浓度的极小值。在缓冲区内形成有n型杂质浓度的极大值。在缓冲区与阴极区中的至少一方内形成有与周围相比以高浓度分布有晶体缺陷的晶体缺陷区域。对从表面朝向背面的方向上的晶体缺陷的浓度分布进行观察时的晶体缺陷的浓度的峰值被形成在与具有n型杂质浓度的极大值的一半的n型杂质浓度的位置相比靠背面侧的区域内。

Description

半导体装置以及半导体装置的制造方法
技术领域
(关联申请的相互参照)
本申请为2014年4月28日申请的日本专利申请特愿2014-092438的关联申请，并要求基于该日本专利申请的优先权，且将该日本专利申请所记载的全部内容作为构成本说明书的内容而进行援用。
本发明涉及一种半导体装置。
背景技术
在日本专利公开第2007-288158号公报(以下称为专利文献1)中公开了一种具有二极管和IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极性晶体管)的半导体装置(所谓的RC-IGBT)。在该半导体装置中，在二极管的阴极区与漂移区之间形成有n型杂质浓度比较高的缓冲区。在二极管断开时，通过缓冲区而防止耗尽层伸展至阴极区的情况。
发明内容
发明所要解决的课题
如专利文献1所记载的那样，在二极管与IGBT被形成在同一半导体基板上的半导体装置中，当IGBT导通时，电子从IGBT的漂移层流入二极管的缓冲区。因此，当IGBT导通时，在发射极-集电极间电压暂时性地上升后，在IGBT中流通的电流增加。这种特性被称为回扫(snapback)。当IGBT展现出回扫时，IGBT的损耗将增大，从而成为问题。在专利文献1的技术中，通过将各个半导体层的电阻率、厚度以及宽度设为预定的关系，从而抑制了回扫的发生。但是，各个半导体层的电阻率、厚度以及宽度对半导体装置的其他特性会产生较大的影响。因此，当如专利文献1那样对各个半导体层的电阻率、厚度以及宽度设置制约时，存在无法使半导体装置的特性最优化的问题。
用于解决课题的方法
本发明的半导体装置具有半导体基板，该半导体基板具有IGBT区和二极管区。在IGBT区内的半导体基板的表面上形成有发射电极，在二极管区内的半导体基板的表面上形成有阳极电极，在半导体基板的背面上形成有背面电极。在IGBT区内形成有：n型的发射区，其与所述发射电极相接；p型的体区，其与所述发射电极相接；n型的IGBT漂移区，其通过所述体区而与所述发射区分离；p型的集电区，其通过所述IGBT漂移区而与所述体区分离，并与所述背面电极相接；栅绝缘膜，其与所述体区相接；栅电极，其隔着所述栅绝缘膜而与所述体区对置。在二极管区内形成有：p型的阳极区，其与所述阳极电极相接；n型的二极管漂移区，其相对于所述阳极区在所述背面侧邻接，并且与所述IGBT漂移区相连；n型的缓冲区，其相对于所述二极管漂移区而在所述背面侧邻接；n型的阴极区，其相对于所述缓冲区在所述背面侧邻接，并且与所述背面电极相接。在对从所述表面朝向所述背面的方向上的n型杂质浓度分布进行观察时，在所述阴极区与所述缓冲区的边界处形成有n型杂质浓度的极小值，并且在所述缓冲区内形成有n型杂质浓度的极大值。所述阴极区内的n型杂质浓度的峰值以及所述极大值与所述二极管漂移区的n型杂质浓度相比较高。在所述缓冲区与所述阴极区中的至少一方内形成有与周围相比以高浓度分布有晶体缺陷的晶体缺陷区域。对从所述表面朝向所述背面的方向上的所述晶体缺陷的浓度分布进行观察时的所述晶体缺陷的浓度的峰值被形成在与如下的位置相比靠所述背面侧的区域内，所述位置为与所述极大值的位置相比靠所述表面侧且具有所述极大值的一半的n型杂质浓度的位置。
在该半导体装置中，在缓冲区与阴极区中的至少一方内，以在缓冲区或阴极区内形成晶体缺陷的浓度的峰值的方式而形成有晶体缺陷区域。当以此种方式形成有晶体缺陷区域时，在IGBT导通时，会抑制电子从IGBT漂移区向缓冲区或阴极区流通的情况。由此，会抑制回扫。
附图说明
图1为实施例1的半导体装置10的纵剖视图。
图2为表示实施例1的半导体装置10的深度方向上的n型杂质与晶体缺陷的浓度分布的图表。
图3为比较例的半导体装置的纵剖视图。
图4为表示图3的半导体装置的IGBT的特性的图表。
图5为形成晶体缺陷的工序的说明图。
图6为实施例2的半导体装置的纵剖视图。
图7为表示实施例2的半导体装置的深度方向上的n型杂质与晶体缺陷的浓度分布的图表。
图8为实施例3的半导体装置的纵剖视图。
图9为表示实施例3的半导体装置的深度方向上的n型杂质与晶体缺陷的浓度分布的图表。
图10为实施例4的半导体装置的纵剖视图。
图11为表示实施例4的半导体装置的深度方向上的n型杂质与晶体缺陷的浓度分布的图表。
图12为表示实施例5的半导体装置的深度方向上的n型杂质与晶体缺陷的浓度分布的图表。
具体实施方式
首先，在以下对实施例的特征进行列述。
(特征1)晶体缺陷的浓度的峰值被形成在缓冲区内。由于缓冲区与阴极区相比容易通过晶体缺陷而使电阻上升，因此根据这种方式能够更理想地抑制回扫。
(特征2)晶体缺陷的浓度的峰值被形成在具有与极大值的一半的n型杂质浓度相比较高的n型杂质浓度的区域内。
(特征3)通过向半导体基板注入带电粒子从而形成晶体缺陷区域。
图1所示的实施例1的半导体装置10具有半导体基板12、上部电极14和下部电极16。半导体基板12为硅制的基板。上部电极14被形成在半导体基板12的上表面(表面)上。下部电极16被形成在半导体基板12的下表面(背面)上。
半导体基板12具有IGBT区20和二极管区40，所述IGBT区20形成有纵型的IGBT，所述二极管区40形成有纵型的二极管。上部电极14兼作IGBT的发射电极和二极管的阳极电极。下部电极16兼作IGBT的集电电极和二极管的阴极电极。
在IGBT区20内的半导体基板12内形成有发射区22、体区24、IGBT漂移区26、IGBT缓冲区28以及集电区30。
发射区22为n型区域，并且被形成在露出于半导体基板12的上表面的范围内。发射区22与上部电极14欧姆接触。
体区24为p型区域，并且与发射区22相接。体区24被形成在露出于半导体基板12的上表面的范围内。体区24从发射区22的侧方延伸至发射区22的下侧。体区24具有体接触区24a和低浓度体区24b。体接触区24a具有较高的p型杂质浓度。体接触区24a被形成在露出于半导体基板12的上表面的范围内，并且与上部电极14欧姆接触。低浓度体区24b具有与体接触区24a相比较低的p型杂质浓度。低浓度体区24b被形成于发射区22和体接触区24a的下侧。
IGBT漂移区26为n型区域，并且与体区24相接。IGBT漂移区26被形成于体区24的下侧。IGBT漂移区26通过体区24而与发射区22分离。
IGBT缓冲区28为n型区域，并且与IGBT漂移区26相接。IGBT缓冲区28被形成于IGBT漂移区26的下侧。IGBT缓冲区28的n型杂质浓度与IGBT漂移区26相比较高。
集电区30为p型区域，并且与IGBT缓冲区28相接。集电区30被形成在IGBT缓冲区28的下侧。集电区30被形成在露出于半导体基板12的下表面的范围内。集电区30与下部电极16欧姆接触。集电区30通过IGBT漂移区26以及IGBT缓冲区28而与体区24分离。
在IGBT区20内的半导体基板12的上表面上形成有多个沟槽。各个沟槽被形成在与发射区22邻接的位置处。各个沟槽延伸至到达IGBT漂移区26的深度。
IGBT区20内的各个沟槽的内表面被栅绝缘膜32覆盖。此外，在各个沟槽内配置有栅电极34。各个栅电极34通过栅绝缘膜32而与半导体基板12绝缘。各个栅电极34隔着栅绝缘膜32而与发射区22、低浓度体区24b以及IGBT漂移区26对置。在各个栅电极34的上部上形成有绝缘膜36。各个栅电极34通过绝缘膜36而与上部电极14绝缘。
在二极管区40内的半导体基板12内形成有阳极区42、二极管漂移区44、二极管缓冲区46以及阴极区48。
阳极区42被形成在露出于半导体基板12的上表面的范围内。阳极区42具有阳极接触区42a和低浓度阳极区42b。阳极接触区42a具有较高的p型杂质浓度。阳极接触区42a被形成在露出于半导体基板12的上表面的范围内，并且与上部电极14欧姆接触。低浓度阳极区42b具有与阳极接触区42a相比较低的p型杂质浓度。低浓度阳极区42b被形成于阳极接触区42a的侧方以及下侧。
二极管漂移区44为n型区域，并且与阳极区42相接。二极管漂移区44被形成于阳极区42的下侧。二极管漂移区44的n型杂质浓度与IGBT漂移区26的n型杂质浓度大致相等。二极管漂移区44与IGBT漂移区26相连。即，二极管漂移区44和IGBT漂移区26实质上为相互连接的一个半导体区域。
二极管缓冲区46为n型区域，并且与二极管漂移区44相接。二极管缓冲区46被形成于二极管漂移区44的下侧。二极管缓冲区46的n型杂质浓度与二极管漂移区44相比较高。二极管缓冲区46的n型杂质浓度与IGBT缓冲区28的n型杂质浓度大致相等。二极管缓冲区46与IGBT缓冲区28相连。即，二极管缓冲区46和IGBT缓冲区28实质上为相互连接的一个半导体区域。
阴极区48为n型区域，并且与二极管缓冲区46相接。阴极区48被形成在二极管缓冲区46的下侧。阴极区48的n型杂质浓度与二极管漂移区44相比较高。阴极区48被形成在露出于半导体基板12的下表面的范围内。阴极区48与下部电极16欧姆接触。
在二极管区40内的半导体基板12的上表面上形成有多个沟槽。各个沟槽延伸至到达二极管漂移区44的深度。
二极管区40内的各个沟槽的内表面被绝缘膜52覆盖。此外，在各个沟槽内配置有控制电极54。各个控制电极54通过绝缘膜52而与半导体基板12绝缘。各个控制电极54隔着绝缘膜52而与阳极区42以及二极管漂移区44对置。在各个控制电极54的上部上形成有绝缘膜56。各个控制电极54通过绝缘膜56而与上部电极14绝缘。
在二极管缓冲区46内形成有晶体缺陷区域50。晶体缺陷区域50为与其周围的区域(例如，二极管漂移区44或阴极区48)相比晶体缺陷浓度较高的区域。晶体缺陷区域50内的晶体缺陷是通过向半导体基板12注入氦离子等带电粒子而被形成的。如此被形成的晶体缺陷阻碍载流子的移动。因此，晶体缺陷区域50具有较高的电阻。
图2表示半导体基板12的深度方向(从上表面朝向下表面的方向)上的二极管区40内的n型杂质和晶体缺陷的浓度分布。图2的纵轴表示半导体基板12中的深度方向的位置。图2的横轴利用对数来表示n型杂质的浓度与晶体缺陷的浓度。另外，n型杂质的浓度与晶体缺陷的浓度的范围不同。
在阴极区48内，且在半导体基板12的下表面的位置处，n型杂质浓度达到峰值N1。随着从峰值N1的位置趋向于上表面侧n型杂质浓度减少，并且在阴极区48与二极管缓冲区46的边界的位置处n型杂质浓度成为极小值N2。换言之，具有极小值N2的深度为阴极区48与二极管缓冲区46的边界。n型杂质浓度随着从极小值N2的位置趋向于上表面侧而增加，并且在二极管缓冲区46内成为极大值N3。n型杂质浓度随着从极大值N3的位置趋向于上侧而减少，并且在二极管缓冲区46与二极管漂移区44的边界的位置处成为值N4。在二极管漂移区44内n型杂质浓度大致固定为值N4。即，n型杂质浓度以大致固定的值N4分布的区域为二极管漂移区44，位于与之相比靠下表面侧，且与值N4相比具有n型杂质浓度的区域为二极管缓冲区46。极小值N2与值N4相比较高。极大值N3与极小值N2相比较高。峰值N1与极大值N3相比较高。
此外，图2所示的深度方向的位置D1、D2表示在二极管缓冲区46内具有极大值N3的一半的n型杂质浓度(N3/2)的位置。位置D1位于与极大值N3的位置相比靠上表面侧，位置D2位于与极大值N3的位置相比靠下表面侧。此外，图2的区域60表示位置D1与位置D2之间的区域。在区域60内，n型杂质浓度与极大值N3的一半的值相比较高。
此外，如图2所示，晶体缺陷浓度的峰值C1被形成在二极管缓冲区46内。更详细而言，晶体缺陷浓度的峰值C1被形成在区域60内。
接下来，在与比较例的半导体装置进行比较的同时对实施例1的半导体装置10的动作进行说明。图3表示比较例的半导体装置。图3的半导体装置在不具有晶体缺陷区域50这一点上与实施例1的半导体装置10不同。此外，图4表示在使图3的半导体装置的IGBT导通时的特性。在使该IGBT动作时，向栅电极34施加阈值以上的电压。由此，在栅绝缘膜32附近的体区24内形成沟道。在该状态下，使集电极电压(集电极-发射极间电压)上升。于是，如图3的箭头100所示，电子从发射区22流入IGBT漂移区26。在该阶段，由于集电极电压较低，因此集电区30与IGBT缓冲区28的边界的pn结不导通。因此，电子如箭头102、104所示那样，经由阴极区48而朝向下部电极16流动。多数的电子如箭头102所示那样，从IGBT漂移区26流入IGBT缓冲区28，之后，经由二极管缓冲区46与阴极区48而流动至下部电极16。此外，一部分电子如箭头104所示那样，从IGBT漂移区26流入二极管漂移区44，之后，经由二极管缓冲区46和阴极区48而流动至下部电极16。由于电流以此方式流动，因此如图4所示，随着集电极电压的上升，集电极电流逐渐上升。此外，随着集电极电流的上升，向集电区30与IGBT缓冲区28的边界的pn结的施加电压也上升。当集电极电压上升至图4所示的电压V1时，pn结将导通。于是，空穴从集电区30流入IGBT漂移区26，从而IGBT漂移区26的电阻因电导率调制现象而急剧减少。因此，如图4所示，集电极电压急剧减少至电压V2。之后，在集电极电压的上升的同时，集电极电流急剧地增加。如此，在比较例的半导体装置中，当IGBT导通时，集电极电压瞬间上升至较高的电压V1。即，产生回扫。因此，比较例的半导体装置在IGBT导通时的损耗较大。
与此相对，在图1所示的实施例1的半导体装置10中，在二极管缓冲区46内形成有晶体缺陷区域50。如上所述，在晶体缺陷区域50内电阻较高。因此，电子如图3的箭头102、104所示那样流动的情况被抑制。因此，在实施例1的半导体装置10中，不易产生如图4所示的回扫，从而IGBT导通时的损耗较小。
接下来，对半导体装置10的制造方法进行说明。首先，利用现有公知的方法，如图5所示，形成半导体装置10的下部电极16以外的结构。接着，朝向半导体基板12的下表面照射氦离子。以氦离子在二极管缓冲区46内停止的方式对能量进行调节并照射氦离子。朝向半导体基板12的下表面所照射的氦离子被注入到半导体基板12中，并且在二极管缓冲区46内停止。当氦离子停止时，在该停止位置的附近会形成晶体缺陷。因此，根据该方法，在二极管缓冲区46内以高浓度形成有晶体缺陷(即，晶体缺陷区域50)。即，在二极管缓冲区46内形成有晶体缺陷的浓度的峰值C1。之后，通过形成下部电极16，从而完成半导体装置10。另外，虽然在上述的制造方法中，在半导体基板12内形成n型或p型的各个半导体区域之后注入氦离子，但氦离子的注入也可以在各个半导体区域的形成之前实施。此外，也可以在氦离子的注入之前形成一部分半导体区域，在氦离子的注入之后形成剩余的半导体区域。
另外，在上述的实施例1中，晶体缺陷浓度的峰值C1被形成在区域60内。但是，晶体缺陷浓度的峰值C1只要在与图2的位置D1(即，具有极大值N3的一半的浓度且与极大值N3的位置相比靠上表面侧的位置)相比靠下表面侧的区域62内，则可以处于任意位置。例如，如图6、7所示，峰值C1可以被形成在阴极区48内。此外，图8、9所示，峰值C1可以被形成在极小值N2的深度(即，二极管缓冲区46与阴极区48的边界)的附近。即使是这些结构，也能够通过晶体缺陷而抑制如图3的箭头102、104所示那样流通的电流。即，即使是这些结构，也能够抑制回扫。此外，如图10、11所示，晶体缺陷区域50也可以被形成在半导体基板12的深度方向上的较宽的范围内。即使是这种结构，只要峰值C1处于区域62内，便能够抑制回扫。但是，优选为，晶体缺陷浓度的峰值C1被形成在二极管缓冲区46内。二极管缓冲区46的n型杂质浓度与阴极区48的n型杂质浓度相比较低。因此，二极管缓冲区46的电阻与阴极区48的电阻相比较高。因此，只需将比较少量的晶体缺陷形成在二极管缓冲区46内，便能够使二极管缓冲区46的电阻上升至抑制箭头102、104所示的电子的流动的程度。通过如上述那样将晶体缺陷设为少量，从而能够抑制由晶体缺陷的形成引起的二极管的导通电阻的上升。此外，能够抑制由晶体缺陷的形成引起的二极管的泄漏电流的增大。此外，由于晶体缺陷为少量，因此能够以短时间实施晶体缺陷形成工序，从而能够效率地制造出半导体装置10。此外，更优选为，晶体缺陷浓度的峰值C1如图2所示那样处于区域60内。当如上述那样在二极管缓冲区46内的n型杂质浓度较高的区域60内设定晶体缺陷浓度的峰值C1时，即使在区域60内峰值C1的位置发生些许偏移，回扫的抑制效果也几乎不变。因此，批量生产时，半导体装置10的特性稳定。
此外，在上述的各个实施例中，如图2所示，在半导体基板12的下表面的位置处形成有阴极区48内的n型杂质浓度的峰值N1。但是，如图12所示，也可以在阴极区48的内部的位置处形成有峰值N1。
此外，虽然在上述的各个实施例的半导体装置中形成有IGBT缓冲区28，但也可以不形成有IGBT缓冲区28。即，集电区30可以与IGBT漂移区26相接。
此外，在上述的各个实施例中，单一的上部电极14作为IGBT的发射电极和二极管的阳极电极而发挥作用。但是，也可以在半导体基板12的上表面上形成相互分离的IGBT的发射电极和二极管的阳极电极。
以上，虽然对本发明的具体示例进行了详细说明，但这些只不过是示例，并不对权利要求书进行限定。在权利要求书所记载的技术中，包括对上文所例示的具体示例进行了各种改变、变更的内容。
在本说明书或附图中所说明的技术要素以单独或各种组合的方式而发挥技术上的有用性，并不限定于申请时权利要求所记载的组合。此外，本说明书或附图所例示的技术能够同时实现多个目的，并且实现其中一个目的本身便具有技术上的有用性。

Claims (4)

1.一种半导体装置，其中，
所述半导体装置具有半导体基板，该半导体基板具有绝缘栅双极性晶体管区和二极管区，
在绝缘栅双极性晶体管区内的半导体基板的表面上形成有发射电极，
在二极管区内的半导体基板的表面上形成有阳极电极，
在半导体基板的背面上形成有背面电极，
在绝缘栅双极性晶体管区内形成有：
n型的发射区，其与所述发射电极相接；
p型的体区，其与所述发射电极相接；
n型的绝缘栅双极性晶体管漂移区，其通过所述体区而与所述发射区分离；
p型的集电区，其通过所述绝缘栅双极性晶体管漂移区而与所述体区分离，并且与所述背面电极相接；
栅绝缘膜，其与所述体区相接；
栅电极，其隔着所述栅绝缘膜而与所述体区对置，
在二极管区内形成有：
p型的阳极区，其与所述阳极电极相接；
n型的二极管漂移区，其相对于所述阳极区在所述背面侧邻接，并且与所述绝缘栅双极性晶体管漂移区相连；
n型的缓冲区，其相对于所述二极管漂移区在所述背面侧邻接；
n型的阴极区，其相对于所述缓冲区在所述背面侧邻接，并且与所述背面电极相接，
在对从所述表面朝向所述背面的方向上的n型杂质浓度分布进行观察时，在所述阴极区与所述缓冲区的边界处形成有n型杂质浓度的极小值，并且在所述缓冲区内形成有n型杂质浓度的极大值，
所述阴极区内的n型杂质浓度的峰值以及所述极大值与所述二极管漂移区的n型杂质浓度相比较高，
在所述缓冲区与所述阴极区中的至少一方内形成有与周围相比以高浓度分布有晶体缺陷的晶体缺陷区域，
对从所述表面朝向所述背面的方向上的所述晶体缺陷的浓度分布进行观察时的所述晶体缺陷的浓度的峰值被形成在与如下的位置相比靠所述背面侧的区域内，所述位置为与所述极大值的位置相比靠所述表面侧且具有所述极大值的一半的n型杂质浓度的位置。
2.如权利要求1所述的半导体装置，其中，
所述晶体缺陷的浓度的所述峰值被形成在所述缓冲区内。
3.如权利要求2所述的半导体装置，其中，
所述晶体缺陷的浓度的所述峰值被形成在具有与所述极大值的一半的n型杂质浓度相比较高的n型杂质浓度的区域内。
4.一种制造权利要求1至3中任意一项所述的半导体装置的方法，其中，
包括通过向半导体基板注入带电粒子从而形成所述晶体缺陷区域的工序。
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