WO2016129041A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2016129041A1 WO2016129041A1 PCT/JP2015/053540 JP2015053540W WO2016129041A1 WO 2016129041 A1 WO2016129041 A1 WO 2016129041A1 JP 2015053540 W JP2015053540 W JP 2015053540W WO 2016129041 A1 WO2016129041 A1 WO 2016129041A1
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Definitions
- the present invention relates to a semiconductor device used for a high withstand voltage power module ( ⁇ 600 V).
- the forward voltage drop VF has been reduced by applying a thinning process and optimizing the cathode profile (see, for example, Non-Patent Document 1).
- thinning of the wafer is effective for lowering VF, but the margin for snap-off at the time of recovery is reduced, and the risk of element breakage increases.
- recovery SOA Safe
- Improvement of Operating Area has been achieved (see, for example, Non-Patent Document 2).
- Non-Patent Document 3 The field strength of the p-type layer and the n-type layer which is repeatedly formed alternately on the back side of the active region in addition to the main junction cathode side snap-off phenomenon is suppressed increasingly, n according to which - -type drift layer In the low to medium breakdown voltage class of 600 to 1700 V, it has been demonstrated that the total loss can be reduced by the benefit of the thin plate (see Non-Patent Document 3, for example).
- the substrate concentration is increased and the thickness of the n -- type drift layer is designed to be thin in order to reduce the total loss while securing the withstand voltage, in the vicinity of the breakdown start point which greatly exceeded the rated voltage It leads to destruction simultaneously with avalanche. For this reason, there is a limit to thinning of the wafer thickness in applications requiring operation guarantee at the time of avalanche.
- the back surface structure of the termination is the entire n + -type layer, the carrier concentration in the termination region is high from the on state to the termination region. Therefore, there is a problem that holes concentrate at the contact end of the boundary between the active region and the termination region at the time of turn-off operation, and the local temperature increase ( ⁇ 800 K) leads to destruction.
- the present invention has been made to solve the problems as described above, and its object is to suppress the snap-off phenomenon at the end of the turn-off operation and the oscillation phenomenon triggered by it, and A semiconductor device capable of preventing destruction at the boundary of the termination region and improving avalanche resistance at the time of the off operation and the turn-off operation is obtained.
- a semiconductor device is a semiconductor device in which a termination region is disposed outside an active region, and includes an n-type drift layer having opposed surfaces and a back surface, and the n-type drift layer in the active region.
- the distance by which the n-type layer overhangs to the active region side from the end portion of W is WGR1, and 10 ⁇ m ⁇ WGR1 ⁇ 500 ⁇ m is satisfied.
- an n-type layer is formed on the back surface of the n-type buffer layer in the boundary region between the active region and the termination region, and the distance WGR1 of the n-type layer overhanging on the active region side satisfies 10 ⁇ m ⁇ WGR1 ⁇ 500 ⁇ m.
- FIG. 1 is a cross-sectional view showing a semiconductor device according to Embodiment 1 of the present invention.
- FIG. 1 is a bottom view showing a semiconductor device in accordance with a first embodiment of the present invention.
- FIG. 16 is a bottom view showing a modified example of the semiconductor device in accordance with the first embodiment of the present invention.
- FIG. 16 is a bottom view showing a modified example of the semiconductor device in accordance with the first embodiment of the present invention.
- FIG. 5 is a cross-sectional view showing a semiconductor device in accordance with a second embodiment of the present invention.
- FIG. 7 is a bottom view showing a semiconductor device in accordance with a second embodiment of the present invention. It is sectional drawing which shows the semiconductor device concerning Embodiment 3 of this invention.
- FIG. 7 is a bottom view showing a semiconductor device according to Embodiment 3 of the present invention. It is sectional drawing which shows the semiconductor device concerning Embodiment 4 of this invention.
- FIG. 20 is a bottom view showing the semiconductor device in the fourth embodiment of the present invention. It is sectional drawing which shows the semiconductor device concerning Embodiment 5 of this invention. It is sectional drawing which shows the semiconductor device concerning Embodiment 6 of this invention. It is sectional drawing which shows the semiconductor device based on Embodiment 7 of this invention. It is sectional drawing which shows the semiconductor device concerning Embodiment 8 of this invention. It is sectional drawing which shows the semiconductor device concerning Embodiment 9 of this invention. It is sectional drawing which shows the semiconductor device based on Embodiment 10 of this invention.
- FIG. 35 is a cross-sectional view showing a semiconductor device in accordance with a thirteenth embodiment of the present invention.
- FIG. 44 is a cross sectional view showing a semiconductor device in accordance with a fourteenth embodiment of the present invention. It is sectional drawing which shows the semiconductor device concerning Embodiment 15 of this invention.
- FIG. 61 is a cross sectional view showing a semiconductor device in accordance with a sixteenth embodiment of the present invention.
- FIG. 66 is a bottom view showing a semiconductor device in accordance with a sixteenth embodiment of the present invention.
- FIG. 51 is a bottom view showing a modified example of the semiconductor device in accordance with the sixteenth embodiment of the present invention.
- FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention.
- a termination region is disposed outside the active region.
- the n ⁇ -type drift layer 1 has a front surface and a back surface facing each other.
- a p-type anode layer 2 is formed on the surface of the n ⁇ -type drift layer 1 in the active region.
- the end of the p-type anode layer 2 coincides with the end of the active region.
- a typical p-type guard ring layer 3 and a channel stopper layer 4 are formed on the surface of the n ⁇ -type drift layer 1 in the termination region.
- the anode electrode 5 is in ohmic contact with the p-type anode layer 2 through the opening of the interlayer film 6.
- An n-type buffer layer 7 is formed on the back surface of the n ⁇ -type drift layer 1.
- An n-type cathode layer 8 and a p-type cathode layer 9 are formed side by side on the back surface of the n-type buffer layer 7.
- An n-type layer 10 is formed side by side with the n-type cathode layer 8 and the p-type cathode layer 9 on the back surface of the n-type buffer layer 7 in the boundary region between the active region and the termination region.
- the n-type layer 10 has the same impurity concentration as the n-type cathode layer 8.
- the cathode electrode 11 is in ohmic contact with the n-type cathode layer 8, the p-type cathode layer 9 and the n-type layer 10.
- the distance that the n-type layer 10 extends to the active region side from the end of the active region is WGR1, and the distance from the end of the active region to the end region is WGR2.
- FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment of the present invention.
- the patterns of the p-type cathode layer 9 and the n-type cathode layer 8 are arranged in a lattice shape perpendicularly to the long side of the chip.
- 3 and 4 are bottom views showing modifications of the semiconductor device according to the first embodiment of the present invention.
- the patterns of the p-type cathode layer 9 and the n-type cathode layer 8 are arranged in a lattice shape in parallel to the long side of the chip.
- the patterns of the p-type cathode layer 9 and the n-type cathode layer 8 are arranged in a ring shape.
- the conventional structure in which the p-type cathode layer 9 is formed in the boundary region and the terminal region is compared with the present embodiment in which the n-type layer 10 is formed.
- Both are diodes in which an FLR (Field Limiting Ring) structure is formed on the surface of the termination region, and a repeated structure of p layer and n layer is formed on the back surface of the active region.
- FLR Field Limiting Ring
- FIG. 5 is a diagram showing a sample of the conventional structure with avalanche breakdown.
- Si bumps were observed at the tip end of the anode at the tip corner, and melting marks were found in the Si immediately below the interlayer. From this result, the final stage of the destruction mechanism is considered to be thermal destruction due to over current.
- FIG. 6 is a diagram showing the result of simulating the internal state at the time of reverse bias application.
- NDR Negative Differential Resistance
- the principle of avalanche breakdown of the conventional structure is basically the same as the principle of secondary breakdown of a bipolar transistor, "the operation where carriers generated by impact ionization due to high electric field act as a base current and continue on operation" You can say that.
- FIG. 7 is a diagram simulating the recovery characteristic.
- FIG. 8 is a view showing the hole density and the electric field strength of the conventional structure
- FIG. 9 is a view showing the hole density and the electric field strength of the present embodiment.
- the result that the surge voltage is higher than that of the conventional structure was obtained.
- the internal analysis at each recovery timing was conducted to investigate the cause of the surge voltage increase.
- the depletion layer extends gently to the cathode side immediately above the p-type cathode layer on the back surface of the termination region.
- FIG. 10 is a diagram showing the results of measuring the room temperature withstand voltage characteristics for the 1200 V prototype lot.
- the p-type cathode layer was formed on the back surface of the termination region, breakdown occurred at around 1500 V simultaneously with the onset of breakdown.
- the avalanche resistance can be improved as intended.
- FIG. 11 is a diagram showing the snap-off characteristic.
- FIG. 12 is a diagram showing the WGR1 and WGR2 dependencies of the secondary breakdown start current and the maximum controllable current.
- WGR1 and WGR2 approach 0, the secondary breakdown start current decreases but the maximum controllable current increases.
- WGR1 and WGR2 increase, the maximum controllable current decreases but the secondary breakdown start current increases. Therefore, it is necessary to satisfy 10 ⁇ m ⁇ WGR1 ⁇ 500 ⁇ m and to satisfy 10 ⁇ m ⁇ WGR2 ⁇ 500 ⁇ m.
- the operation of the parasitic pnp transistor is suppressed by forming the n-type layer 10 on the back surface of the boundary region between the active region and the termination region. It is possible to prevent destruction at the boundary of the region and to improve avalanche resistance at the time of the off operation and the turn off operation.
- electric field concentration is likely to occur at the end of the active region due to the curvature of the diffusion layer, and rapid depletion of carriers inside the device, which is a trigger for voltage / current waveform oscillation during recovery operation, is likely to occur first. For this reason, as the p-type cathode layer 9 is separated from the end of the active region, voltage / current waveform oscillation at the time of recovery operation tends to occur.
- the distances WGR1 and WGR2 in which the n-type layer 10 protrudes to the active region side and the termination region side are set so as to satisfy 10 ⁇ m ⁇ WGR1 ⁇ 500 ⁇ m and 10 ⁇ m ⁇ WGR2 ⁇ 500 ⁇ m.
- FIG. 13 is a cross-sectional view showing a semiconductor device according to the second embodiment of the present invention.
- FIG. 14 is a bottom view showing the semiconductor device according to the second embodiment of the present invention.
- the n-type layer 10 has the same impurity concentration as the n-type buffer layer 7.
- the other configuration is the same as that of the first embodiment, and the same effect as that of the first embodiment can be obtained.
- FIG. 15 is a cross-sectional view showing a semiconductor device according to the third embodiment of the present invention.
- FIG. 16 is a bottom view showing the semiconductor device according to the third embodiment of the present invention.
- the p-type cathode layer 9 is not formed in the termination region.
- the other configuration is the same as that of the first embodiment, and the same effect as that of the first embodiment can be obtained.
- FIG. 17 is a cross-sectional view showing a semiconductor device according to the fourth embodiment of the present invention.
- FIG. 18 is a bottom view showing the semiconductor device according to the fourth embodiment of the present invention.
- the n-type layer 10 has the same impurity concentration as the n-type buffer layer 7 and the p-type cathode layer 9 is not formed in the termination region.
- the other configuration is the same as that of the first embodiment, and the same effect as that of the first embodiment can be obtained.
- FIG. 19 is a cross-sectional view showing a semiconductor device according to the fifth embodiment of the present invention.
- a p-type cathode layer 9 having a width Wp1 is adjacent to an end of the n-type layer 10 on the active region side.
- the other configuration is the same as that of the first embodiment, and the same effect as that of the first embodiment can be obtained.
- the built-in potential Vin ⁇ ⁇ buffer ⁇ I e ⁇ xdx.
- Ie 200 A / cm 2
- acceptor density NA of p-type cathode layer 9 is 1E17 / cm 3
- donor density ND of n-type buffer layer 7 is 3E16 / cm 3
- peak concentration N buffer of n-type buffer layer 7 is 3E16 / cm 2
- the thickness of the n-type buffer layer 7 is 1.5 [mu] m
- Wp1 for more than the built-in potential of about 0.79V is derived about 58.5Myuemu.
- FIG. 20 is a cross-sectional view showing a semiconductor device according to the sixth embodiment of the present invention.
- a p-type cathode layer 9 having a width Wp2 is adjacent to an end of the n-type layer 10 on the termination region side.
- the other configuration is the same as that of the first embodiment, and the same effect as that of the first embodiment can be obtained.
- FIG. 21 is a cross-sectional view showing a semiconductor device according to a seventh embodiment of the present invention.
- the n-type layer 10 has the same impurity concentration as the n-type buffer layer 7.
- the other configuration is the same as that of the fifth embodiment, and the same effect as that of the fifth embodiment can be obtained.
- FIG. 22 is a cross-sectional view showing a semiconductor device according to the eighth embodiment of the present invention.
- the n-type layer 10 has the same impurity concentration as the n-type buffer layer 7.
- the other configuration is the same as that of the sixth embodiment, and the same effect as that of the sixth embodiment can be obtained.
- FIG. 23 is a cross-sectional view showing a semiconductor device according to the ninth embodiment of the present invention.
- the n-type cathode layer 8 is adjacent to the end of the n-type layer 10 on the active region side.
- the other configuration is the same as that of the eighth embodiment, and the same effect as that of the eighth embodiment can be obtained.
- FIG. 24 is a cross-sectional view showing a semiconductor device according to the tenth embodiment of the present invention.
- p -- type layers 12a and 12b having a concentration lower than that of p-type cathode layer 9 are formed on the back surface of n-type buffer layer 7 and adjacent to the active region side and termination region side of n-type layer 10, respectively.
- the other configuration is the same as that of the eighth embodiment, and the same effect as that of the eighth embodiment can be obtained.
- the widths Wp1 and Wp2 of the p -- type layers 12a and 12b are preferably designed to be about several tens of ⁇ m.
- FIG. 25 is a cross-sectional view showing a semiconductor device according to the eleventh embodiment of the present invention.
- p ⁇ -type layer 13 instead of n-type layer 10 of the first embodiment, p ⁇ -type layer 13 having a lower concentration than p-type cathode layer 9 is the back surface of n-type buffer layer 7 in the boundary region between the active region and the termination region. Are formed side by side with the n-type cathode layer 8 and the p-type cathode layer 9.
- the distance that the p - type layer 13 extends to the active region side from the end of the active region is WGR1, and the distance from the end of the active region to the end area is the distance that the p - type layer 13 extends to the termination region WGR2 and 10 ⁇ m ⁇ WGR1 ⁇ 500 ⁇ m and 10 ⁇ m ⁇ WGR2 ⁇ 500 ⁇ m are satisfied.
- the other configuration is the same as that of the first embodiment, and the same effect as that of the first embodiment can be obtained.
- FIG. 26 is a cross-sectional view showing a semiconductor device according to the twelfth embodiment of the present invention.
- a p-type cathode layer 9 having widths Wp1 and Wp2 is adjacent to the active region side and the termination region side of the p -- type layer 13, respectively.
- the other configuration is the same as that of the eleventh embodiment, and the same effect as that of the eleventh embodiment can be obtained.
- FIG. 27 is a cross-sectional view showing a semiconductor device according to the thirteenth embodiment of the present invention.
- the n-type cathode layer 8 is adjacent to the end on the active region side of the p ⁇ -type layer 13.
- the other configuration is the same as that of the eleventh embodiment, and the same effect as that of the eleventh embodiment can be obtained.
- FIG. 28 is a cross sectional view showing a semiconductor device in accordance with a fourteenth embodiment of the present invention.
- the n-type cathode layer 8 is adjacent to the end on the termination region side of the p ⁇ -type layer 13.
- the other configuration is the same as that of the eleventh embodiment, and the same effect as that of the eleventh embodiment can be obtained.
- FIG. 29 is a cross-sectional view showing a semiconductor device according to the fifteenth embodiment of the present invention.
- the n-type layer 10 and the n-type cathode layer 8 are deeper than the p-type cathode layer 9 and the peak concentration is twice or more higher.
- the n-type layer 10 and the n-type cathode layer 8 contain the impurities of the p-type cathode layer 9. With this configuration, after the p-type cathode layer 9 is formed on the entire surface, the n-type layer 10 and the n-type cathode layer 8 can be partially cancelled. Therefore, the process flow can be simplified and the concern of the influence of the electrical characteristics due to the pattern deviation can be eliminated.
- FIG. 30 is a cross sectional view showing a semiconductor device in accordance with a sixteenth embodiment of the present invention.
- 31 is a bottom view showing a semiconductor device according to the sixteenth embodiment of the present invention.
- the n-type layers 10 of the first to tenth embodiments are arranged in a plurality of rings in plan view.
- FIG. 32 is a bottom view showing a modification of the semiconductor device according to the sixteenth embodiment of the present invention.
- the n-type layers 10 of the first to tenth embodiments are arranged in a dot shape in plan view.
- the p ⁇ -type layers 13 according to the eleventh to fifteenth embodiments may be arranged in a plurality of rings or dots in plan view. Even in this case, the same effects as in Embodiments 1 to 15 can be obtained.
- the semiconductor device is not limited to one formed of silicon, and may be formed of a wide band gap semiconductor having a larger band gap than silicon.
- the wide band gap semiconductor is, for example, silicon carbide, gallium nitride based material, or diamond.
- a semiconductor device formed of such a wide band gap semiconductor can be miniaturized because of high voltage resistance and allowable current density. By using this miniaturized device, it is possible to miniaturize a semiconductor module incorporating this device. Further, since the heat resistance of the device is high, the heat radiation fins of the heat sink can be miniaturized, and the water cooling portion can be air cooled, so that the semiconductor module can be further miniaturized. In addition, since the power loss of the device is low and the efficiency is high, the semiconductor module can be highly efficient.
- the low and medium breakdown voltage class diodes of 1200 V and 1700 V are described as an example, but a semiconductor device having a parasitic bipolar transistor structure inside, such as IGBT or RC-IGBT, regardless of the breakdown voltage class If it is, the above effect is exhibited.
- a semiconductor device having a parasitic bipolar transistor structure inside such as IGBT or RC-IGBT, regardless of the breakdown voltage class If it is, the above effect is exhibited.
- the termination structure is FLR
- the same effects as described above can be obtained with a variable lateral doping (VLD) structure or a reduced surface field (RESURF) structure.
- VLD variable lateral doping
- RESURF reduced surface field
- n ⁇ type drift layer 1 n ⁇ type drift layer, 2 p type anode layer, 7 n type buffer layer, 8 n type cathode layer, 9 p type cathode layer, 10 n type layer, 12 a, 12 b, 13 p ⁇ type layer
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Abstract
Description
図1は、本発明の実施の形態1に係る半導体装置を示す断面図である。活性領域の外側に終端領域が配置されている。n-型ドリフト層1は互いに対向する表面と裏面を持つ。
図13は、本発明の実施の形態2に係る半導体装置を示す断面図である。図14は、本発明の実施の形態2に係る半導体装置を示す下面図である。本実施の形態ではn型層10はn型バッファ層7と同じ不純物濃度を有する。その他の構成は実施の形態1と同様であり、実施の形態1と同様の効果を得ることができる。
図15は、本発明の実施の形態3に係る半導体装置を示す断面図である。図16は、本発明の実施の形態3に係る半導体装置を示す下面図である。本実施の形態では終端領域にp型カソード層9が形成されていない。その他の構成は実施の形態1と同様であり、実施の形態1と同様の効果を得ることができる。
図17は、本発明の実施の形態4に係る半導体装置を示す断面図である。図18は、本発明の実施の形態4に係る半導体装置を示す下面図である。本実施の形態ではn型層10はn型バッファ層7と同じ不純物濃度を有し、終端領域にp型カソード層9が形成されていない。その他の構成は実施の形態1と同様であり、実施の形態1と同様の効果を得ることができる。
図19は、本発明の実施の形態5に係る半導体装置を示す断面図である。本実施の形態ではn型層10の活性領域側の端部に幅Wp1を持ったp型カソード層9が隣接している。その他の構成は実施の形態1と同様であり、実施の形態1と同様の効果を得ることができる。
図20は、本発明の実施の形態6に係る半導体装置を示す断面図である。本実施の形態ではn型層10の終端領域側の端部に幅Wp2を持ったp型カソード層9が隣接している。その他の構成は実施の形態1と同様であり、実施の形態1と同様の効果を得ることができる。実施の形態5と同様に幅Wp2を数10μm程度に設計することが好ましい。
図21は、本発明の実施の形態7に係る半導体装置を示す断面図である。本実施の形態ではn型層10はn型バッファ層7と同じ不純物濃度を有する。その他の構成は実施の形態5と同様であり、実施の形態5と同様の効果を得ることができる。
図22は、本発明の実施の形態8に係る半導体装置を示す断面図である。本実施の形態ではn型層10はn型バッファ層7と同じ不純物濃度を有する。その他の構成は実施の形態6と同様であり、実施の形態6と同様の効果を得ることができる。
図23は、本発明の実施の形態9に係る半導体装置を示す断面図である。本実施の形態ではn型層10の活性領域側の端部にn型カソード層8が隣接している。その他の構成は実施の形態8と同様であり、実施の形態8と同様の効果を得ることができる。
図24は、本発明の実施の形態10に係る半導体装置を示す断面図である。本実施の形態ではp型カソード層9より濃度が低いp-型層12a,12bがn型バッファ層7の裏面に形成され、それぞれn型層10の活性領域側と終端領域側に隣接している。その他の構成は実施の形態8と同様であり、実施の形態8と同様の効果を得ることができる。実施の形態5と同様にp-型層12a,12bの幅Wp1,Wp2を数10μm程度に設計することが好ましい。
図25は、本発明の実施の形態11に係る半導体装置を示す断面図である。本実施の形態では、実施の形態1のn型層10の代わりに、p型カソード層9より濃度が低いp-型層13が活性領域と終端領域の境界領域においてn型バッファ層7の裏面にn型カソード層8及びp型カソード層9と横並びに形成されている。活性領域の端部を起点にしてp-型層13が活性領域側に張り出した距離がWGR1であり、活性領域の端部を起点にしてp-型層13が終端領域側に張り出した距離がWGR2であり、10μm≦WGR1≦500μmと10μm≦WGR2≦500μmを満たす。その他の構成は実施の形態1と同様であり、実施の形態1と同様の効果を得ることができる。
図26は、本発明の実施の形態12に係る半導体装置を示す断面図である。幅Wp1,Wp2を持ったp型カソード層9がそれぞれp-型層13の活性領域側と終端領域側に隣接している。その他の構成は実施の形態11と同様であり、実施の形態11と同様の効果を得ることができる。実施の形態5と同様に幅Wp1,Wp2を数10μm程度に設計することが好ましい。
図27は、本発明の実施の形態13に係る半導体装置を示す断面図である。本実施の形態ではp-型層13の活性領域側の端部にn型カソード層8が隣接している。その他の構成は実施の形態11と同様であり、実施の形態11と同様の効果を得ることができる。
図28は、本発明の実施の形態14に係る半導体装置を示す断面図である。本実施の形態ではp-型層13の終端領域側の端部にn型カソード層8が隣接している。その他の構成は実施の形態11と同様であり、実施の形態11と同様の効果を得ることができる。
図29は、本発明の実施の形態15に係る半導体装置を示す断面図である。n型層10及びn型カソード層8はp型カソード層9よりも深さが深く、ピーク濃度が2倍以上高い。n型層10及びn型カソード層8中にp型カソード層9の不純物が含まれる。この構成であれば、p型カソード層9を全面形成した後、n型層10及びn型カソード層8を部分的に打ち消して形成することができる。従って、プロセスフローが簡略化でき、パターンずれによる電気特性の影響の懸念をなくすことができる。
図30は、本発明の実施の形態16に係る半導体装置を示す断面図である。図31は、本発明の実施の形態16に係る半導体装置を示す下面図である。実施の形態1~10のn型層10が平面視において複数のリング状に配置されている。図32は、本発明の実施の形態16に係る半導体装置の変形例を示す下面図である。実施の形態1~10のn型層10が平面視においてドット状に配置されている。また、実施の形態11~15のp-型層13が平面視において複数のリング状又はドット状に配置されていてもよい。この場合でも実施の形態1~15と同様の効果を得ることができる。
Claims (13)
- 活性領域の外側に終端領域が配置された半導体装置であって、
互いに対向する表面と裏面を持つn型ドリフト層と、
前記活性領域において前記n型ドリフト層の前記表面に形成されたp型アノード層と、
前記n型ドリフト層の前記裏面に形成されたn型バッファ層と、
前記n型バッファ層の裏面に互いに横並びに形成されたn型カソード層及びp型カソード層と、
前記活性領域と前記終端領域の境界領域において前記n型バッファ層の裏面に前記n型カソード層及び前記p型カソード層と横並びに形成されたn型層とを備え、
前記活性領域の端部を起点にして前記n型層が前記活性領域側に張り出した距離がWGR1であり、
10μm≦WGR1≦500μmを満たすことを特徴とする半導体装置。 - 前記活性領域の端部を起点にして前記n型層が前記終端領域側に張り出した距離がWGR2であり、
10μm≦WGR2≦500μmを満たすことを特徴とする請求項1に記載の半導体装置。 - 前記n型層は、前記n型カソード層と同じ不純物濃度を有することを特徴とする請求項1又は2に記載の半導体装置。
- 前記n型層は、前記n型バッファ層と同じ不純物濃度を有することを特徴とする請求項1又は2に記載の半導体装置。
- 前記n型層の前記活性領域側の端部に前記p型カソード層が隣接していることを特徴とする請求項1~4の何れか1項に記載の半導体装置。
- 前記n型層の前記終端領域側の端部に前記p型カソード層が隣接していることを特徴とする請求項1~5の何れか1項に記載の半導体装置。
- 前記n型層の前記活性領域側の端部に前記n型カソード層が隣接していることを特徴とする請求項4に記載の半導体装置。
- 前記n型バッファ層の裏面に形成され、前記n型層の前記活性領域側と前記終端領域側の少なくとも一方に隣接し、前記p型カソード層より濃度が低いp型層を更に備えることを特徴とする請求項1~4の何れか1項に記載の半導体装置。
- 前記n型層及び前記n型カソード層は前記p型カソード層よりも深さが深く、ピーク濃度が2倍以上高く、
前記n型層及び前記n型カソード層中に前記p型カソード層の不純物が含まれることを特徴とする請求項3に記載の半導体装置。 - 前記n型層が平面視においてドット状に配置されていることを特徴とする請求項1~9の何れか1項に記載の半導体装置。
- 活性領域の外側に終端領域が配置された半導体装置であって、
互いに対向する表面と裏面を持つn型ドリフト層と、
前記活性領域において前記n型ドリフト層の前記表面に形成されたp型アノード層と、
前記n型ドリフト層の前記裏面に形成されたn型バッファ層と、
前記n型バッファ層の裏面に互いに横並びに形成されたn型カソード層及びp型カソード層と、
前記活性領域と前記終端領域の境界領域において前記n型バッファ層の裏面に前記n型カソード層及び前記p型カソード層と横並びに形成され、前記p型カソード層より濃度が低いp型層とを備え、
前記活性領域の端部を起点にして前記p型層が前記活性領域側に張り出した距離がWGR1であり、
前記活性領域の端部を起点にして前記p型層が前記終端領域側に張り出した距離がWGR2であり、
10μm≦WGR1≦500μmと10μm≦WGR2≦500μmを満たすことを特徴とする半導体装置。 - 前記p型カソード層が前記p型層の前記活性領域側と前記終端領域側の少なくとも一方に隣接していることを特徴とする請求項11に記載の半導体装置。
- 前記p型層が平面視においてドット状に配置されていることを特徴とする請求項11又は12に記載の半導体装置。
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JP2018120990A (ja) * | 2017-01-26 | 2018-08-02 | ローム株式会社 | 半導体装置 |
CN108574015A (zh) * | 2017-03-13 | 2018-09-25 | 三菱电机株式会社 | 半导体装置及电力变换装置 |
CN108574015B (zh) * | 2017-03-13 | 2021-07-06 | 三菱电机株式会社 | 半导体装置及电力变换装置 |
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JP7246423B2 (ja) | 2021-03-16 | 2023-03-27 | ローム株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
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CN107251234B (zh) | 2020-10-09 |
CN107251234A (zh) | 2017-10-13 |
JP6288315B2 (ja) | 2018-03-07 |
DE112015006128T5 (de) | 2017-10-26 |
US20170263785A1 (en) | 2017-09-14 |
JPWO2016129041A1 (ja) | 2017-06-29 |
US10510904B2 (en) | 2019-12-17 |
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