JP2018107303A - 半導体装置、電力変換装置および半導体装置の製造方法 - Google Patents
半導体装置、電力変換装置および半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】本発明に係る半導体装置において、バッファ層は、活性層と接合し不純物濃度のピーク点を1つ有する第1バッファ層(15a)と、第1バッファ層およびドリフト層と接合し、不純物濃度のピーク点を少なくとも1つ有し、第1バッファ層より最大不純物濃度が低い第2バッファ層(15b)とを備え、第2バッファ層の最大不純物濃度は、ドリフト層の不純物濃度よりも高く1.0×1015cm−3以下である。
【選択図】図1
Description
本発明は、パワーモジュール(耐圧(定格電圧)が600V以上)のキーコンポーネントであるIGBT(Insulated Gate Bipolar Transistor)またはダイオードなどのバイポーラ系パワー半導体素子を有する、半導体装置において、以下の特徴(a)〜(d)を有する縦構造領域に関する。
図5〜図17はIGBTの製造方法(その1)を示す断面図である。なお、これらの図面は活性セル領域R1における製造方法を示している。
図18〜図26は、図3に示すRFCダイオードの製造方法を示す断面図である。
図30〜図32は、本発明の実施の形態1に係る半導体装置であるIGBT、PINダイオードおよびRFCダイオードの断面図である。図30〜図32は、それぞれ図4に示した活性セル領域R1内のA2−A2断面に沿った断面図であり、それぞれ図1〜図3に示したIGBT、PINダイオードおよびRFCダイオードの活性セル領域R1内の構成を示している。なお、図31のE−E断面が、発明の原理で述べた図27〜図29の深さの横軸に相当する。図30〜図32に示すN−ドリフト層14は、不純物濃度が1.0×1012〜5.0×1014cm−3で、FZ(Floating Zone)法で作製されたFZウエハを用い形成される。図30に示すIGBTにおいて、Pベース層9とN層11との接合が主接合となる。また、図31に示すPINダイオードおよび図32に示すRFCダイオードにおいて、Pアノード層10とN−ドリフト層14との接合が主接合となる。
図51は、第2構造の第2バッファ層15bのアニーリング後の不純物プロファイルを示している。図51の横軸は深さ(×10−6μm)を、縦軸はN型不純物濃度(cm−3)を示している。また、プロトン(H+)をSiへ導入する際の加速エネルギーが一条件の場合の不純物プロファイルを点線で、二条件の場合の不純物プロファイルを一点鎖線で、理想的な不純物プロファイルを実線で示している。また、実線L56のピークに付した符号は、第2バッファ層15bの各サブバッファ層15b1〜15b4を示している。
実施の形態2では、図32に示すRFCダイオードのNバッファ層15に、実施の形態1で述べた種々の構造パラメータと条件a)〜e)を適用したときの、ダイオード性能の結果(図52〜図60)を説明する。
実施の形態3では、図31に示すPINダイオードのNバッファ層15に、実施の形態1で述べた種々の構造パラメータと条件a)〜e)を適用したときの、ダイオード性能の結果図61〜図63)を説明する。
実施の形態4では、図30に示すトレンチゲート構造のIGBTのNバッファ層15に、実施の形態1で述べた種々の構造パラメータと条件a)〜e)を適用したときの、IGBT性能の結果(図64〜図71)を説明する。
実施の形態5の半導体装置は、図4に示すパワー半導体の構成要素と実施の形態1から実施の形態4に示す特徴的なNバッファ層15との関係により、IGBT及びダイオードのターンオフ時の遮断能力のさらなる向上を図っている。
本実施の形態では、実施の形態1で説明した第1構造または第2構造におけるNバッファ層15の、特に第2バッファ層15bの不純物プロファイルを安定的に製造する方法について説明する。
本実施の形態は、上述した実施の形態1〜5にかかる半導体装置を電力変換装置に適用したものである。本発明は特定の電力変換装置に限定されるものではないが、以下、実施の形態7として、三相のインバータに本発明を適用した場合について説明する。
Claims (37)
- 一方主面及び他方主面を有し、第1導電型のドリフト層を主要構成部として含む半導体基体と、
前記半導体基体内において、前記ドリフト層に対し他方主面側に前記ドリフト層に隣接して形成される第1導電型のバッファ層と、
前記半導体基体の他方主面上に形成される、第1及び第2導電型のうち少なくとも一つの導電型を有する活性層と、
前記半導体基体の一方主面上に形成される第1電極と、
前記活性層上に形成される第2電極と、を備え、
前記バッファ層は、
前記活性層と接合し不純物濃度のピーク点を1つ有する第1バッファ層と、
前記第1バッファ層および前記ドリフト層と接合し、不純物濃度のピーク点を少なくとも1つ有し、前記第1バッファ層より最大不純物濃度が低い第2バッファ層とを備え、
前記第2バッファ層の最大不純物濃度は、前記ドリフト層の不純物濃度よりも高く、1.0×1015cm−3以下である、
半導体装置。 - 請求項1に記載の半導体装置であって、
前記第2バッファ層の第1導電型のドーズ量は、前記ドリフト層の第1導電型のドーズ量より多く、1.0×1014cm−2よりも少ない、
半導体装置。 - 請求項1又は2に記載の半導体装置であって、
前記バッファ層の活性化後の第1導電型のドーズ量に占める前記第2バッファ層の活性化後の第1導電型のドーズ量の割合は、5%以上40%以下である、
半導体装置。 - 請求項1から3のいずれか1項に記載の半導体装置であって、
前記第2バッファ層の最大不純物濃度を前記ドリフト層の不純物濃度で除した値は、2以上1.0×103以下である、
半導体装置。 - 請求項1から4のいずれか1項に記載の半導体装置であって、
前記第2バッファ層の最大不純物濃度を前記第1バッファ層のピーク不純物濃度で除した値は、2×10−5より大きく0.1以下である、
半導体装置。 - 請求項1から5のいずれか1項に記載の半導体装置であって、
前記第1バッファ層の活性化率は前記第2バッファ層の活性化率より高い、
半導体装置。 - 請求項1から6のいずれか1項に記載の半導体装置であって、
前記第2バッファ層は、前記第2バッファ層を構成する半導体のバンドギャップ中に再結合中心となるエネルギー準位を有する、
半導体装置。 - 請求項1から7のいずれか1項に記載の半導体装置であって、
前記第2バッファ層は、不純物濃度のピーク点をそれぞれ一つ有する複数のサブバッファ層の積層構造であり、
前記複数のサブバッファ層のうち最も他方主面側のサブバッファ層である第1サブバッファ層は前記第1バッファ層と接合し、
前記第2バッファ層の最大不純物濃度は、前記複数のサブバッファ層のピーク不純物濃度の最大値であり、
隣接する2つの前記サブバッファ層の不純物濃度のピーク点間の距離は、少なくとも2組の隣接する前記サブバッファ層間で等しい、
半導体装置。 - 請求項8に記載の半導体装置であって、
全ての隣接する2つの前記サブバッファ層の不純物濃度のピーク点間の距離は等しい、
半導体装置。 - 請求項9に記載の半導体装置であって、
前記第1バッファ層と前記第1サブバッファ層の不純物濃度のピーク点間の距離は、隣接する2つの前記サブバッファ層の不純物濃度のピーク点間の距離より小さい、
半導体装置。 - 請求項8から10のいずれか1項に記載の半導体装置であって、
前記複数のサブバッファ層のピーク不純物濃度は、他方主面から一方主面に向かう方向において低下する、
半導体装置。 - 請求項8から11のいずれか1項に記載の半導体装置であって、
前記バッファ層において、一方主面から他方主面に向かう方向における濃度勾配は、前記複数のサブバッファ層において他方主面側のサブバッファ層ほど高く、最も他方主面側のサブバッファ層の濃度勾配は前記第1バッファ層の濃度勾配より低い、
半導体装置。 - 請求項8から12のいずれか1項に記載の半導体装置であって、
前記複数のサブバッファ層のうち少なくとも2つのサブバッファ層の活性化後の不純物プロファイルは、一方主面から他方主面に向けて裾を引く形状である、
半導体装置。 - 請求項8から13のいずれか1項に記載の半導体装置であって、
前記第2バッファ層において、隣接する2つの前記サブバッファ層の接合部の不純物濃度は前記ドリフト層の不純物濃度よりも高い、
半導体装置。 - 請求項1から請求項14のいずれか1項に記載の半導体装置であって、
前記ドリフト層内の一方主面側に第1導電型の絶縁ゲート型のトランジスタ形成領域を有し、
前記活性層は第2導電型を呈し、
前記半導体装置は、
前記トランジスタ形成領域、前記バッファ層、前記活性層、並びに前記第1及び第2電極によりIGBTが形成される素子形成領域と、
前記素子形成領域に隣接して耐圧保持用に設けられる周辺領域とを有する、
半導体装置。 - 請求項15に記載の半導体装置であって、
前記絶縁ゲート型のトランジスタ形成領域のゲートは1又は複数のトレンチゲートである、
半導体装置。 - 請求項15又は16に記載の半導体装置であって、
前記活性層は前記素子形成領域のみに形成され、
前記周辺領域において前記バッファ層上に前記第2電極が設けられる、
半導体装置。 - 請求項15又は16に記載の半導体装置であって、
前記活性層は前記素子形成領域と前記周辺領域に形成され、
前記周辺領域に形成される前記活性層は、前記素子形成領域に形成される前記活性層よりも、第2導電型の不純物濃度が低い、
半導体装置。 - 請求項15又は16に記載の半導体装置であって、
前記周辺領域の前記ドリフト層内の一方主面側に、複数のフローティング状態の第2導電型の不純物領域を有する、
半導体装置。 - 請求項15又は16に記載の半導体装置であって、
前記周辺領域の前記ドリフト層内の一方主面側に、パッシベーション膜とコンタクトを有する第2導電型の不純物領域を有する、
半導体装置。 - 請求項1から14のいずれか1項に記載の半導体装置であって、
前記ドリフト層内の一方主面側に第2導電型の一方電極領域を有し、
前記活性層は第1導電型を呈し、第1導電型の不純物濃度が前記バッファ層より高く設定され、前記活性層が他方電極領域として機能し、
前記半導体装置は、
前記一方電極領域、前記バッファ層、前記活性層、並びに前記第1及び第2電極によりダイオードが形成される素子形成領域と、
前記素子形成領域に隣接して耐圧保持用に設けられる周辺領域とを有する、
半導体装置。 - 請求項21に記載の半導体装置であって、
前記活性層は前記素子形成領域のみに形成され、
前記周辺領域において前記バッファ層上に前記第2電極が設けられる、
半導体装置。 - 請求項1から請求項14のいずれか1項に記載の半導体装置であって、
前記ドリフト層内の一方主面側に第2導電型の一方電極領域を有し、
前記活性層は第1導電型の第1部分活性層と、第2導電型の第2部分活性層とを含み、
前記第1部分活性層の第1導電型の不純物濃度および前記第2部分活性層の第2導電型の不純物濃度は前記バッファ層より高く設定され、
前記第1部分活性層が他方電極領域として機能し、
前記半導体装置は、
前記一方電極領域、前記バッファ層、前記第1及び第2の部分活性層、並びに前記第1及び第2電極によりダイオードが形成される素子形成領域と、
前記素子形成領域に隣接して耐圧保持用に設けられる周辺領域とを有する、
半導体装置。 - 請求項23に記載の半導体装置であって、
前記活性層は前記素子形成領域のみに形成され、
前記周辺領域において前記バッファ層上に前記第2電極が設けられる、
半導体装置。 - 請求項23に記載の半導体装置であって、
前記活性領域に前記第1部分活性層と前記第2部分活性層が形成され、
前記周辺領域に前記第2部分活性層が形成される、
半導体装置。 - 請求項23に記載の半導体装置であって、
前記活性領域に前記第1部分活性層と前記第2部分活性層が形成され、
前記周辺領域に前記第1部分活性層が形成される、
半導体装置。 - 請求項23に記載の半導体装置であって、
前記周辺領域は、前記活性領域を囲む終端領域と、前記終端領域と前記周辺領域の間に挟まれた中間領域とを有し、
前記活性領域に前記第1部分活性層と前記第2部分活性層が形成され、
前記中間領域に前記第1部分活性層が形成され、
前記終端領域に前記第2部分活性層が形成される、
半導体装置。 - 請求項23に記載の半導体装置であって、
前記周辺領域の前記ドリフト層内の一方主面側に、複数のフローティング状態の第2導電型の不純物領域を有する、
半導体装置。 - 請求項23に記載の半導体装置であって、
前記周辺領域の前記ドリフト層内の一方主面側に、パッシベーション膜とコンタクトを有する第2導電型の不純物領域を有する、
半導体装置。 - 請求項1から請求項14のいずれか1項に記載の半導体装置であって、
前記ドリフト層内の一方主面側に第2導電型の一方電極領域を有し、
前記活性層は第1導電型の第1部分活性層と、第2導電型の第2部分活性層とを含み、
前記第1部分活性層の第1導電型の不純物濃度は前記バッファ層より高く設定され、
前記第1部分活性層が他方電極領域として機能し、
前記半導体装置は、
前記一方電極領域、前記バッファ層、前記活性層、並びに前記第1及び第2電極によりPINダイオードが形成される素子形成領域と、
前記素子形成領域に隣接して耐圧保持用に設けられる周辺領域とを有し、
前記素子形成領域に前記第1部分活性層が形成され、
前記周辺領域に前記第2部分活性層が形成される、
半導体装置。 - 一方主面及び他方主面を有し、第1導電型のドリフト層を主要構成部として含む半導体基体と、
前記半導体基体内において、前記ドリフト層に対し他方主面側に前記ドリフト層に隣接して形成される第1導電型のバッファ層と、
前記半導体基体の他方主面上に形成される、第1及び第2導電型のうち少なくとも一つの導電型を有する活性層と、
前記半導体基体の一方主面上に形成される第1電極と、
前記活性層上に形成される第2電極と、を備え、
前記バッファ層は、
前記活性層と接合し不純物濃度のピーク点を1つ有する第1バッファ層と、
前記第1バッファ層および前記ドリフト層と接合し、前記第1バッファ層より最大不純物濃度が低い第2バッファ層とを備え、
前記第2バッファ層は、前記第2バッファ層を構成する半導体のバンドギャップ中に再結合中心となるエネルギー準位を有する、
半導体装置。 - 請求項1から31のいずれか1項に記載の半導体装置の製造方法であって、
(a)半導体基体の他方主面側から第1イオンを注入する工程と、
(b)前記第1イオンをアニールにより活性化させて前記第1バッファ層を形成する工程と、
(c)前記工程(b)の後、前記半導体基体の他方主面側から第2イオンを注入する工程と、
(d)前記第2イオンをアニールにより活性化させて前記第2バッファ層を形成する工程と、を備える、
半導体装置の製造方法。 - 請求項32に記載の半導体装置の製造方法であって、
前記工程(c)、(d)の間に、
(c1)前記半導体基体の他方主面上に活性層を形成する工程をさらに備える、
半導体装置の製造方法。 - 請求項32に記載の半導体装置の製造方法であって、
前記工程(b)、(c)の間に、
(b1)前記半導体基体の他方主面上に活性層を形成する工程をさらに備える、
半導体装置の製造方法。 - 請求項32に記載の半導体装置の製造方法であって、
前記工程(b1)、(c)の間に、
(b2)前記活性層上に第2電極を形成する工程をさらに備える、
半導体装置の製造方法。 - 請求項32に記載の半導体装置の製造方法であって、
前記工程(b1)、(c)の間に、
(b3)前記活性層上に複数層で構成される第2電極の一部の層を形成する工程をさらに備え、
前記工程(d)の後に、
(e)前記第2電極の残りの層を形成する工程をさらに備える、
半導体装置の製造方法。 - 請求項1から31のいずれか1項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路と、を備える、
電力変換装置。
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