JP2018056163A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 206
- 238000003475 lamination Methods 0.000 abstract 3
- 239000000758 substrate Substances 0.000 description 35
- 239000012535 impurity Substances 0.000 description 23
- 238000004519 manufacturing process Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Abstract
【解決手段】本発明による半導体装置は、n型のn−i層3と、n−i層3の表面に形成されたp型のpアノード層4と、n−i層3の裏面に形成されたn型のn−バッファ層7と、n−バッファ層7の裏面、またはn−i層3およびn−バッファ層7の裏面に、平面視において互いに隣接または隣接部分が重なって形成されたn型のn+カソード層5およびp型のpコレクタ層6と、pアノード層4の表面を覆うように形成された表面電極8と、n+カソード層5およびpコレクタ層6の裏面を覆うように形成された裏面電極9とよりなる積層構造を備え、n+カソード層5の積層構造における積層高さ位置と、pコレクタ層6の積層構造における積層高さ位置とは異なる。
【選択図】図1
Description
まず、本発明の前提となる技術である前提技術について説明する。
<構成>
まず、本発明の実施の形態による半導体装置の構成について説明する。図1は、本実施の形態1による半導体装置1の構成の一例を示す断面図である。
次に、半導体装置1の製造方法について説明する。
図2は、本発明の実施の形態2による半導体装置12の構成の一例を示す断面図である。
図3は、本発明の実施の形態3による半導体装置13の構成の一例を示す断面図である。
図4は、本発明の実施の形態4による半導体装置14の構成の一例を示す断面図である。
図5は、本発明の実施の形態5による半導体装置17の構成の一例を示す断面図である。
Claims (9)
- 第1導電型の第1半導体層と、
前記第1半導体層の表面に形成された第2導電型の第2半導体層と、
前記第1半導体層の裏面に形成された前記第1導電型の第3半導体層と、
前記第3半導体層の裏面、または前記第1半導体層および前記第3半導体層の裏面に、平面視において互いに隣接または隣接部分が重なって形成された前記第1導電型の第4半導体層および前記第2導電型の第5半導体層と、
前記第2半導体層の表面を覆うように形成された第1電極と、
前記第4半導体層および前記第5半導体層の裏面を覆うように形成された第2電極と、
よりなる積層構造を備え、
前記第4半導体層の前記積層構造における積層高さ位置と、前記第5半導体層の前記積層構造における積層高さ位置とは異なることを特徴とする、半導体装置。 - 前記第4半導体層を含む前記積層構造における前記第1半導体層の厚さと、前記第5半導体層を含む前記積層構造における前記第1半導体層の厚さとは異なることを特徴とする、請求項1に記載の半導体装置。
- 前記第4半導体層を含む前記積層構造における前記第1半導体層の厚さと、前記第5半導体層を含む前記積層構造における前記第1半導体層の厚さとの差は、前記第4半導体層と前記第5半導体層との段差と同じであることを特徴とする、請求項2に記載の半導体装置。
- 前記第4半導体層を含む前記積層構造における前記第1半導体層の厚さと、前記第5半導体層を含む前記積層構造における前記第1半導体層の厚さとの差は、前記第4半導体層と前記第5半導体層との段差と、前記第5半導体層を含む前記積層構造における前記第3半導体層の厚さとを合わせた厚さと同じであることを特徴とする、請求項2に記載の半導体装置。
- 前記第5半導体層の前記積層構造における積層高さ位置は、前記第4半導体層の前記積層構造における積層高さ位置よりも前記第1半導体層側に位置し、かつ前記第4半導体層および前記第5半導体層は、前記隣接部分が重なって形成され、
前記隣接部分が重なっている箇所における前記第5半導体層と前記第4半導体層との間には、前記第5半導体層が形成されていることを特徴とする、請求項2から4のいずれか1項に記載の半導体装置。 - 前記第4半導体層の前記積層構造における積層高さ位置は、前記第5半導体層の前記積層構造における積層高さ位置よりも前記第1半導体層側に位置し、かつ前記第4半導体層および前記第5半導体層は、前記隣接部分が重なって形成され、
前記隣接部分が重なっている箇所における前記第5半導体層と前記第4半導体層との間には、前記第4半導体層が形成されていることを特徴とする、請求項2から4のいずれか1項に記載の半導体装置。 - 前記第4半導体層と前記第2電極との間に形成された第3電極をさらに備え、
前記第4半導体層を含む前記積層構造における前記第1半導体層の厚さと、前記第5半導体層を含む前記積層構造における前記第1半導体層の厚さとの差は、前記第4半導体層と前記第5半導体層との段差と、前記第3電極の厚さとを合わせた厚さであることを特徴とする、請求項2から5のいずれか1項に記載の半導体装置。 - 前記第5半導体層を含む前記積層構造における前記第1半導体層の厚さは、前記第4半導体層を含む前記積層構造における前記第1半導体層の厚さよりも薄いことを特徴とする、請求項2から5のいずれか1項に記載の半導体装置。
- 前記第4半導体層を含む前記積層構造における前記第1半導体層の厚さは、前記第5半導体層を含む前記積層構造における前記第1半導体層の厚さよりも薄いことを特徴とする、請求項2、3、または6のいずれか1項に記載の半導体装置。
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JP2016186769A JP6698487B2 (ja) | 2016-09-26 | 2016-09-26 | 半導体装置 |
US15/480,593 US9960158B2 (en) | 2016-09-26 | 2017-04-06 | Semiconductor device |
DE102017212818.6A DE102017212818B4 (de) | 2016-09-26 | 2017-07-26 | Halbleiteranordnung |
CN201710881263.1A CN107871779A (zh) | 2016-09-26 | 2017-09-26 | 半导体装置 |
CN202210629378.2A CN115064535A (zh) | 2016-09-26 | 2017-09-26 | 半导体装置 |
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Citations (4)
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JP2011507299A (ja) * | 2007-12-19 | 2011-03-03 | アーベーベー・テヒノロギー・アーゲー | 逆導電半導体デバイス及びそのような逆導電半導体デバイスを製造するための方法 |
JP2015095618A (ja) * | 2013-11-14 | 2015-05-18 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
US20160211258A1 (en) * | 2015-01-05 | 2016-07-21 | Maxpower Semiconductor Inc. | Reverse-Conducting Gated-Base Bipolar-Conduction Devices and Methods with Reduced Risk of Warping |
WO2016129041A1 (ja) * | 2015-02-09 | 2016-08-18 | 三菱電機株式会社 | 半導体装置 |
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JP2020021906A (ja) * | 2018-08-03 | 2020-02-06 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP7115124B2 (ja) | 2018-08-03 | 2022-08-09 | 株式会社デンソー | 半導体装置の製造方法 |
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US9960158B2 (en) | 2018-05-01 |
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