CN105378934B - 具有多个注入层的高压场效应晶体管 - Google Patents
具有多个注入层的高压场效应晶体管 Download PDFInfo
- Publication number
- CN105378934B CN105378934B CN201480039829.0A CN201480039829A CN105378934B CN 105378934 B CN105378934 B CN 105378934B CN 201480039829 A CN201480039829 A CN 201480039829A CN 105378934 B CN105378934 B CN 105378934B
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
-
- H10P30/204—
-
- H10P30/212—
-
- H10P30/222—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/051—Forming charge compensation regions, e.g. superjunctions
- H10D62/054—Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
Landscapes
- Physics & Mathematics (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Toxicology (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Composite Materials (AREA)
- Crystallography & Structural Chemistry (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/941,119 | 2013-07-12 | ||
| US13/941,119 US9660053B2 (en) | 2013-07-12 | 2013-07-12 | High-voltage field-effect transistor having multiple implanted layers |
| PCT/US2014/044769 WO2015006074A1 (en) | 2013-07-12 | 2014-06-28 | High-voltage field-effect transistor having multiple implanted layers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105378934A CN105378934A (zh) | 2016-03-02 |
| CN105378934B true CN105378934B (zh) | 2018-12-11 |
Family
ID=52276454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201480039829.0A Active CN105378934B (zh) | 2013-07-12 | 2014-06-28 | 具有多个注入层的高压场效应晶体管 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9660053B2 (enExample) |
| JP (1) | JP6490679B2 (enExample) |
| KR (1) | KR102283496B1 (enExample) |
| CN (1) | CN105378934B (enExample) |
| DE (1) | DE112014003246B4 (enExample) |
| WO (1) | WO2015006074A1 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11355580B2 (en) * | 2019-10-18 | 2022-06-07 | Semiconductor Components Industries, Llc | Lateral DMOS device with step-profiled RESURF and drift structures |
| CN113130632B (zh) | 2019-12-31 | 2022-08-12 | 无锡华润上华科技有限公司 | 横向扩散金属氧化物半导体器件及其制备方法 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6168983B1 (en) * | 1996-11-05 | 2001-01-02 | Power Integrations, Inc. | Method of making a high-voltage transistor with multiple lateral conduction layers |
| US7011998B1 (en) * | 2004-01-12 | 2006-03-14 | Advanced Micro Devices, Inc. | High voltage transistor scaling tilt ion implant method |
| US20110127607A1 (en) * | 2009-12-02 | 2011-06-02 | Fairchild Semiconductor Corporation | Stepped-source ldmos architecture |
| CN102148162A (zh) * | 2010-02-08 | 2011-08-10 | 台湾积体电路制造股份有限公司 | 横向扩散金属氧化物半导体晶体管及其制造方法 |
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| JPS5638867A (en) | 1979-09-07 | 1981-04-14 | Hitachi Ltd | Insulated gate type field effect transistor |
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| JPS5712557A (en) | 1980-06-25 | 1982-01-22 | Sanyo Electric Co Ltd | High dielectric resisting mos transistor |
| GB2089119A (en) | 1980-12-10 | 1982-06-16 | Philips Electronic Associated | High voltage semiconductor devices |
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| US4626879A (en) | 1982-12-21 | 1986-12-02 | North American Philips Corporation | Lateral double-diffused MOS transistor devices suitable for source-follower applications |
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-
2013
- 2013-07-12 US US13/941,119 patent/US9660053B2/en active Active
-
2014
- 2014-06-28 WO PCT/US2014/044769 patent/WO2015006074A1/en not_active Ceased
- 2014-06-28 DE DE112014003246.8T patent/DE112014003246B4/de active Active
- 2014-06-28 CN CN201480039829.0A patent/CN105378934B/zh active Active
- 2014-06-28 KR KR1020167000416A patent/KR102283496B1/ko active Active
- 2014-06-28 JP JP2016525370A patent/JP6490679B2/ja active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6168983B1 (en) * | 1996-11-05 | 2001-01-02 | Power Integrations, Inc. | Method of making a high-voltage transistor with multiple lateral conduction layers |
| US7011998B1 (en) * | 2004-01-12 | 2006-03-14 | Advanced Micro Devices, Inc. | High voltage transistor scaling tilt ion implant method |
| US20110127607A1 (en) * | 2009-12-02 | 2011-06-02 | Fairchild Semiconductor Corporation | Stepped-source ldmos architecture |
| CN102148162A (zh) * | 2010-02-08 | 2011-08-10 | 台湾积体电路制造股份有限公司 | 横向扩散金属氧化物半导体晶体管及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20150014770A1 (en) | 2015-01-15 |
| US9660053B2 (en) | 2017-05-23 |
| JP6490679B2 (ja) | 2019-03-27 |
| WO2015006074A1 (en) | 2015-01-15 |
| KR20160030171A (ko) | 2016-03-16 |
| DE112014003246T5 (de) | 2016-04-07 |
| JP2016526804A (ja) | 2016-09-05 |
| KR102283496B1 (ko) | 2021-07-29 |
| CN105378934A (zh) | 2016-03-02 |
| DE112014003246B4 (de) | 2025-04-03 |
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