TWI712173B - 整合在超級接面功率mosfet中的肖特基二極體 - Google Patents
整合在超級接面功率mosfet中的肖特基二極體 Download PDFInfo
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- TWI712173B TWI712173B TW107142428A TW107142428A TWI712173B TW I712173 B TWI712173 B TW I712173B TW 107142428 A TW107142428 A TW 107142428A TW 107142428 A TW107142428 A TW 107142428A TW I712173 B TWI712173 B TW I712173B
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Abstract
一種溝槽金屬-氧化物-半導體場效應電晶體(MOSFET)元件,包括一個主動晶胞區,主動晶胞區包括複數個超級接面溝槽功率MOSFET,肖特基二極體區包括複數個肖特基二極體,形成在具有超級接面結構的漂流區中。每個整合的肖特基二極體都包括一個肖特基接頭,在輕摻雜的半導體層和金屬層之間。
Description
本發明主要涉及金屬-氧化物-半導體場效應電晶體(MOMSFET),更確切地說是一種超級接面功率MOSFET及其製備方法。
微處理器和儲存元件等積體電路含有複數個金屬-氧化物-半導體場效應電晶體(MOSFET)。MOSFET通常用於需要功率切換和功率放大的應用中。用於功率開關的MOSFET元件有時稱為功率MOSFET。大多數的功率MOSFET的特點是在填充多晶矽的閘極溝槽的對邊上具有一個帶主動極和汲極區的垂直結構,作為閘極電極。
功率MOSFET元件通常包括複數個單獨的MOSFET結構,排布在主動晶胞中。肖特基二極體通常用於低壓功率MOSFET元件(例如小於40伏)。它們有助於改善元件開關動作的二極體恢復部分,並且由於它們較低的正向電壓,從而可以降低功率損耗。另外,在某些應用中(例如直流-直流轉換器),MOSFET快速的接通和斷開可以產生帶有電壓尖峰的開關節點振鈴。鉗位到MOSFET元件的肖特基二極體可以減少這種電壓尖峰。
另一方面,超級接面結構已經用於高壓功率MOSFET元件(例如500伏以上),以獲得很低的導通電阻(Rds-on),同時保持很高的斷開狀態擊穿電壓(BV)。在一個功率MOSFET中,必須降低傳導時的元件電阻(Rds-on),提高其擊穿電壓(BV)。然而,導通電阻(Rds-on)和擊穿電壓(BV)處於一種相互制約的關係。也就是說,對於傳統的電晶體來說,隨著擊穿電壓(BV)的增大,導通電阻(Rds-on)也會劇烈增大。由於超級接面元件包括交替的p-型和n-型摻雜立柱,平行排布,並且在漂流區中相互連接,當汲極和源極之間加載反向偏壓時,這些電荷平衡的立柱在水平方向上相互耗盡。因此,超級接面元件可以在垂直方向上承受很高的擊穿電壓,同時在相同的擊穿電壓下,具有比傳統的MOSFET元件低得多的導通電阻(Rds-on)(或者在指定的導通電阻Rds-on下,具有比傳統的MOSFET元件高得多的擊穿電壓BV)。
正是在這樣的背景下,提出了本發明的實施例。
本發明的目的在於提出一種整合在超級接面功率MOSFET中的肖特基二極體,以改善習知技術中的一個或多個問題。
本發明的一個方面在於提出一種金屬-氧化物-半導體場效應電晶體(MOSFET)元件,包括:一個主動晶胞區,包括複數個超級接面溝槽MOSFET,其中主動晶胞區包括:一個第一導電類型的輕摻雜漂流區,位於相同導電類型的重摻雜基材上方;
一個第二導電類型的本體區,位於漂流區上方,第二導電類型與第一導電類型相反;複數個閘極溝槽,位於本體區中,並延伸到漂流區內,其中複數個閘極溝槽中的每個閘極溝槽都內襯介電質材料,閘極溝槽包括一個閘極電極;一個第一導電類型的重摻雜源極區,位於本體區中;一個源極接頭,位於源極接觸溝槽中,延伸到兩個相鄰的閘極溝槽之間的本體區;以及一個超級接面結構,位於漂流區中,包括交替的第一導電類型的第一摻雜立柱以及平行排布的第二導電類型的第二摻雜立柱,其中第二摻雜立柱位於每個源極接觸溝槽的底部附近;以及一個肖特基二極體區,包括複數個肖特基二極體形成在具有超級接面結構的漂流區中,每個肖特基二極體都包括一個肖特基接頭,在輕摻雜的半導體層和金屬層之間。
其中,肖特基接頭沿肖特基接觸溝槽的一部分垂直側壁形成。
其中,肖特基接頭形成在相鄰的第二摻雜立柱之間的輕摻雜漂流區的表面上。
其中,肖特基接觸溝槽比複數個源極接觸溝槽中的每個源極接觸溝槽都寬。
其中,肖特基接觸溝槽的寬度約為0.5至0.7微米。
其中,肖特基接觸溝槽和相鄰的閘極溝槽之間的縫隙小於0.2微米。
其中,元件的工作電壓在8V至40V之間,複數個閘極溝槽的每個閘極溝槽的間距在1.3至1.7微米之間。
其中,元件的工作電壓為30V,複數個閘極溝槽的每個閘極溝槽的間距在1.3至1.7微米之間。
其中,元件的工作電壓高於100V,複數個閘極溝槽的每個閘極溝槽的間距在3.5至5微米之間。
其中,複數個閘極溝槽的每個閘極溝槽都包括一個在頂部的閘極電極以及一個在底部的遮蔽電極。
其中,形成肖特基接頭的表面是凹陷的。
本發明的另一個方面在於提出一種溝槽金屬-氧化物-半導體場效應電晶體(MOSFET)元件的製備方法,該方法包括:製備一個主動晶胞區,包括複數個超級接面溝槽功率MOSFET,其中製備主動晶胞區包括:製備一個第一導電類型的漂流區,位於相同導電類型的重摻雜基材上方;製備一個第二導電類型的本體區,位於漂流區上方,第二導電類型與第一導電類型相反;製備複數個閘極溝槽,位於本體區中,並延伸到漂流區內,其中內襯介電質材料的複數個閘極溝槽的每個閘極溝槽都含有一個閘極電極;製備一個第一導電類型的重摻雜源極區,位於本體區中;製備一個源極接頭,在源極接觸溝槽中,延伸到兩個相鄰的閘極溝槽之間的本體區;並且製備一個超級接面結構,位於漂流區中,包括交替的第一導電類型的第一摻雜立柱以及平行排布的第二導電類型的第二摻雜立柱,其中第二摻雜立柱的每個立柱都位於每個源極接觸溝槽的底部附近;並且
製備複數個肖特基二極體,在肖特基二極體區中具有超級接面結構的漂流區中,每個肖特基二極體都包括一個肖特基接頭,在輕摻雜半導體層和金屬層之間。
其中,肖特基接頭沿肖特基接觸溝槽的一部分垂直側壁形成。
其中,肖特基接頭形成在相鄰的第二摻雜立柱之間的輕摻雜漂流區的表面上。
其中,肖特基接觸溝槽比複數個源極接觸溝槽的每個源極接觸溝槽都寬。
其中,肖特基接觸溝槽和相鄰的閘極溝槽之間的縫隙小於0.2微米。
其中,製備複數個閘極溝槽包括在漂流區上使用一個閘極溝槽遮罩,不覆蓋主動晶胞區中的閘極溝槽開口以及肖特基二極體區中的閘極溝槽開口的位置。
其中,製備複數個閘極溝槽包括在漂流區上使用一個閘極溝槽遮罩,不覆蓋主動晶胞區中的閘極溝槽開口的位置,覆蓋肖特基二極體區的整個部分。
其中,製備一個本體區包括使用一個本體遮罩,覆蓋著肖特基二極體區的整個部分,留下主動晶胞區不覆蓋。
其中,製備一個源極區包括使用一個本體遮罩,覆蓋著肖特基二極體區的整個部分,留下主動晶胞區不覆蓋。
其中,製備複數個肖特基二極體包括在每個肖特基接觸溝槽下方,製備一個接觸注入區,其中藉由肖特基接觸溝槽開口,利用帶角度的注入,製備接觸注入區。
其中,製備複數個肖特基二極體包括在每個肖特基接觸溝槽下方,製備一個接觸注入區,其中藉由肖特基接觸溝槽開口,利用香農注入,製備接觸注入區。
閱讀以下詳細說明的實施例並參照各種圖式,本發明的這些特點和優勢對於所屬技術領域具有通常知識者來說,無疑將顯而易見。
100:功率MOSFET元件
110:主動晶胞區
120:肖特基二極體區
130:閘極墊
132:閘極滑道
200:功率MOSFET元件
200a:主動晶胞區
200b:肖特基二極體區
202:基材
204:漂流區
206:本體區
208:源極區
210:閘極溝槽
212:閘極電極
214:介電質材料
216:介電質層、絕緣層
220:立柱
230a:極接觸溝槽
230b:肖特基接觸溝槽
232:注入物
300:功率MOSFET元件
310:閘極溝槽
312a:閘極電極
312b:遮蔽電極
400:功率MOSFET元件
400a:主動晶胞區
400b:肖特基二極體區
430:肖特基接觸構成、肖特基接頭
500:功率MOSFET元件
500a:主動晶胞區
500b:肖特基二極體區
530:肖特基接觸溝槽
602~636:步驟
閱讀以下詳細說明並參照圖式之後,本發明的各個方面及優勢將顯而易見:第1圖表示依據本發明的各個方面,一部分功率MOSFET元件的俯視圖。
第2圖表示依據本發明的各個方面,一部分功率MOSFET元件的剖面圖。
第3圖表示依據本發明的各個方面,一部分功率MOSFET元件的剖面圖。
第4圖表示依據本發明的各個方面,一部分功率MOSFET元件的剖面圖。
第5圖表示依據本發明的各個方面,一部分功率MOSFET元件的剖面圖。
第6圖表示依據本發明的各個方面,一種功率MOSFET元件的製備流程圖。
在以下說明中,參照圖式,該圖式形成了本發明的一部分,並且在其中表示出了可以實施本發明的圖示特定實施例的方式。為方便起見,在特定的導電或淨雜質載流子類型(P或N)之後使用+或-,通常指的是半導體材料中指定類型的淨雜質載流子的相對濃度。一般而言,n+材料具有比n材料更高的n型淨摻雜物(例如,電子)濃度,並且n材料具有比n材料更高的載流子濃度。與之類似,p+材料具有比p材料更高的p型淨摻雜物(例如電洞)濃度,並且p材料具有比p材料更高的濃度。要注意的是,相關的是載流子的淨濃度,而不一定是摻雜物。例如,材料可以重摻雜n-型摻雜物,但是如果材料也充分反向摻雜p-型摻雜物,那麼仍然具有相對低的淨載流子濃度。此處所用的摻雜物濃度小於1016/cm3可以認為是“輕摻雜”,摻雜物濃度大於1017/cm3可以認為是“重摻雜”。此處所使用的高壓元件是指工作電壓為400V以上的元件。中壓元件是指工作電壓在40V至400V之間的元件,低壓元件是指工作電壓低於40V的元件,最好是在8V至40V之間。
引言
雖然超級接面元件通常用於高壓應用,但是人們已經提議它們也可以用於低壓應用。在一個示例中,超級接面元件可以用於低壓熱插拔應用。熱插拔時,汲極和源極之間相對很高的電壓以及高電流會導致元件發生故障。超級接面結構有助於降低來自溝槽電極的高電場,從而防止擊穿,並提高性能。
本發明的各個方面提出了與超級接面功率MOSFET元件整合在一起的肖特基二極體,可以用於低壓應用以及中壓或高壓應用。肖特基二極體可以降低體二極體正向電壓降(Vf)並且使儲存的電荷最少,具有快速的反向恢復時間,從而使MOSFET元件更加高效。依據本發明的各個方面,肖特基接頭可以沿肖特基接觸溝槽的側壁形成。依據本發明的其他方面,肖特基接頭可以形成在輕摻雜的半導體層的表面上,在超級接面結構的p立柱之間。
第1圖表示依據本發明的各個方面,一部分功率MOSFET元件的俯視圖。功率MOSFET元件100包括一個主動晶胞區110和一個肖特基二極體區120。在某些實施例中,主動晶胞區110和肖特基二極體區120包含在功率MOSFET元件中的主動晶胞區中。主動晶胞區110包括帶有超級接面結構的元件晶胞的一個陣列。元件中的每個元件晶胞都具有一個閘極電極,在元件溝槽(或閘極溝槽)中。閘極電極可以藉由閘極滑道132連接到閘極墊130。元件晶胞的源極區可以連接到主動晶胞區110內的源極墊(圖中沒有表示出)。肖特基二極體區120具有複數個肖特基二極體。肖特基二極體可以連接到閘極墊130和源極墊,在主動晶胞區110中,用於合適的連接。肖特基二極體的面積小於元件晶胞的面積。作為示例,但不作為局限,肖特基二極體的面積(即肖特基二極體區120)約為功率MOSFET元件100的整個主動晶胞區面積的10%至15%。要注意的是,第1圖表示依據本發明的一個方面,功率MOSFET元件的一種可能的佈局。本發明的其他方面包括可選的元件佈局。在某些實施例中,包括複數個肖特基二極體區,包圍著複數個主動晶胞區110。在某些實施例中,複數個肖特基二極體區位於主動晶胞區110中。另外,閘極電極可以呈條形,但是本發明的可選方面還包括可選的元件佈局,例如但不局限於封閉的晶胞方向。
在以下示例中,功率MOSFET元件表示為一個n-型超級接面溝槽MOSFET元件,其中元件晶胞的源極區和汲極區具有n型導電類型,本體區具有p型導電類型。要注意的是,這些導電類型可以相反,以獲得p-型超級接面溝槽MOSFET。還要注意的是,依據本發明的各個方面,功率MOSFET元件可以是一個單獨的多晶矽MOSFET元件或一個遮蔽柵溝槽MOSFET元件。
第一個示例
第2圖表示依據本發明的一部分功率MOSFET元件的剖面圖。第2圖所示的n-型功率MOSFET元件200包括一個主動晶胞區200a和一個肖特基二極
體區200b。主動晶胞區200a由一個元件晶胞的陣列組成。每個元件晶胞都包括一個n-型輕摻雜的漂流區204,在重摻雜的n-型半導體基材202上方,以及一個形成在漂流區204頂部附近的p-型本體區206。另外,元件晶胞包括一個閘極電極212,形成在閘極溝槽210中,在本體區206和漂流區204中延伸,以及一個重摻雜的n-型源極區208,形成在本體區206的頂部附近,在源極接觸溝槽230a的對邊上。形成在源極接觸溝槽230a中的源極接頭(圖中沒有表示出)提供了一個到源極區208的外部接頭。閘極電極212藉由介電質層216,與源極接頭(圖中沒有表示出)電絕緣。
功率MOSFET元件200具有一個在漂流區中的超級接面結構,包括交替的第一導電類型的第一摻雜立柱(即n立柱)和平行排布的第二導電類型的第二摻雜立柱(即p立柱)。每個p立柱220都形成在源極接觸溝槽230a下方,以及兩個相鄰的閘極溝槽210之間。N立柱可以包括n漂流區204位於p立柱220附近的那一部分。
與主動晶胞區200a類似,肖特基二極體區200b可以包括n+基材202、位於基材202上方的n漂流區204、形成在內襯介電質材料214的閘極溝槽210中的閘極電極212以及一個形成在閘極溝槽210上的絕緣層216。肖特基二極體區200b還包括超級接面結構,具有交替的p摻雜立柱220和n摻雜立柱。一個p立柱220形成在漂流區204中的兩個相鄰的閘極溝槽210之間。N立柱可以包括位於p立柱220附近的那部分n漂流區204。
肖特基接觸溝槽230b形成在漂流區204中,在p立柱220上方的兩個相鄰的閘極溝槽之間。接觸注入物232形成在肖特基接觸溝槽230b底部下方。勢壘金屬(圖中沒有表示出)可以沉積在肖特基接觸溝槽230b的表面上方。作為示例,但不作為局限,勢壘金屬可以是藉由物理氣相沉積(PVD)的鈦(Ti),或者是藉由CVD或PVD沉積的TiN等合金。沉積勢壘金屬之後,可以藉由CVD,
在肖特基接觸溝槽230b中沉積導電材料(鎢)。一旦沉積了一層鎢之後,可以回刻,以便保留源極接觸溝槽230a和肖特基接觸溝槽230b中的鎢。肖特基接頭可以形成在肖特基溝槽230b的側壁上。在整個表面上沉積金屬,並形成圖案,以便為源極區和閘極電極提供合適的接頭。
可以調節肖特基接觸溝槽230b的寬度,以微調漏電流(Idss)。當肖特基接觸溝槽230b較寬時,肖特基溝槽230b和閘極溝槽210之間的縫隙較窄。因此,可以降低漏電流。肖特基接觸溝槽230b比形成在主動晶胞區200a中的源極接觸溝槽230a更寬。作為示例,但不作為局限,主動晶胞區200a中的源極接觸溝槽230a可以具有0.4微米的寬度,對於1.4微米的間距尺寸來說,肖特基接觸溝槽230b的寬度約為0.5至0.7微米。在某些實施例中,肖特基接觸溝槽230b和閘極溝槽210之間的縫隙可以小於0.2微米。另外,對於低壓元件(例如25V)來說,閘極溝槽的間距可以在1.3至1.5微米之間,對於30V的元件來說,間距在1.3至1.7微米之間,對於中壓元件(例如200V)來說,間距在3.5至5微米之間。P立柱的間距與元件閘極溝槽的間距相等。與肖特基二極體整合之後,功率MOSFET元件就可以具有很低的體二極體正向電壓降(Vf),在0.35至0.45V之間。
第2圖所示的功率MOSFET200表示為一個單獨的多晶矽MOSFET元件。本發明的各個方面還使用了如第3圖所示的遮蔽柵溝槽MOSFET元件。確切地說,功率MOSFET元件300與第2圖所示的元件200類似,除了功率MOSFET元件300中的閘極溝槽310具有一個在溝槽頂部的閘極電極312a以及一個在閘極溝槽底部的遮蔽電極312b。這種遮蔽柵溝槽(SGT)結構允許很低的閘極電荷和很高的開關頻率。第3圖和第2圖所示的一致的數字符號代表一樣的部件/元件或等效元件。這些一致的部件的詳細說明在此不再贅述,以便簡便。如第3圖所示,肖特基接頭形成在肖特基接觸溝槽230b的側壁上。
第二個示例
第4圖表示依據本發明的各個方面,一部分功率MOSFET元件400的剖面圖。第4圖所示的n-型功率MOSFET元件400包括一個主動晶胞區400a和一個肖特基二極體區400b。主動晶胞區400a包括一個元件晶胞的陣列,與第2圖所示的元件晶胞類似。第4圖和第2圖所示的一致的數字符號代表一樣的部件/元件或等效元件。這些一致的部件的詳細說明在此不再贅述,以便簡便。雖然第4圖所示的主動晶胞區400a中每個元件晶胞都具有一個單獨的閘極多晶矽在閘極溝槽210中,要注意的是,元件晶胞可以選擇具有一個SGT結構,即一個在閘極溝槽頂部的閘極電極以及一個在溝槽底部的遮蔽電極。
肖特基二極體區400b可以包括n+基材202、位於基材202上方的n漂流區204、形成在漂流區204頂部附近的p-型本體區206以及一個形成在本體區206上的絕緣層216。肖特基二極體區400b還包括超級接面結構,具有交替的p摻雜立柱220和n摻雜立柱。P立柱220形成在漂流區204中的p型本體區206下方。N立柱可以由位於p立柱220附近的那部分n漂流區204構成。
肖特基接觸構成430形成在漂流區204上方的兩個相鄰的p立柱220之間。勢壘金屬(圖中沒有表示出)可以沉積在肖特基接頭430的表面上,然後在接觸溝槽中沉積鎢。肖特基接頭可以形成在漂流區204的表面上,在兩個相鄰的p立柱220之間。金屬可以沉積在整個表面上,以便為源極區和閘極電極提供合適的接頭。
第5圖表示整合在功率MOSFET元件中的另一個肖特基二極體,肖特基接頭也形成在兩個相鄰的p立柱之間的漂流區的表面上。確切地說,功率MOSFET元件500與4所示的元件400類似,除了肖特基二極體區500b中的肖特基接觸溝槽530延伸到漂流區204的頂部中。第5圖和第4圖所示的一致的數字符號
代表一樣的部件/元件或等效元件。這些一致的部件的詳細說明在此不再贅述,以便簡便。
對於該實施例來說,對於低壓元件(例如25V)來說,閘極溝槽的間距可以在1.3至1.5微米之間,對於30V的元件來說,間距在1.3至1.7微米之間,對於中壓元件(例如200V)來說,間距在3.5至5微米之間。P立柱的間距與元件閘極溝槽的間距相等。與肖特基二極體整合之後,功率MOSFET元件就可以具有很低的體二極體正向電壓降(Vf),在0.35至0.45V之間。
製備製程
第6圖表示依據本發明的各個方面,用於低壓功率MOSFET元件的製備製程的流程圖。以下的製備製程提出了用於製備一種n-型超級接面溝槽MOSFET元件的製程,其中元件晶胞的源極區和汲極區具有n型導電類型,本體區具有p型導電類型。要注意的是,這些導電類型可以反向,以便製備p型超級接面溝槽MOSFET。
製備製程從輕摻雜的n-型外延層(即漂流區)開始,在重摻雜的n-型半導體基材上方,作為初始材料。在602處,在漂流區上使用一個溝槽遮罩。在某些實施例中,溝槽遮罩可以是一個氧化層,生長或沉積在漂流區上方。溝槽遮罩含有開口,以便為MOSFET元件的溝槽電晶體限定複數個閘極溝槽的位置。對於肖特基接頭沿肖特基接觸溝槽(例如第2圖和第3圖所示的元件)形成的元件來說,溝槽遮罩含有開口,用於主動晶胞區和肖特基二極體區中的閘極溝槽。對於元件中肖特基接頭形成在兩個相鄰的p立柱之間的漂流區的表面上的元件(例如第4圖和第5圖所示的元件)來說,溝槽遮罩含有開口,僅用於主動晶胞區中的閘極溝槽,並且整個肖特基二極體區被遮罩覆蓋。在604處,進行蝕刻製程,向下蝕刻下方的漂流區的相應部分,以構成複數個閘極構成。閘極溝槽的深度約為1.0微米。閘極溝槽的寬度可以小到製程允許的最小值。作為示例,
但不作為局限,閘極溝槽的寬度在0.3至0.5微米之間。對於25V的元件來說,閘極溝槽的間距可以在1.3至1.5微米之間。還可選擇,形成閘極溝槽並且出去溝槽遮罩之後,可以生長一個犧牲氧化層(圖中沒有表示出),然後除去,以改善矽表面。
然後,在漂流區的頂面上並且沿著閘極溝槽的內表面,在606處形成一個絕緣層(例如閘極氧化物)。在608處,在閘極氧化層上方沉積一個導電材料,然後藉由回刻製程或化學-機械拋光(CMP)製程,在610處形成一個在閘極溝槽中的閘極電極。在某些實施例中,導電材料可以是原位摻雜的或未摻雜的多晶矽,這需要在後續的製備製程中進行多晶矽摻雜。
對於元件中肖特基接頭沿肖特基接觸溝槽的側壁形成的元件(例如第2圖和第3圖所示的元件)來說,在主動晶胞區中,利用漂流區上的本體遮罩,在612處進行本體注入,漂流區覆蓋了肖特基二極體區,並且留下主動晶胞區未被覆蓋。對於肖特基接頭形成在兩個相鄰的p立柱之間的漂流區表面上的元件來說,利用漂流區上的本體遮罩,在主動晶胞區中以及肖特基二極體區域上的特定區域中的612處進行本體注入,漂流區覆蓋了肖特基二極體區域中的肖特基接觸溝槽的位置,並且保留主動晶胞區未被覆蓋。利用本體遮罩注入本體摻雜物。摻雜物離子的導電類型與半導體基材的摻雜物導電類型相反。在某些實施例中,對於n-型元件來說,摻雜離子可以是硼離子。在某些實施例中,對於p-型元件來說,可以使用磷或砷離子。利用熱激活摻雜物原子,並驅使摻雜物擴散,形成本體區,在614處進行本體驅進。
在616處,進行源極注入,然後進行源極擴散製程。確切地說,利用源極注入遮罩,在漂流區上進行源極摻雜注入,漂流區覆蓋了肖特基二極體區域,保留主動晶胞區未被覆蓋。摻雜離子的導電類型與半導體基材的摻雜
離子導電類型相同。在某些實施例中,對於n-型元件,可以注入磷或砷離子。隨後進行源極擴散,在本體區中形成摻雜的源極區。
在618處,藉由選擇性注入P-型摻雜物,形成超級接面結構。這種注入可以藉由遮罩完成,以便在N-型基材中形成P-立柱。藉由沉積氧化物,例如低溫氧化物(LTO)或含有硼酸的矽玻璃(BPSG),使閘極電極與源極接頭電絕緣,如同620所示。
源極接觸溝槽和肖特基接觸溝槽形成在622處。確切地說,在介電質層上使用一個接觸遮罩,接觸遮罩所帶的圖案在元件晶胞區中的源極接觸溝槽和肖特基二極體區中肖特基接觸溝槽的位置上具有開口。利用蝕刻製程,除去介電質層未被覆蓋的那部分,形成源極接觸溝槽,穿過源極區到本體區內,以及肖特基二極體區中所需的肖特基接觸溝槽。肖特基接觸溝槽比源極接觸溝槽更寬。作為示例,但不作為局限,主動元件晶胞區中的源極接觸溝槽的寬度約為0.4微米,肖特基接觸溝槽的寬度約為0.5至0.7微米,取決於檯面結構的寬度。
對於肖特基接頭沿肖特基接觸溝槽的側壁形成的元件(例如第2圖和第3圖所示的元件)來說,在624處進行p-型接觸注入,在每個肖特基接觸溝槽和每個源極接觸溝槽下方形成一個接觸注入區。接觸注入區可以藉由肖特基接觸開口的帶角度的注入形成。作為示例,但不作為局限,注入是在20至40KeV的能級下,使用1×1012-4×1012/cm2的劑量。根據所需的肖特基接頭寬度,選擇合適的角度。要注意的是,每個接觸注入區都至少是肖特基接觸溝槽的寬度。在某些實施例中,角度約為10至15°之間。我們希望,對於第2圖和第3圖所示的元件來說,肖特基接觸溝槽230b比接觸注入物232下方的p立柱220的寬度更寬。對於肖特基接頭形成在兩個相鄰的p立柱之間的漂流區的表面上的元件(例如第4圖和第5圖所示的元件)來說,可以在624處進行輕p-型香農注入,以便在每個肖
特基接觸溝槽下方形成一個接觸注入區。作為示例,但不作為局限,香農注入是在20至40KeV的能級下,使用1×1012-4×1012/cm2的劑量。
要注意的是,勢壘高度取決於接觸注入製程。肖特基勢壘高度與肖特基二極體的汲極至源極漏電流Idss有關。隨著勢壘高度的增加,漏電流降低,並且正向電壓降增大。626表示退火製程,進行退火製程,激活注入物。
然後在628處,沉積一個薄勢壘金屬層(例如鈦(Ti)或氮化鈦(TiN)),在源極接觸溝槽和肖特基接觸溝槽的側壁和底部。藉由快速的加熱製程,加熱勢壘金屬。在630處,在剩餘的溝槽內沉積鎢,然後在632處,進行回刻製程。勢壘金屬作為鎢插頭和半導體材料之間的擴散勢壘,溝槽就形成在半導體材料中。金屬層(例如鋁)可以沉積在BPSG層以及鎢插頭上方,在634處。進行金屬蝕刻之後,在636處形成標準的蝕刻鋁合金互聯。
中壓或高壓功率MOSFET元件的製備製程與第6圖所示的製備製程類似,除了超級接面結構在製程開始階段形成之外。超級接面結構可以利用多層序列的外延和注入,在外延的n-型漂流區中形成p立柱。在每個連續的外延層中,藉由注入遮罩,注入離子。重複使用相同的遮罩,注入每個外延層,產生p立柱。
儘管本發明關於某些較佳的版本已經做了詳細的敘述,但是仍可能存在各種不同的修正、變化和等效情況。因此,本發明的範圍不應由上述說明決定,與之相反,本發明的範圍應參照所附的申請專利範圍及其全部等效內容。任何可選件(無論首選與否),都可與其他任何可選件(無論首選與否)組合。在以下申請專利範圍中,除非特別聲明,否則不定冠詞“一個”或“一種”都指下文內容中的一個或多個項目的數量。除非用“意思是”明確指出限定功能,否則所附的申請專利範圍並不應認為是意義-加-功能的局限。沒有明確
指出“意思是”執行特定功能的申請專利範圍中的任意內容,都不應認為是35USC § 112(f)中所述的“意思”或“步驟”。
110:主動晶胞區
120:肖特基二極體區
130:閘極墊
132:閘極滑道
Claims (18)
- 一種金屬-氧化物-半導體場效應電晶體(MOSFET)元件,其包括:一個主動晶胞區,包括多個超級接面溝槽MOSFET,其中主動晶胞區包括:一個第一導電類型的輕摻雜漂流區,位於相同導電類型的重摻雜基材上方;一個第二導電類型的本體區,位於漂流區上方,第二導電類型與第一導電類型相反;複數個閘極溝槽,位於本體區中,並延伸到漂流區內,其中複數個閘極溝槽中的每個閘極溝槽都內襯介電質材料,閘極溝槽包括一個閘極電極;一個第一導電類型的重摻雜源極區,位於本體區中;一個源極接頭,位於源極接觸溝槽中,延伸到兩個相鄰的閘極溝槽之間的本體區;以及一個超級接面結構,位於漂流區中,包括交替的第一導電類型的第一摻雜立柱以及平行排布的第二導電類型的第二摻雜立柱,其中第二摻雜立柱位於每個源極接觸溝槽的底部附近;以及一個肖特基二極體區,包括多個肖特基二極體形成在具有超級接面結構的漂流區中,每個肖特基二極體都包括一個肖特基接頭,在輕摻雜的半導體層和金屬層之間;其中,肖特基接頭沿肖特基接觸溝槽的一部分垂直側壁形成;其中,肖特基接觸溝槽比複數個源極接觸溝槽中的每個源極接 觸溝槽都寬。
- 如申請專利範圍第1項所述的元件,其中,肖特基接觸溝槽的寬度約為0.5至0.7微米。
- 如申請專利範圍第1項或第2項所述的元件,其中,肖特基接觸溝槽和相鄰的閘極溝槽之間的縫隙小於0.2微米。
- 如申請專利範圍的1項所述的元件,其中,元件的工作電壓在8V至40V之間,複數個個閘極溝槽的每個閘極溝槽的間距在1.3至1.7微米之間。
- 如申請專利範圍第1項所述的元件,其中,元件的工作電壓為30V,多個閘極溝槽的每個閘極溝槽的間距在1.3至1.7微米之間。
- 如申請專利範圍第1項所述的元件,其中,元件的工作電壓高於100V,複數個閘極溝槽的每個閘極溝槽的間距在3.5至5微米之間。
- 如申請專利範圍第1項所述的元件,其中,複數個閘極溝槽的每個閘極溝槽都包括一個在頂部的閘極電極以及一個在底部的遮蔽電極。
- 如申請專利範圍第1項所述的元件,其中,形成肖特基接頭的表面是凹陷的。
- 一種溝槽金屬-氧化物-半導體場效應電晶體(MOSFET)元件的製備方法,其包括:製備一個主動晶胞區,包括複數個超級接面溝槽功率MOSFET,其中製備主動晶胞區包括: 製備一個第一導電類型的漂流區,位於相同導電類型的重摻雜基材上方;製備一個第二導電類型的本體區,位於漂流區上方,第二導電類型與第一導電類型相反;製備複數個閘極溝槽,位於本體區中,並延伸到漂流區內,其中內襯介電質材料的多個閘極溝槽的每個閘極溝槽都含有一個閘極電極;製備一個第一導電類型的重摻雜源極區,位於本體區中;製備一個源極接頭,在源極接觸溝槽中,延伸到兩個相鄰的閘極溝槽之間的本體區;並且製備一個超級接面結構,位於漂流區中,包括交替的第一導電類型的第一摻雜立柱以及平行排布的第二導電類型的第二摻雜立柱,其中第二摻雜立柱的每個立柱都位於每個源極接觸溝槽的底部附近;並且製備複數個肖特基二極體,在肖特基二極體區中具有超級接面結構的漂流區中,每個肖特基二極體都包括一個肖特基接頭,在輕摻雜半導體層和金屬層之間;其中,製備一個本體區包括使用一個本體遮罩,覆蓋著肖特基二極體區的整個部分,留下主動晶胞區不覆蓋。
- 如申請專利範圍第9項所述的方法,其中,肖特基接頭沿肖特基接觸溝槽的一部分垂直側壁形成。
- 如申請專利範圍第9項所述的方法,其中,肖特基接頭形成在相鄰的第二摻雜立柱之間的輕摻雜漂流區的表面上。
- 如申請專利範圍第10項所述的方法,其中,肖特基接觸溝槽比複數個源極接觸溝槽的每個源極接觸溝槽都寬。
- 如申請專利範圍第10項或第12項所述的方法,其中,肖特基接觸溝槽和相鄰的閘極溝槽之間的縫隙小於0.2微米。
- 如申請專利範圍第10項所述的方法,其中,製備複數個閘極溝槽包括在漂流區上使用一個閘極溝槽遮罩,不覆蓋主動晶胞區中的閘極溝槽開口以及肖特基二極體區中的閘極溝槽開口的位置。
- 如申請專利範圍第11項所述的方法,其中,製備複數個閘極溝槽包括在漂流區上使用一個閘極溝槽遮罩,不覆蓋主動晶胞區中的閘極溝槽開口的位置,覆蓋肖特基二極體區的整個部分。
- 如申請專利範圍第10項所述的方法,其中,製備一個源極區包括使用一個本體遮罩,覆蓋著肖特基二極體區的整個部分,留下主動晶胞區不覆蓋。
- 如申請專利範圍第10項所述的方法,其中,製備多個肖特基二極體包括在每個肖特基接觸溝槽下方,製備一個接觸注入區,其中藉由肖特基接觸溝槽開口,利用帶角度的注入,製備接觸注入區。
- 如申請專利範圍第11項所述的方法,其中,製備多個肖特基二極體包括在每個肖特基接觸溝槽下方,製備一個接觸注入區,其中藉由肖特基接觸溝槽開口,利用香農注入,製備接觸注入區。
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IT201900006709A1 (it) * | 2019-05-10 | 2020-11-10 | St Microelectronics Srl | Dispositivo mosfet di potenza a super giunzione con affidabilita' migliorata, e metodo di fabbricazione |
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US20220069073A1 (en) * | 2020-08-28 | 2022-03-03 | Nanjing Zizhu Microelectronics Co., Ltd. | Integrated circuit system with super junction transistor mechanism and method of manufacture thereof |
CN112201690A (zh) * | 2020-09-24 | 2021-01-08 | 芜湖启源微电子科技合伙企业(有限合伙) | Mosfet晶体管 |
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