KR102283496B1 - 다수의 주입층들을 갖는 고-전압 전계-효과 트랜지스터 - Google Patents
다수의 주입층들을 갖는 고-전압 전계-효과 트랜지스터 Download PDFInfo
- Publication number
- KR102283496B1 KR102283496B1 KR1020167000416A KR20167000416A KR102283496B1 KR 102283496 B1 KR102283496 B1 KR 102283496B1 KR 1020167000416 A KR1020167000416 A KR 1020167000416A KR 20167000416 A KR20167000416 A KR 20167000416A KR 102283496 B1 KR102283496 B1 KR 102283496B1
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- South Korea
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- oxide layer
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- layers
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
-
- H01L29/66681—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H01L29/0615—
-
- H01L29/105—
-
- H01L29/7816—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
-
- H10P30/204—
-
- H10P30/212—
-
- H10P30/222—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/051—Forming charge compensation regions, e.g. superjunctions
- H10D62/054—Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
Landscapes
- Physics & Mathematics (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Toxicology (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Composite Materials (AREA)
- Crystallography & Structural Chemistry (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/941,119 | 2013-07-12 | ||
| US13/941,119 US9660053B2 (en) | 2013-07-12 | 2013-07-12 | High-voltage field-effect transistor having multiple implanted layers |
| PCT/US2014/044769 WO2015006074A1 (en) | 2013-07-12 | 2014-06-28 | High-voltage field-effect transistor having multiple implanted layers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20160030171A KR20160030171A (ko) | 2016-03-16 |
| KR102283496B1 true KR102283496B1 (ko) | 2021-07-29 |
Family
ID=52276454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020167000416A Active KR102283496B1 (ko) | 2013-07-12 | 2014-06-28 | 다수의 주입층들을 갖는 고-전압 전계-효과 트랜지스터 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9660053B2 (enExample) |
| JP (1) | JP6490679B2 (enExample) |
| KR (1) | KR102283496B1 (enExample) |
| CN (1) | CN105378934B (enExample) |
| DE (1) | DE112014003246B4 (enExample) |
| WO (1) | WO2015006074A1 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11355580B2 (en) * | 2019-10-18 | 2022-06-07 | Semiconductor Components Industries, Llc | Lateral DMOS device with step-profiled RESURF and drift structures |
| CN113130632B (zh) | 2019-12-31 | 2022-08-12 | 无锡华润上华科技有限公司 | 横向扩散金属氧化物半导体器件及其制备方法 |
Family Cites Families (73)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5638867A (en) | 1979-09-07 | 1981-04-14 | Hitachi Ltd | Insulated gate type field effect transistor |
| JPS5712558A (en) | 1980-06-25 | 1982-01-22 | Sanyo Electric Co Ltd | Mos transistor having high withstand voltage |
| JPS5712557A (en) | 1980-06-25 | 1982-01-22 | Sanyo Electric Co Ltd | High dielectric resisting mos transistor |
| GB2089119A (en) | 1980-12-10 | 1982-06-16 | Philips Electronic Associated | High voltage semiconductor devices |
| US4462041A (en) | 1981-03-20 | 1984-07-24 | Harris Corporation | High speed and current gain insulated gate field effect transistors |
| US4454648A (en) * | 1982-03-08 | 1984-06-19 | Mcdonnell Douglas Corporation | Method of making integrated MNOS and CMOS devices in a bulk silicon wafer |
| US4626879A (en) | 1982-12-21 | 1986-12-02 | North American Philips Corporation | Lateral double-diffused MOS transistor devices suitable for source-follower applications |
| US4503601A (en) * | 1983-04-18 | 1985-03-12 | Ncr Corporation | Oxide trench structure for polysilicon gates and interconnects |
| JPS6064771A (ja) | 1983-09-19 | 1985-04-13 | Daihen Corp | 溶接機制御装置 |
| DE3404834A1 (de) | 1984-02-08 | 1985-08-08 | Hahn-Meitner-Institut für Kernforschung Berlin GmbH, 1000 Berlin | Halbleiter-leistungsbauelement, insbesondere thyristor und gridistor, sowie verfahren zu dessen herstellung |
| US4618541A (en) | 1984-12-21 | 1986-10-21 | Advanced Micro Devices, Inc. | Method of forming a silicon nitride film transparent to ultraviolet radiation and resulting article |
| US4665426A (en) | 1985-02-01 | 1987-05-12 | Advanced Micro Devices, Inc. | EPROM with ultraviolet radiation transparent silicon nitride passivation layer |
| US4764800A (en) | 1986-05-07 | 1988-08-16 | Advanced Micro Devices, Inc. | Seal structure for an integrated circuit |
| US4894694A (en) | 1986-10-31 | 1990-01-16 | Hewlett-Packard Company | MOSFET structure and method for making same |
| US5010024A (en) | 1987-03-04 | 1991-04-23 | Advanced Micro Devices, Inc. | Passivation for integrated circuit structures |
| US4811075A (en) | 1987-04-24 | 1989-03-07 | Power Integrations, Inc. | High voltage MOS transistors |
| US4890146A (en) | 1987-12-16 | 1989-12-26 | Siliconix Incorporated | High voltage level shift semiconductor device |
| US4922327A (en) | 1987-12-24 | 1990-05-01 | University Of Toronto Innovations Foundation | Semiconductor LDMOS device with upper and lower passages |
| US5025296A (en) | 1988-02-29 | 1991-06-18 | Motorola, Inc. | Center tapped FET |
| US5237193A (en) | 1988-06-24 | 1993-08-17 | Siliconix Incorporated | Lightly doped drain MOSFET with reduced on-resistance |
| DE68926384T2 (de) | 1988-11-29 | 1996-10-10 | Toshiba Kawasaki Kk | Lateraler Leitfähigkeitsmodulations-MOSFET |
| US4950977A (en) * | 1988-12-21 | 1990-08-21 | At&T Bell Laboratories | Method of measuring mobile ion concentration in semiconductor devices |
| JPH02214114A (ja) * | 1989-02-15 | 1990-08-27 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
| US5270226A (en) * | 1989-04-03 | 1993-12-14 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method for LDDFETS using oblique ion implantion technique |
| JPH038323A (ja) * | 1989-06-06 | 1991-01-16 | Nec Corp | イオン注入方法およびイオン注入装置 |
| JP2597412B2 (ja) | 1990-03-20 | 1997-04-09 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| US5040045A (en) | 1990-05-17 | 1991-08-13 | U.S. Philips Corporation | High voltage MOS transistor having shielded crossover path for a high voltage connection bus |
| JP2991753B2 (ja) | 1990-08-27 | 1999-12-20 | 松下電子工業株式会社 | 半導体装置及びその製造方法 |
| JP2599493B2 (ja) | 1990-08-27 | 1997-04-09 | 松下電子工業株式会社 | 半導体装置 |
| JP2609753B2 (ja) * | 1990-10-17 | 1997-05-14 | 株式会社東芝 | 半導体装置 |
| US5386136A (en) | 1991-05-06 | 1995-01-31 | Siliconix Incorporated | Lightly-doped drain MOSFET with improved breakdown characteristics |
| US5146298A (en) | 1991-08-16 | 1992-09-08 | Eklund Klas H | Device which functions as a lateral double-diffused insulated gate field effect transistor or as a bipolar transistor |
| US5258636A (en) | 1991-12-12 | 1993-11-02 | Power Integrations, Inc. | Narrow radius tips for high voltage semiconductor devices with interdigitated source and drain electrodes |
| US5270264A (en) | 1991-12-20 | 1993-12-14 | Intel Corporation | Process for filling submicron spaces with dielectric |
| JP3435173B2 (ja) | 1992-07-10 | 2003-08-11 | 株式会社日立製作所 | 半導体装置 |
| JP3076468B2 (ja) | 1993-01-26 | 2000-08-14 | 松下電子工業株式会社 | 半導体装置 |
| US5313082A (en) | 1993-02-16 | 1994-05-17 | Power Integrations, Inc. | High voltage MOS transistor with a low on-resistance |
| DE4309764C2 (de) | 1993-03-25 | 1997-01-30 | Siemens Ag | Leistungs-MOSFET |
| US5349225A (en) | 1993-04-12 | 1994-09-20 | Texas Instruments Incorporated | Field effect transistor with a lightly doped drain |
| US5324683A (en) | 1993-06-02 | 1994-06-28 | Motorola, Inc. | Method of forming a semiconductor structure having an air region |
| JP3218267B2 (ja) | 1994-04-11 | 2001-10-15 | 新電元工業株式会社 | 半導体装置 |
| US5523604A (en) | 1994-05-13 | 1996-06-04 | International Rectifier Corporation | Amorphous silicon layer for top surface of semiconductor device |
| CN1040814C (zh) | 1994-07-20 | 1998-11-18 | 电子科技大学 | 一种用于半导体器件的表面耐压区 |
| US5494853A (en) | 1994-07-25 | 1996-02-27 | United Microelectronics Corporation | Method to solve holes in passivation by metal layout |
| US5521105A (en) | 1994-08-12 | 1996-05-28 | United Microelectronics Corporation | Method of forming counter-doped island in power MOSFET |
| US5550405A (en) | 1994-12-21 | 1996-08-27 | Advanced Micro Devices, Incorporated | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS |
| US5656543A (en) | 1995-02-03 | 1997-08-12 | National Semiconductor Corporation | Fabrication of integrated circuits with borderless vias |
| US5670828A (en) | 1995-02-21 | 1997-09-23 | Advanced Micro Devices, Inc. | Tunneling technology for reducing intra-conductive layer capacitance |
| US5659201A (en) | 1995-06-05 | 1997-08-19 | Advanced Micro Devices, Inc. | High conductivity interconnection line |
| KR100188096B1 (ko) | 1995-09-14 | 1999-06-01 | 김광호 | 반도체 장치 및 그 제조 방법 |
| EP1039548B1 (de) | 1996-02-05 | 2004-03-31 | Infineon Technologies AG | Durch Feldeffekt steuerbares Halbleiterbauelement |
| US6207994B1 (en) * | 1996-11-05 | 2001-03-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
| WO1998020562A1 (en) | 1996-11-05 | 1998-05-14 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region and method of making the same |
| US6168983B1 (en) * | 1996-11-05 | 2001-01-02 | Power Integrations, Inc. | Method of making a high-voltage transistor with multiple lateral conduction layers |
| KR100228331B1 (ko) | 1996-12-30 | 1999-11-01 | 김영환 | 반도체 소자의 삼중웰 제조 방법 |
| JP3393544B2 (ja) | 1997-02-26 | 2003-04-07 | シャープ株式会社 | 半導体装置の製造方法 |
| US5843817A (en) * | 1997-09-19 | 1998-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for integrating stacked capacitor DRAM devices with MOSFET devices used for high performance logic circuits |
| JP3059423B2 (ja) * | 1998-10-19 | 2000-07-04 | 松下電子工業株式会社 | 半導体装置の製造方法 |
| US6174758B1 (en) * | 1999-03-03 | 2001-01-16 | Tower Semiconductor Ltd. | Semiconductor chip having fieldless array with salicide gates and methods for making same |
| US6429077B1 (en) * | 1999-12-02 | 2002-08-06 | United Microelectronics Corp. | Method of forming a lateral diffused metal-oxide semiconductor transistor |
| US6509220B2 (en) * | 2000-11-27 | 2003-01-21 | Power Integrations, Inc. | Method of fabricating a high-voltage transistor |
| US6424007B1 (en) | 2001-01-24 | 2002-07-23 | Power Integrations, Inc. | High-voltage transistor with buried conduction layer |
| US6448625B1 (en) * | 2001-03-16 | 2002-09-10 | Semiconductor Components Industries Llc | High voltage metal oxide device with enhanced well region |
| US6489224B1 (en) * | 2001-05-31 | 2002-12-03 | Sun Microsystems, Inc. | Method for engineering the threshold voltage of a device using buried wells |
| US6773997B2 (en) * | 2001-07-31 | 2004-08-10 | Semiconductor Components Industries, L.L.C. | Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability |
| JP3546037B2 (ja) * | 2001-12-03 | 2004-07-21 | 松下電器産業株式会社 | 半導体装置の製造方法 |
| US7011998B1 (en) | 2004-01-12 | 2006-03-14 | Advanced Micro Devices, Inc. | High voltage transistor scaling tilt ion implant method |
| KR100539247B1 (ko) * | 2004-02-04 | 2005-12-27 | 삼성전자주식회사 | 스플릿 게이트형 비휘발성 반도체 메모리 소자 및 그제조방법 |
| EP1742250A1 (en) | 2005-07-08 | 2007-01-10 | STMicroelectronics S.r.l. | Power field effect transistor and manufacturing method thereof |
| JP2009515332A (ja) | 2005-11-02 | 2009-04-09 | エヌエックスピー ビー ヴィ | 半導体デバイスの製造方法 |
| KR20100064556A (ko) | 2008-12-05 | 2010-06-15 | 주식회사 동부하이텍 | 반도체 소자 및 그 제조 방법 |
| US8362557B2 (en) * | 2009-12-02 | 2013-01-29 | Fairchild Semiconductor Corporation | Stepped-source LDMOS architecture |
| US8349678B2 (en) * | 2010-02-08 | 2013-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Laterally diffused metal oxide semiconductor transistor with partially unsilicided source/drain |
-
2013
- 2013-07-12 US US13/941,119 patent/US9660053B2/en active Active
-
2014
- 2014-06-28 WO PCT/US2014/044769 patent/WO2015006074A1/en not_active Ceased
- 2014-06-28 DE DE112014003246.8T patent/DE112014003246B4/de active Active
- 2014-06-28 CN CN201480039829.0A patent/CN105378934B/zh active Active
- 2014-06-28 KR KR1020167000416A patent/KR102283496B1/ko active Active
- 2014-06-28 JP JP2016525370A patent/JP6490679B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20150014770A1 (en) | 2015-01-15 |
| US9660053B2 (en) | 2017-05-23 |
| JP6490679B2 (ja) | 2019-03-27 |
| WO2015006074A1 (en) | 2015-01-15 |
| KR20160030171A (ko) | 2016-03-16 |
| CN105378934B (zh) | 2018-12-11 |
| DE112014003246T5 (de) | 2016-04-07 |
| JP2016526804A (ja) | 2016-09-05 |
| CN105378934A (zh) | 2016-03-02 |
| DE112014003246B4 (de) | 2025-04-03 |
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