CN102148162A - 横向扩散金属氧化物半导体晶体管及其制造方法 - Google Patents

横向扩散金属氧化物半导体晶体管及其制造方法 Download PDF

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CN102148162A
CN102148162A CN2011100375761A CN201110037576A CN102148162A CN 102148162 A CN102148162 A CN 102148162A CN 2011100375761 A CN2011100375761 A CN 2011100375761A CN 201110037576 A CN201110037576 A CN 201110037576A CN 102148162 A CN102148162 A CN 102148162A
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silicide
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CN102148162B (zh
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庄学理
张立伟
朱鸣
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种横向扩散金属氧化物半导体晶体管及其制造方法，该制造方法包含：形成虚置栅极于基材上；形成源极及漏极于基材上的虚置栅极两侧；形成第一硅化物于源极上；形成第二硅化物于漏极上，以使源极或漏极至少其一的未硅化区与虚置栅极相邻，漏极的未硅化区提供一阻抗区，能足以负载高电压横向扩散金属氧化物半导体导体应用所需的电压；对虚置栅极进行栅极替换工艺以形成栅极。本发明实施例所提供的制造方法，因为其无需在栅极区域形成硅化物，因而具有较佳的工艺控制。

Description

横向扩散金属氧化物半导体晶体管及其制造方法
技术领域
本发明涉及集成电路装置，尤其涉及一种横向扩散金属氧化物半导体(LDMOS)晶体管。
背景技术
目前，横向扩散金属氧化物半导体晶体管已广泛应用于射频(RF)/微波领域。例如，应用于功率放大器时，需要高输出功率。因此，需要能足以承受高电压及增大电流的横向扩散金属氧化物半导体晶体管。使用多晶硅/氮氧化硅栅极堆叠的横向扩散金属氧化物半导体晶体管，在栅极上形成硅化物时具有控制不易的问题，造成在硅化工艺中形成部分硅化的栅极。因此，业界亟需一种新颖的横向扩散金属氧化物半导体晶体管及其制造方法。
发明内容
为了克服现有技术中存在的缺陷，本发明提供一种横向扩散金属氧化物半导体(LDMOS)晶体管的制造方法，包括：形成一虚置栅极于一基材上；形成一源极及一漏极于此基材上的此虚置栅极两侧；形成一第一硅化物于此源极上及一第二硅化物于此漏极上，且于此源极或此漏极至少其一留下与此虚置栅极相邻的一未硅化区，以提供能足以负载应用于高电压横向金属氧化物半导体导体所需的电压的阻抗区(resistive region)；以及对此虚置栅极进行一替换栅极工艺，以形成栅极。
本发明还提供一种横向扩散金属氧化物半导体(LDMOS)晶体管，包括：一基材；一栅极，位于此基材上；一源极及一漏极，位于此栅极两侧；一第一硅化物，位于此源极上；以及一第二硅化物，位于此漏极上，其中此源极或此漏极至少其一具有与此栅极相邻的一未硅化区，以提供能足以负载应用于高电压横向扩散金属氧化物半导体导体所需的电压的阻抗区(resistive region)。
本发明实施例所提供的横向扩散金属氧化物半导体(LDMOS)晶体管及其制造方法，具有较佳的工艺控制，因为其无需在栅极区域形成硅化物。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合所附图，作详细说明如下：
附图说明
图1所示为依照本发明一或多个实施例的横向扩散金属氧化物半导体晶体管。
图2至图7所示为依照本发明一或多个实施例的横向扩散金属氧化物半导体晶体管的制造方法的各种中间阶段。
【主要附图标记说明】
100～横向扩散金属氧化物半导体晶体管
102～基材              104～源极
106～第一硅化物        108～漏极
110～第二硅化物        111～金属栅极
112～沟槽填充金属材料  114～功函数金属
116～栅极介电层        118～间隔物
120～未硅化区          202～虚置栅极
204～硬掩模            302～阻抗保护氧化层
402～图案化的阻抗保护氧化层
602～介电层            604～沟槽
具体实施方式
本发明接下来将会提供许多不同的实施例以说明本发明中不同的特征。各特定实施例中的构成及配置将会在以下作详细说明以阐述本发明的精神，但这些实施例并非用于限定本发明。
本发明在此提供一种横向扩散金属氧化物半导体(LDMOS)晶体管的结构。图1所示为依照本发明一或多个实施例的横向扩散金属氧化物半导体晶体管。横向扩散金属氧化物半导体晶体管100包含基材102、位于基材102上的金属栅极111、及位于基材102上的金属栅极111两侧的源极104及漏极108。基材102可包含块状硅或绝缘层上覆硅。或者，基材102包含其他可以或不可以与硅结合的材料，例如锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、锑化镓或其他任意合适材料。栅极介电层116设置于基材102上的金属栅极111与晶体管100沟道222之间。间隔物118也同样设置于金属栅极111两侧。
第一硅化物106设置于源极104上。第二硅化物110设置于漏极108上。硅化物为硅与金属的合金，作为制造硅装置时的接触材料，例如TiSi2、CoSi2、NiSi、其他硅化物或前述的组合。硅化物结合了金属接触点(例如远低于多晶硅的阻抗)及多晶硅接触点(例如无电迁移性)的优点。漏极108具有与金属栅极111相邻的未硅化区120，以提供一阻抗区，能足以负载高电压横向扩散金属氧化物半导体导体应用所需的电压。
例如，横向扩散金属氧化物半导体导体广泛地用于作为基地台的功率扩大器，其需有高输出功率，因而所对应的漏极至源极击穿电压常超过60V。许多高功率射频应用使用约20至50V的直流(DC)供应电压。
在一实施例中，可定义未硅化120于间隔物118与硅化物110之间。在某些实施例中，未硅化区120的长度为约0.05μm 至1μm。栅极介电层116包含高介电常数栅极介电材料，包含氧化铪、硅氧化铪、氧化镧、氧化锆、硅氧化锆、氧化钽、氧化钛、钛酸钡锶(barium strontium titanium oxide)、钛酸钡(barium titanium oxide)、钛酸锶锶(barium titanium oxide)、氧化钇(yttrium oxide)、钽酸铅钪(lead scandium tantalum oxide)、铌酸铅锌(lead zinc niobate)或其他任意合适材料，这些材料可用于形成高介电常数栅极介电质。金属栅极111可包含多个金属层，例如功函数金属层114及沟槽填充金属材料112。沟槽填充金属材料112可包含钨、铝、钛、氮化钛或其他任意合适材料。
表1
  LDMOS   Poly/SiON   HK/MG
  Vtlin(V)   0.256   0.257
  Vtsat(V)   0.251   0.251
  Idlin(μA/μm)   19.6   20.1
  Ion(μA/μm)   402.5   419.9
  DIBL(mV)   5.4   5.3
表1显示为使用多晶硅/氮氧化硅(poly/SiON)栅极堆叠的横向扩散金属氧化物半导体晶体管(LDMOS)与依照本发明一或多个实施例的使用高介电常数介电质/金属(HK/MG)栅极堆叠的横向扩散金属氧化物半导体晶体管(LDMOS)的效能比较，其中上述两种横向扩散金属氧化物半导体晶体管皆具有相同的等效氧化层厚度(EOT)
Figure BSA00000433903100041
及栅极长度1μm。由于使用高介电常数介电质/金属栅极堆叠(HK/MG)的横向扩散金属氧化物半导体晶体管去除了多晶硅栅极耗尽效应(poly depletion effect)，具有较高的导通电流Ion，其较使用多晶硅/氮氧化硅(poly/SiON)栅极堆叠的横向扩散金属氧化物半导体晶体管的导通电流Ion增加约4％。使用高介电常数介电质/金属栅极堆叠(HK/MG)的横向扩散金属氧化物半导体晶体管的线性区电流Id lin也有所增加。此外，两种横向扩散金属氧化物半导体晶体管具有近似的线性区临界电压Vt lin及饱和区临界电压Vt sat，且漏极导致势垒降低(DIBL)的数值也皆近似。
关于导通电阻(on-state resistance)分布，在使用高介电常数介电质/金属(HK/MG)栅极堆叠的横向扩散金属氧化物半导体晶体管的实施例中，源极电阻为107ohm-cm，其为晶体管总导通电阻的约4.3％。沟道电阻为1460.2ohm-cm，其为晶体管总导通电阻的约58.7％。漏极电阻为920.4ohm-cm，其为晶体管总导通电阻的约37％。这些值均近似于使用多晶硅(poly)/氮氧化硅(SiON)栅极堆叠的横向扩散金属氧化物半导体晶体管的导通电阻分布。
图2-图7所示为依照本发明一或多个实施例的横向扩散金属氧化物半导体晶体管的制造方法的各种中间阶段。图2显示为虚置栅极202形成于基材102上。在一实施例中，虚置栅极202可包含例如多晶硅。硬掩模202形成于虚置栅极202上。硬掩模204及虚置栅极202可由光学光刻工艺和/或蚀刻工艺来作图案化。在一实施例中，多晶硅虚置栅极202的厚度为约100至
Figure BSA00000433903100051
硬掩模204可包含氮化硅、二氧化硅和/或氮氧化硅，且其厚度为约100至
Figure BSA00000433903100052
间隔物118形成于虚置栅极202两侧。间隔物118可包含例如氮化硅。在间隔物118形成后，形成源极104及漏极108于基材102上的虚置栅极202两侧。源极104及漏极108可由将离子注入进入基材102中形成，并接着对其进行适当的退火工艺。在进行离子注入及退火步骤后，部分的源极104及漏极108可转换成如下所述的硅化物。
在图3中，阻抗保护氧化层302形成于硬掩模204、虚置栅极202、间隔物118、源极104及漏极108上。在阻抗保护氧化层302覆盖及基材102表面上所有定义的元件区后，元件区可被区分为将用于电性接触的硅化区及不欲被硅化的另一区域。在一实施例中，使用二氧化硅来形成阻抗保护氧化层302。
在图4中，将阻抗保护氧化层302(如图3所示)部分蚀刻，留下阻抗保护氧化层302在至少一部分的虚置栅极202上，并延伸至漏极108。元件区受阻抗保护氧化层402覆盖的区域将不被硅化。可由进行例如氧化物湿式蚀刻，对阻抗保护氧化层302作部分蚀刻，以定义阻抗保护氧化层402。阻抗保护氧化层402保护其底下的区域不被硅化，硬掩模204也保护虚置栅极202不被硅化。
在图5中，进行硅化工艺以形成第一硅化物106及第二硅化物110。第一硅化物106形成在源极104上。第二硅化物110形成在漏极108上，且在漏极108留下与虚置栅极202相邻的未硅化区120。漏极108的未硅化区120提供一阻抗区，能足以负载高电压横向扩散金属氧化物半导体导体应用所需的电压。在一实施例中，未硅化区120的长度为约0.05μm至1μm。
在图6至图中，对虚置栅极202(如图5所示)进行栅极替换工艺。在图6中，在形成硅化区106及110于源极104及漏极108上之后，可移除阻抗保护氧化层402(如图5所示)并沉积介电层602于元件区上。介电层602可包含二氧化硅、低介电常数材料或其他任意材料。介电层602可掺杂磷、硼或其他元素，且可使用高密度等离子体沉积工艺形成。
图6显示在进行栅极替换工艺后，对介电层602进行研磨。可以化学机械研磨(CMP)操作来移除部分的介电层602。在暴露出硬掩模204(如图5所示)后，移除部分的硬掩模204以暴露出虚置栅极202。在某些实施例中，当研磨介电层602时，自虚置栅极202的表面研磨硬掩模204。被间隔物118所括住(bracketed)的虚置栅极202(如图5所示)被移除，以在间隔物118之间形成沟槽604。虚置栅极202可由选择性湿式蚀刻工艺移除。
在图7中，在移除虚置栅极116后，形成栅极介电层116于位于沟槽604底部的基材102上。沟槽604由栅极介电层116及其上的金属栅极111所填满。栅极介电层116可包含任何可作为金属栅极晶体管的栅极介电层的材料，特别是高介电常数介电材料。
可使用沉积方式形成栅极介电层116于基材102上，例如化学气相沉积(CVD)、低压化学气相沉积(low pressure CVD)或物理气相沉积(PVD)工艺。在许多实施例中，高介电常数介电层的厚度可小于
Figure BSA00000433903100061
在某些实施例中，为了移除栅极介电层116中的杂质及增加介电层的含氧量，可对栅极介电层116进行湿式化学处理。
在某些实施例中，金属栅极111可包含多个金属层。例如，可沉积功函数金属层114于栅极介电层116上，及可沉积沟槽填充金属层112于功函数金属层114上。用于NMOS晶体管的功函数金属层114可包含铪、锆、钛、钽、铝或前述的合金，例如含前述元素的金属碳化物，也即碳化铪、碳化锆、碳化钛、碳化钽、碳化铝或其他任意合适材料。可使用化学气相沉积(CVD)或物理气相沉积(PVD)工艺(例如溅镀和/或原子层沉积工艺)来形成功函数金属层114于栅极介电层116上。
在某些实施例中，用于NMOS晶体管的功函数金属层114的功函数在约3.9eV 4.2eV之间。如未沉积沟槽金属材料112，功函数金属层114可填满(fill up)沟槽。如此，功函数金属层114的厚度为约100至
Figure BSA00000433903100062
Figure BSA00000433903100063
如沉积沟槽金属112于功函数金属层114上以填充沟槽604，沟槽填充金属层112可包含容易研磨的材料，例如钨、铝、钛、氮化钛和/或其他任意材料。如此，功函数金属层的厚度为约50至
Figure BSA00000433903100071
用于PMOS晶体管的功函数金属层114可包含钌、钯、铂、钴、镍、导电金属氧化物，例如氧化钌或其他任意合适材料。在某些实施例中，用于PMOS晶体管的功函数金属层114的功函数约在4.9eV至5.2eV之间。
在对应于图1-图7所示的特定实施例中，位于间隔物118外的漏极108有部分未被硅化。然而，在某些其他实施例中，位于间隔物118外的源极104有部分未被硅化，且位于间隔物118外的漏极108被完全硅化。在另外的实施例中，位于间隔物118外的源极104漏极及108皆有部分未硅化。上述源极104和/或漏极108的未硅化区提供了一或多个高阻抗区，能同样达到足以负载高电压横向扩散金属氧化物半导体导体应用所需的电压。
相较于公知多晶硅/氮氧化硅栅极堆叠，上述实施例所提供的制造方法具有较佳的工艺控制，因为其无需在栅极区域形成硅化物。并且，高介电常数介电层/金属栅极堆叠可使结构的工艺变异(process variations)较少。为了减少工艺的成本及复杂度，可通过谨慎的逻辑操作定义硅化物及整合现有工艺。本技术领域中具有普通知识的技术人员可知本发明还具有许多其他变化实施例。
虽然本发明已以数个较佳实施例公开如上，然其并非用以限定本发明，任何所属技术领域中具有普通知识的技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当以所附的权利要求所界定的范围为准。

Claims (10)

1.一种横向扩散金属氧化物半导体晶体管的制造方法，包括：
形成一虚置栅极于一基材上；
形成一源极及一漏极于该基材上的该虚置栅极两侧；
形成一第一硅化物于该源极上及一第二硅化物于该漏极上，且于该源极或该漏极至少其一留下与该虚置栅极相邻的一未硅化区，以提供一能负载高电压横向金属氧化物半导体导体应用所需电压的阻抗区；以及
对该虚置栅极进行一替换栅极工艺，以形成栅极。
2.如权利要求1所述的横向扩散金属氧化物半导体晶体管的制造方法，还包含形成一硬掩模于该虚置栅极上。
3.如权利要求1所述的横向扩散金属氧化物半导体晶体管的制造方法，还包含形成一阻抗保护氧化层于至少一部分的该虚置栅极上及该未硅化区上，以保护位于该阻抗保护氧化层底下的区域不因硅化工艺形成该第一硅化物及该第二硅化物。
4.如权利要求1所述的横向扩散金属氧化物半导体晶体管的制造方法，还包含形成一第一间隔物及一第二间隔物于该虚置栅极两侧，其中该未硅化区未被该第一间隔物或一第二间隔物所覆盖。
5.如权利要求1所述的横向扩散金属氧化物半导体晶体管的制造方法，其中该栅极包含多个金属层。
6.一种横向扩散金属氧化物半导体晶体管，包括：
一基材；
一栅极，位于该基材上；
一源极及一漏极，位于该栅极两侧；
一第一硅化物，位于该源极上；以及
一第二硅化物，位于该漏极上，其中该源极或该漏极至少其一具有与该栅极相邻的一未硅化区，以提供一能负载高电压横向扩散金属氧化物半导体导体应用所需电压的阻抗区。
7.如权利要求6所述的横向扩散金属氧化物半导体晶体管，其中该未硅化区的长度为约0.05μm至1μm。
8.如权利要求6所述的横向扩散金属氧化物半导体晶体管，还包含一高介电常数介电层，位于该栅极及该基材之间。
9.如权利要求6所述的横向扩散金属氧化物半导体晶体管，其中该栅极包含多个金属层。
10.如权利要求6所述的横向扩散金属氧化物半导体晶体管，其中栅极包含一功函数金属及一沟槽填充导电材料，其中该沟槽填充导电材料是选择自下列群组：钨、铝、钛及氮化钛。
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