CN104170061B - 具有部分硅化的字线的垂直nand装置及其制造方法 - Google Patents

具有部分硅化的字线的垂直nand装置及其制造方法 Download PDF

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CN104170061B
CN104170061B CN201380015009.3A CN201380015009A CN104170061B CN 104170061 B CN104170061 B CN 104170061B CN 201380015009 A CN201380015009 A CN 201380015009A CN 104170061 B CN104170061 B CN 104170061B
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J.阿尔斯梅尔
P.拉布金
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SanDisk Technologies LLC
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Abstract

一种三维存储装置，包括衬底(100)和半导体沟道(151)。该半导体沟道的至少一个端部基本上垂直于该衬底的主表面延伸。该装置还包括设置(102)为邻近半导体沟道的至少一个电荷存储区域(114)和具有条状、基本上平行于该衬底的该主表面延伸的多个控制栅极电极。该多个控制栅极电极至少包括位于第一装置层级中的第一控制栅极电极和位于第二装置层级中的第二控制栅极电极。该多个控制栅极电极的每一个包括基本上无硅化物的第一边缘表面(102D)，该第一边缘表面面对该半导体沟道和该至少一个电荷存储区域，硅化物(128)，位于该控制栅极电极的其余表面上。控制栅极电极之间设置有空气间隙。

Description

具有部分硅化的字线的垂直NAND装置及其制造方法
技术领域
本发明总体上涉及半导体装置领域，具体而言涉及三维垂直NAND串和其它三维装置及其制造方法。
背景技术
三维垂直NAND串公开在T.Endoh,et.al.的文章中，标题为Novel Ultra HighDensity Memory With A Stacked-Surrounding Gate Transistor(S-SGT)StructuredCell,IEDM Proc.(2001)33-36。然而，该NAND串每个单元仅提供一个位。而且，NAND串的有源区域通过相对困难且耗时的工艺形成，其涉及重复地形成间隔壁且蚀刻衬底的一部分，导致大致的圆锥有源区域形状。
发明内容
一实施例涉及三维存储装置，包括衬底和半导体沟道。半导体沟道的至少一个端部基本上垂直于衬底的主表面延伸。该装置还包括设置为邻近半导体沟道的至少一个电荷存储区域和具有条形形状基本上平行于衬底的主表面延伸的多个控制栅极电极。多个控制栅极电极至少包括位于第一装置层级的第一控制栅极电极和位于第二装置层级的第二控制栅极电极，第二装置层级位于衬底的主表面之上且在第一装置层级之下。多个控制栅极电极的每一个包括基本上无硅化物的第一边缘表面，所述第一边缘表面面对半导体沟道和至少一个电荷存储区域，以及位于控制栅极电极的其余表面上的硅化物。
另一个实施例涉及制造三维存储装置的方法。该方法包括提供多个柱，其基本上垂直于衬底的主表面延伸，其中每个柱包括具有半导体沟道的芯、具有隧道电介质的第一外壳、具有电荷存储材料的第二外壳和具有阻挡电介质的第三外壳。每个柱由衬底的主表面之上的第一材料和第二材料的交替层堆叠围绕。第一材料包括IV族半导体控制栅极材料。第二材料包括牺牲材料，并且该堆叠包括分开第一柱和第二柱的至少一个沟槽。该方法还包括去除牺牲材料层以在半导体控制栅极材料各层之间形成空气间隙，并且在半导体控制栅极材料层通过去除牺牲层暴露的表面上形成硅化物。
附图说明
图1A是示出在制造根据一实施例的三维存储装置的方法中一个步骤的示意性侧视截面图。
图1B是示出在制造根据一实施例的三维存储装置的方法中另一个步骤的示意性侧视截面图。
图1C是示出在制造根据一实施例的三维存储装置的方法中另一个步骤的示意性侧视截面图。
图1D是示出在制造根据一实施例的三维存储装置的方法中另一个步骤的示意性侧视截面图。
图1E是示出在制造根据一实施例的三维存储装置的方法中另一个步骤的示意性侧视截面图。
图1F是示出在制造根据一实施例的三维存储装置的方法中另一个步骤的示意性侧视截面图。
图2是根据一实施例的存储装置的平面图。还示出了图1的方法中所用的支撑掩模样式。
图3A是根据一实施例的垂直NAND串的侧视截面图。
图3B是根据另一个实施例的另一个垂直NAND串的侧视截面图。
图4是根据一实施例的存储装置的平面图。
具体实施方式
实施例包括单片三维NAND串和制造三维NAND串的方法。在一实施例中，NAND串可形成有单一垂直沟道。在一个方面中，垂直沟道具有实心杆形状。在该方面中，整个沟道包括半导体材料。在另一个方面中，垂直沟道具有空心圆筒形状。在该方面中，垂直沟道包括非半导体芯，由半导体沟道外壳围绕。芯可不填充或者可填充有绝缘材料，例如氧化硅或氮化硅。可替换地，NAND串可具有U形状(也称为管状)，其两个垂直沟道翼部分用连接翼部的水平沟道连接。在一个方面中，U状或管状沟道可为实心的，如实心杆状垂直沟道NAND。在另一个方面中，U状或管状沟道可为空心筒形状，如空心筒管状垂直沟道NAND。U-状管沟道可被填充的或不填充的。制造两个单一垂直沟道和U状NAND串的分开前后侧的方法教导于共同在审美国专利申请系列号No.12/827,947中，以引用方式全文结合于本文，用于教导分开前侧和后侧的工艺方法。制造两个单一垂直沟道和U状NAND串的结合前后侧的方法教导于共同在审美国专利申请系列号No.13/083,775中，以引用方式全文结合于本文，用于教导组合前侧和后侧的工艺方法。
垂直沟道位成本可扩展(Bit Cost Scalable,BiCS)NAND存储器和U-状(即管状)BiCS(p-BiCS)被开发来用于超高密度存储装置。
然而，早期的BiCS和p-BiCS 3D NAND架构遭受相对高的控制栅极/字线电阻和电容。这些电阻和电容降低了单元效率且增大了存储装置的功耗。
发明人已经发现，BiCS和p-BiCS工艺的改造使得可以改善控制栅极/字线的硅化。控制栅极/字线的硅化降低了控制栅极/字线的电阻，导致装置功耗的降低并且提供单元效率的增加。BiCS和p-BiCS的另外改造方法包括在相邻装置层级中的控制栅极/字线的空间间隙(即在垂直分隔控制栅极之间的空气间隙)降低控制栅极/字线之间的电容。这也导致装置功耗上的降低并且提高单元效率。
如本文所用，术语“控制栅极”和“字线”是指相同的导电实体。控制栅极可看作字线的一部分，其设置为邻近且控制NAND单元阵列中的一个NAND单元。字线控制阵列中的多个NAND单元。因此，字线可看作是导电实体连接控制栅极的一部分。然而，应理解，字线及其控制栅极部分可在相同的步骤中形成，并且可包括一个或多个导电层，如下面所描述。
图1A-1F示出了根据本发明一实施例的制造三维存储装置(例如，垂直NAND串)的方法。在该实施例中，衬底100提供有第一材料层102和第二材料层104的交替层堆叠，其形成在衬底100的主表面100a之上。
衬底100可为本领域中已知的任何半导体衬底，诸如单晶硅、诸如硅-锗或硅-锗-碳的IV-IV族化合物、III-V族化合物、II-VI族化合物、在这样衬底上的外延层、或者任何其它半导体或非半导体材料，诸如氧化硅、玻璃、塑料、金属或陶瓷衬底。衬底100可包括制作于其上的集成电路，例如用于存储装置的驱动电路。
层102和104可通过适当的沉积方法沉积在衬底100之上，诸如溅射、化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、分子束外延(MBE)法等。优选地，第一材料层102适合于用作控制栅极。适当的材料包括但不限于：重掺杂IV族半导体，诸如硅(例如，多晶硅)、硅锗、碳化硅等。半导体可为p-型或n-型掺杂的，并且具有1017cm-3和1021cm-3之间的掺杂浓度。
第二材料层104包括牺牲材料。可采用与第一材料相比可选择性蚀刻的任何牺牲材料。例如，如果第一材料层102是p-掺杂多晶硅，则牺牲材料104可为本征多晶硅(即掺杂浓度在1016cm-3以下)。可替换地，第二材料层104可包括金属或绝缘材料(例如，氧化硅、氮化硅等)，其相对于第一材料层102可被选择性地蚀刻。该堆叠可覆盖有绝缘材料106的顶层，绝缘材料106诸如为氧化硅或氮化硅。
在沉积层102和104后，该堆叠可蚀刻为形成存储器孔108和狭缝沟槽110。狭缝沟槽110可填充有牺牲材料110A，诸如氮化硅或可相对于层102和104的材料可被选择性蚀刻的其它材料，而存储器单元形成在存储器孔108中。例如，狭缝沟槽110可首先采用光刻和蚀刻形成，然后沟槽110可填充有牺牲材料110A，接下来采用另外的光刻和蚀刻步骤形成存储器孔108。
在一实施例中，存储器单元150(例如，垂直NAND串)可用存储膜的一系列共形沉积步骤和存储器单元150的沟道柱部分151形成在存储器孔108中，如图1B所示。共形沉积技术包括但不限于原子层沉积(ALD)和化学气相沉积(CVD)。
例如，如图2所示，阻挡电介质层112可首先共形地沉积在存储器孔108中。接下来，电荷存储材料层114可共形地沉积在存储器孔108中的阻挡电介质层112上。然后，隧道电介质层116可共形地沉积在存储器孔108中的电荷存储材料114上。然后，存储器孔108的中心部分可填充有半导体沟道材料118，诸如多晶硅。
沟道材料118可包括轻掺杂p-型或n-型(即掺杂在1017cm-3以下)半导体材料(例如，多晶硅)。n-沟道装置是优选的，因为它容易与n+结(即源极和漏极n+掺杂区域，掺杂浓度在1017cm-3和1021cm-3之间，位于每个沟道的相对端)连接。然而，也可采用p-沟道装置。也可采用其它的半导体材料(例如，SiGe、SiC、Ge、III-V、II-VI族化合物等)。
阻挡电介质112可包括通过共形原子层沉积(ALD)或化学气相沉积(CVD)沉积的氧化硅层。其它的高k介电材料，例如氧化铪，可用于替代氧化硅或者与氧化硅一起使用。电介质112的厚度可为6至20nm。电荷存储区域114可包括通过任何适当方法沉积的氮化硅层，例如ALD、CVD等，并且厚度为2至20nm。隧道电介质116可包括氧化硅或其它合适材料的相对薄的绝缘层(例如，4至10nm厚)，其它合适材料诸如为氧氮化物、氧化物和氮化物多层堆叠，或者通过任何适当方法(例如，ALD、CVD)沉积的高k电介质。
共形沉积的结果是形成存储器单元150的柱151，其基本上垂直于衬底的主表面。每个存储器单元柱151包括半导体沟道芯118、隧道电介质的第一外壳116、电荷存储材料的第二外壳114和阻挡电介质的第三外壳112。阻挡介电层、电荷存储材料(即电荷捕获层)和隧道介电层基本上垂直于衬底100的主表面110A在半导体沟道118和多个控制栅极电极102之间延伸。
在一实施例中，控制栅极层102的表面102D直接物理地接触阻挡介电层112，如图1F和2所示。
在可替换实施例中，半导体沟道芯118可包括由半导体材料的外壳围绕的绝缘材料的内芯。在可替换构造中，电荷存储材料114可由多层复合物形成，诸如氧化物-氮化物-氧化物(ONO)多层，和/或阻挡电介质112可包括三层ONO电介质，从而存储膜包括ONO(112)-N(114)-O(116)。
如图1C所示，然后，绝缘材料106的顶层蚀刻为暴露出在半导体材料124的顶层中的开口122以形成上选择栅极123。在一实施例中，存储器单元150用垂直柱沟道118构成，并且上选择栅极123是漏极选择栅极。在该构造中，源极选择栅极125形成在垂直沟道的相对(衬底)端，如图3所示。作为选择，存储器单元150用U状沟道118构成，并且选择栅极包括位于U状沟道118的每个翼部118A的上端的对应的漏极选择栅极和源极选择栅极123、125。翼部118A由位于衬底100之中或上的水平沟道118B连接。
在一实施例中，在形成开口122后，支撑掩模126可沉积在绝缘材料106的顶层之上。在去除牺牲材料层110A进而去除104后，支撑掩模126对存储装置提供支撑。支撑掩模126可由任何适当的材料制造，诸如氧化物或氮化物硬掩模材料。如图2所示，掩模126可为网状掩模，其包括亮的或敞开的间隙部分126A，间隙部分126A由暗或实心网支撑部分126B围绕。
在接下来的步骤中，如图1E所示，去除狭缝沟槽110中的牺牲材料110A。该去除通过掩模126中的间隙126A选择性蚀刻(例如，湿蚀刻)沟槽110中的牺牲材料110A而不蚀刻装置中的其它材料或层而实现。去除沟槽110中的材料110A暴露出堆叠中的牺牲材料层104的侧边缘。
然后，牺牲材料层104可通过狭缝沟槽110选择性蚀刻(例如，湿蚀刻)去除，如图1F所示。这导致暴露的控制栅极102材料的平顶，其由存储器单元柱151支撑。支撑掩模126对存储器单元柱151提供附加支撑。控制栅极102在垂直方向上由其中事先设置了牺牲材料层104的空气间隙104A分隔，并且在水平方向上由狭缝沟槽110分隔。
在形成空气间隙104A后，控制栅极102的暴露表面被硅化，以在多晶硅控制栅极102的暴露表面上形成硅化物层128。硅化物层128可这样形成：在暴露的控制栅极多晶硅材料上共形沉积金属薄层，例如钨、钴、镍或钛，或者两个以上这些材料的组合，并且加热装置以使金属薄层与控制栅极材料反应。金属层可通过掩模126中的间隙126A且通过沟槽110和空气间隙104A形成。硅化物层128形成在暴露的控制栅极102的上表面102A和下表面102B上以及在控制栅极102与面102D相对的暴露面102C上，面102D接触存储装置150的电荷存储区域112。控制栅极102的上表面102A和下表面102B设置为基本上平行于衬底100的主表面100A，而控制栅极102的边缘表面或面102C、102D设置为基本上垂直于衬底100的主表面100A。硅化物层128也形成在沟槽122中暴露的选择栅极123、125的侧壁上。
在完成的装置中，每个存储器单元包括源极电极130和漏极电极132。制造源极电极130和漏极电极132的方法描述在共同在审美国专利申请序列号No.12/827,947和No.13/083,775中，以引用方式结合于本文。在图3A所示的柱沟道构造中，漏极电极130可形成在垂直存储器柱151的顶部，并且源极电极132可形成在衬底100中。在图3B所示的U-状沟道构造中，源极和漏极电极132、130二者可形成为接触垂直存储器柱(一个或多个)151的翼部118A的顶部上的源极和漏极区域。
如图2和4所示，装置层级中相邻存储器单元150中的控制栅极102可彼此连接成条134。连接到给定字线的条134可为梳子形状或指状，并且连接到相邻字线的条可相互交错，如图2所示。如上所述，条134和各控制栅极102可看成字线的部分而不是离散的元件。
在图2所示的实施例中，控制栅极条134围绕单行存储器单元150的柱151。可替换地，如图4所示，每个控制栅极102条134可围绕相邻NAND串(即存储器单元)150的两行柱151(即翼部118A)。
在图3B的U状沟道构造中，U-状沟道118的水平沟道部分118B连接狭缝沟槽110下的相邻沟道翼部118A，如图3B和4所示。因此，U-状沟道118的水平部分118B基本上垂直于控制栅极102的条134的延长方向延伸。相邻存储器单元的漏极选择栅极123可通过源极线彼此连接，而相邻存储器单元的源极选择栅极125可通过位线(未示出)彼此连接。尽管U-状NAND串150示出为控制栅极条134围绕图4的两行柱151构造，但是应理解，U-状NAND串150也可采用控制栅极条134围绕图2的一行柱151构造。
图4示出了位于相同装置层级的三个控制栅极条134A、134B和134C。控制栅极条134B位于条134A和134C之间。控制栅极条134A和134C电连接到相同的字线WL，而控制栅极条134B电连接到不同的字线(未示出)，从而条134B在相同的装置层级中在条134A和134C之间相互交错。条134A、134B和134C由空气间隙沟槽110彼此分隔。NAND串150(由虚线示出)的半导体沟道118的第一翼部118A延伸通过条134C(以及位于条134C之上和之下的其它条，例如图1F中所示的条134D)且由其围绕。半导体沟道118的第二翼部118A延伸通过条134B(以及位于条134B之上和之下的其它条，例如图1F中所示的条134E)且由其围绕。半导体沟道118的连接部分118B(以虚线示出)位于分开条的空气间隙沟槽110之下。
尽管前述涉及特别优选的实施例，但是应理解本发明不限于此。本领域的普通技术人员可对所公开实施例进行各种修改，并且这样的修改旨在包含于本发明的范围内。本文引用的所有出版物、专利申请和专利通过引用全文结合于此。

Claims (14)

1.一种三维存储装置，包括：
衬底；
半导体沟道，该半导体沟道的至少一个端部垂直于该衬底的主表面延伸；
至少一个电荷存储区域，设置为邻近半导体沟道；以及
多个控制栅极电极，具有条形形状，平行于该衬底的该主表面延伸，其中该多个控制栅极电极至少包括位于第一装置层级中的第一控制栅极电极和位于第二装置层级中的第二控制栅极电极，该第二装置层级位于该衬底的该主表面之上且在该第一装置层级之下；
其中每一个该多个控制栅极电极包括：
第一边缘表面，其无硅化物；
该第一边缘表面面对该半导体沟道和该至少一个电荷存储区域；以及
硅化物，位于该控制栅极电极的其余表面上，
其中该装置包括NAND串，
其中每一个该多个控制栅极电极包括多晶硅栅极电极，在该多晶硅栅极电极的上表面和下表面上以及不接触所述至少一个电荷存储区域的该多晶硅栅极电极的至少一个第二边缘表面上具有金属硅化物，
其中，该第一边缘表面包括接触所述至少一个电荷存储区域的该多晶硅栅极电极的边缘表面；
该多晶硅栅极电极的该第一边缘表面和该至少一个第二边缘表面设置为垂直于该衬底的该主表面；并且该上表面和该下表面设置为平行于该衬底的该主表面，
其中该至少一个电荷存储区域包括阻挡介电层、电荷捕获层和隧道介电层，在该半导体沟道和该多个控制栅极电极之间垂直于该衬底的该主表面延伸，
其中该多晶硅栅极电极的该第一边缘表面包括直接物理地接触该阻挡介电层的多晶硅表面。
2.如权利要求1所述的装置，其中该硅化物包括Ti、Ni、Co、Mo或其组合的硅化物。
3.一种三维存储装置，包括：
衬底；
半导体沟道，该半导体沟道的至少一个端部垂直于该衬底的主表面延伸；
至少一个电荷存储区域，设置为邻近半导体沟道；以及
多个控制栅极电极，具有条形形状，平行于该衬底的该主表面延伸，其中该多个控制栅极电极至少包括位于第一装置层级中的第一控制栅极电极和位于第二装置层级中的第二控制栅极电极，该第二装置层级位于该衬底的该主表面之上且在该第一装置层级之下；
其中每一个该多个控制栅极电极包括：
第一边缘表面，其无硅化物；
该第一边缘表面面对该半导体沟道和该至少一个电荷存储区域；以及
硅化物，位于该控制栅极电极的其余表面上，
其中该半导体沟道具有U-状侧视截面，该半导体沟道包括第一翼部和第二翼部，其中该U-状半导体沟道的垂直于该衬底的主表面延伸的该第一翼部和该第二翼部由平行于该衬底的主表面延伸的连接部分连接；
还包括位于该第一装置层级中的第三和第四控制栅极电极，其中该第三控制栅极电极位于该第一装置层级中的该第一控制栅极电极和该第四控制栅极电极之间；
其中，
该第一控制栅极电极和该第四控制栅极电极电连接到第一字线；
该第三控制栅极电极电连接到与该第一字线不同的第二字线，从而该第三控制栅极电极在该第一装置层级中的该第一控制栅极电极和第三控制栅极电极之间相互交错；
该第一、第三和第四控制栅极电极由空气间隙沟槽彼此分隔；
该半导体沟道的该第一翼部延伸通过该第一控制栅极电极和该第二控制栅极电极且由它们围绕；
该半导体沟道的该第二翼部延伸通过该第三控制栅极电极且由其围绕；并且
该半导体沟道的该连接部分位于分开该第一控制栅极电极与该第三控制栅极电极的空气间隙沟槽之下。
4.如权利要求3所述的装置，还包括：
源极或漏极电极中的一个，从上面接触该半导体沟道的第一翼部；
源极或漏极电极中的另一个，从上面接触该半导体沟道的第二翼部；
第一选择栅极电极，位于该源极或漏极电极中的所述一个之下、邻近该半导体沟道的该第一翼部；以及
第二选择栅极电极，位于该源极或漏极电极中的所述另一个之下、邻近该半导体沟道的该第二翼部。
5.一种三维存储装置，包括：
衬底；
半导体沟道，该半导体沟道的至少一个端部垂直于该衬底的主表面延伸；
至少一个电荷存储区域，设置为邻近半导体沟道；以及
多个控制栅极电极，具有条形形状，平行于该衬底的该主表面延伸，其中该多个控制栅极电极至少包括位于第一装置层级中的第一控制栅极电极和位于第二装置层级中的第二控制栅极电极，该第二装置层级位于该衬底的该主表面之上且在该第一装置层级之下；
其中每一个该多个控制栅极电极包括：
第一边缘表面，其无硅化物；
该第一边缘表面面对该半导体沟道和该至少一个电荷存储区域；以及
硅化物，位于该控制栅极电极的其余表面上，
其中，该半导体沟道具有柱状，从上面看具有实心或空心的圆形横截面；并且
该整个柱状半导体沟道垂直于该衬底的该主表面延伸；
其中该第一控制栅极电极位于该第一装置层级中，直接在位于该第二装置层级中的该第二控制栅极电极之上，并且该第一控制栅极电极与该第二控制栅极电极由空气间隙分隔。
6.如权利要求5所述的装置，还包括：
源极或漏极电极中的一个，其从上面接触该柱状半导体沟道；
源极或漏极电极中的另一个，其从下面接触该柱状半导体沟道；
第一选择栅极电极，位于该源极或漏极电极中的该一个之下、邻近该半导体沟道的顶部；以及
第二选择栅极电极，位于该源极或漏极电极中的该另一个之上、邻近该半导体沟道的底部。
7.一种制造三维存储装置的方法，包括：
提供垂直于衬底的主表面延伸的多个柱，每个柱包括芯、第一外壳、第二外壳和第三外壳，该芯包括半导体沟道，该第一外壳包括隧道电介质，该第二外壳包括电荷存储材料，该第三外壳包括阻挡电介质；
其中，
每个柱由该衬底的该主表面之上的第一材料和第二材料的交替层的堆叠围绕；
该第一材料包括IV族半导体控制栅极材料；
该第二材料包括牺牲材料；并且
该堆叠包括分隔第一柱与第二柱的至少一个沟槽；
去除该牺牲材料层以在该半导体控制栅极材料层之间形成空气间隙；并且
在该半导体控制栅极材料层通过去除该牺牲材料暴露的表面上形成硅化物；
其中形成该硅化物的步骤包括在该半导体控制栅极材料层通过去除该牺牲材料暴露的表面上形成金属层以及退火该金属层以使该金属层与该半导体控制栅极材料反应而形成该硅化物；
其中该半导体控制栅极材料层接触该多个柱的至少一个柱的第一边缘表面没有硅化物，并且该硅化物位于该半导体控制栅极材料层的其余表面上；
其中，
该装置包括NAND串；
该半导体控制栅极材料层的每一层包括多晶硅栅极电极，该多晶硅栅极电极在该多晶硅栅极电极不接触该阻挡电介质的上表面和下表面以及在至少一个第二边缘表面上具有金属硅化物；
该第一边缘表面包括该多晶硅栅极电极直接物理地接触该阻挡电介质的边缘表面；
该多晶硅栅极电极的该第一边缘表面和该至少一个第二边缘表面设置为垂直于该衬底的该主表面；该上表面和该下表面设置为平行于该衬底的该主表面；并且
该硅化物包括Ti、Ni、Co、Mo或者其组合的硅化物；
其中该半导体沟道具有U-状侧视截面，该半导体沟道包括第一翼部和第二翼部，其中该U-状半导体沟道垂直于该衬底的该主表面延伸的该第一翼部和该第二翼部由平行于该衬底的该主表面延伸的连接部分连接。
8.如权利要求7所述的方法，还包括：
形成源极或漏极电极中的一个，使其从上面接触该半导体沟道的该第一翼部；
形成源极或漏极电极中的另一个，使其从上面接触该半导体沟道的该第二翼部；
形成第一选择栅极电极，其位于该源极或漏极电极中的该一个之下、邻近该半导体沟道的该第一翼部；以及
形成第二选择栅极电极，其位于该源极或漏极电极中的该另一个之下、邻近该半导体沟道的该第二翼部。
9.如权利要求7所述的方法，其中，
该半导体沟道具有柱状，从上面看具有实心或空心的圆形横截面；并且
该整个柱状半导体沟道垂直于该衬底的该主表面延伸。
10.如权利要求9所述的方法，还包括：
形成源极或漏极电极中的一个，使其从上面接触该柱状半导体沟道；
形成源极或漏极电极中的另一个，使其从下面接触该柱状半导体沟道；
形成第一选择栅极电极，其位于该源极或漏极电极中的该一个之下、邻近该半导体沟道的顶部；以及
形成第二选择栅极电极，其位于该源极或漏极电极中的该另一个之下、邻近该半导体沟道的底部。
11.如权利要求10所述的方法，其中该半导体沟道包括实心圆柱或者填充有绝缘材料的空心芯。
12.一种制造三维存储装置的方法，包括：
提供垂直于衬底的主表面延伸的多个柱，每个柱包括芯、第一外壳、第二外壳和第三外壳，该芯包括半导体沟道，该第一外壳包括隧道电介质，该第二外壳包括电荷存储材料，该第三外壳包括阻挡电介质；
其中，
每个柱由该衬底的该主表面之上的第一材料和第二材料的交替层的堆叠围绕；
该第一材料包括IV族半导体控制栅极材料；
该第二材料包括牺牲材料；并且
该堆叠包括分隔第一柱与第二柱的至少一个沟槽；
去除该牺牲材料层以在该半导体控制栅极材料层之间形成空气间隙；并且
在该半导体控制栅极材料层通过去除该牺牲材料暴露的表面上形成硅化物；
其中形成该硅化物的步骤包括在该半导体控制栅极材料层通过去除该牺牲材料暴露的表面上形成金属层以及退火该金属层以使该金属层与该半导体控制栅极材料反应而形成该硅化物；
其中提供多个柱的步骤包括：
在该堆叠中形成多个沟槽；
用与该第一材料和该第二材料不同的沟槽填充材料填充该多个沟槽；
蚀刻该堆叠以在该堆叠中形成多个开口；
形成该第三外壳，其包括在该堆叠的该多个开口中的该阻挡电介质；
形成该第二外壳，其包括在该第三外壳内的该电荷存储材料；
形成该第一外壳，其包括在该第二外壳内的该隧道电介质；以及
形成芯，其包括在该第一外壳内的该半导体沟道。
13.如权利要求12所述的方法，还包括：
在该堆叠之上形成硬掩模；
在该硬掩模中形成间隙；以及
在去除该牺牲材料层的步骤前，通过该硬掩模中的该间隙从该多个沟槽选择性地去除该沟槽填充材料。
14.如权利要求13所述的方法，其中，
选择性地去除该沟槽填料的步骤包括选择性地湿蚀刻该沟槽填充材料而不蚀刻该第一材料和该第二材料；
去除该牺牲材料层的步骤包括通过该沟槽选择性地湿蚀刻该牺牲材料层；并且
在半导体控制栅极材料层的表面上形成金属层的步骤包括通过该沟槽形成该金属层。
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