CN103855216A - 包括交替的源极和漏极区域以及相应的源极和漏极金属带的半导体器件 - Google Patents

包括交替的源极和漏极区域以及相应的源极和漏极金属带的半导体器件 Download PDF

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CN103855216A
CN103855216A CN201310616727.8A CN201310616727A CN103855216A CN 103855216 A CN103855216 A CN 103855216A CN 201310616727 A CN201310616727 A CN 201310616727A CN 103855216 A CN103855216 A CN 103855216A
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metal
drain
source
metal band
ldmos
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CN103855216B (zh
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A·W·洛特菲
J·德姆斯基
A·菲根森
D·D·洛帕塔
J·诺顿
J·D·威尔德
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Intel Corp
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Altera Corp
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Abstract

本发明提供一种半导体器件及形成半导体器件的方法，在一个实施例中，半导体器件包括衬底1105和在衬底1105上被形成为交替图案的多个源极“s”区域和漏极“d”区域。半导体器件还包括多个栅极1150，在多个源极区域和漏极区域中的源极区域和漏极区域之间并且与其平行地形成于衬底1105之上。半导体器件还包括第一多个交替的源极金属带和漏极金属带1111、1121，形成于在衬底1105上方的第一金属层中，并且与多个源极区域和漏极区域中的相应源极区域和漏极区域平行并且形成电接触。

Description

包括交替的源极和漏极区域以及相应的源极和漏极金属带的半导体器件
相关申请的交叉引用 
本申请要求2012年11月30日提交的名称为“Metal Oxide Semiconductor Device and Method of Forming the Same; 
Three-Dimensional Decoupled Package for Highly Distributed LDMOS Power Switches for Use in Switch-Mode DC-DC Power Converters; 
Three-Dimensional Mixed Pillar Routing for Highly Distributed LDMOS Power Switches for Use in Switch-Mode Power Converters; 
Semiconductor Device Formed with Plural Metallic Layers”的美国临时申请No.61/732,208的权益，该申请在此通过引用整体并入本文。 
技术领域
本发明总体涉及半导体器件，并且更具体而言涉及金属氧化物半导体器件及其形成方法。 
背景技术
可以在定制的高速横向扩散金属氧化物半导体（“LDMOS”）工艺中在硅晶片上制作横向功率开关/晶体管。横向功率开关由大量单元形成，其中允许在晶片顶部侧上路由进入和离开器件端子。与传统竖直和沟槽型器件不同，通常不采用背侧路由。此外，在使用深亚微米光刻技术时，单元的节距（或半节距）降至5微米（μm）以下，这使得源极和漏极金属化更为紧凑，其中较少空间可用于耦合至上层金属接触。上侧金属接触路由至位于半导体封装的外围处的外部封装管脚。这种难处转化为两个不利挑战。 
第一个挑战是降低的金属宽度，这导致在开关的高电流漏极和 源极端子与外部封装管脚之间的增加的电阻。第二个挑战是较大量的开关漏极和源极金属交叠，这导致增加的通常称为“Coss”的开关输出电容。 
在信号或数字应用中，尺寸减小并不妨碍路由。然而，如果应用是功率管理器件，则开关的分段则理想地以非常低的阻抗路由至外部管脚，并且也具有从共同参考点测量的相同阻抗。这一状况难于实现，这是因为单元的内部部分距离外围比单元的外围部分距离外围更远，从而导致去往外部封装管脚的内部连接的电压和功率损耗，如上述两个挑战所反映的那样。 
当源极、漏极和栅极线在电学上远离其相应单点输入信号生成器时，出现分布式传输线问题。在没有补救措施的情形下，在电学上长的连接实际上变成延迟线，这导致在接通或断开异常大精细节距开关方面的问题。效果是从传输线的一端去往另一端地从输入信号生成器传播至有效电流宿的逐渐和缓慢接通（或断开）行为，从而导致在横向功率开关的一些部分断开时其它一些部分仍保持接通，或与之相反。这导致对测量功率开关的潜在地破坏状况（称为“射穿”（shoot through）），这是因为该情况使得电源轨瞬间短路至局部电路接地，从而导致潜在的破坏电流。典型地，在电路设计中通过减缓驱动电路接通或断开这类开关的速度来消除这类问题。虽然这一方案可行，但使得利用深亚微米的高速LDMOS器件的目的破灭。因此，用于大的深亚微米开关的工艺高速互连配置和用于形成这类开关的对应工艺将是有益的。 
相应地，本领域需要的是克服本领域中切换速度、布局缺陷以及开关器件结构限制的包括开关（例如LDMOS器件）的半导体器件及其形成方法。此外，需要一种可以高速切换并且能够用于构造功率变换器或其一部分的紧凑LDMOS器件。 
发明内容
通过本发明的一些有利实施例（包括半导体器件及其形成方法） 总体解决或规避这些问题或其它问题，并且总体实现技术优势。在一个实施例中，半导体器件包括衬底和在衬底上被形成为交替图案的多个源极区域和漏极区域。半导体器件还包括多个栅极，在多个源极区域和漏极区域中的源极区域和漏极区域之间并且与其平行地形成于衬底之上。半导体器件还包括第一多个交替的源极金属带和漏极金属带，形成于在衬底上方的第一金属层中，并且与多个源极区域和漏极区域中的相应源极区域和漏极区域平行并且形成电接触。 
前述内容相当宽泛地概述了本发明的一些特征和技术优势，以便可以更好地理解本发明下面的具体描述。在形成本发明的权利要求主题的本文中将描述本发明的附加特征和优势。本领域技术人员应该理解，所公开的概念和具体实施例可以被容易地用作修改或设计用于执行本发明的相同目的的其它结构或工艺的基础。本领域技术人员可以理解，这类等同构造并不偏离在所附权利要求书中阐述的本发明的精神和范围。 
附图说明
为了更为完整地理解本发明，现在将参考下面结合所附附图的描述，在附图中： 
图1示出了包括半导体器件的功率变换器的实施例的框图； 
图2A和图2B示出了在包封之前的电子器件/功率变换器的实施例的等距视图； 
图3示出了半导体器件的一部分的实施例的截面图； 
图4示出了半导体器件的实施例的正视图，其显示了通过金属柱耦合至多个解耦合器件的倒转半导体裸片； 
图5示出了形成有周缘环分布系统的半导体器件的实施例的平面图； 
图6示出了形成为在半导体裸片上沉积的重分布层的实施例的平面图； 
图7示出了在图6中示出的重分布层的平面图，其中叠置了显示N-LDMOS器件和P-LDMOS器件的轮廓； 
图8和图9示出了在图6中示出的重分布层的放大平面图； 
图10示出了N型金属氧化物半导体（“NMOS”）反相器链的实施例的示意图，该反相器链被配置成根据脉宽调制（“PWM”）信号产生在图1中示出的大幅栅极驱动信号以用于N-LDMOS器件； 
图11示出了在半导体器件中体现的部分构造的N-LDMOS器件的一部分或一些部分的实施例的简化三维图； 
图12示出了在形成基本平面的第二金属层之后的部分构造的N-LDMOS器件的一部分的简化三维图； 
图13示出了在形成第二金属层之后部分构造的N-LDMOS器件的一部分的简化平面图； 
图14示出了在形成基本平面的第三金属层之后部分构造的N-LDMOS器件的一部分的简化平面图； 
图15示出了在形成第三金属层之后部分构造的N-LDMOS器件的一部分的简化平面图； 
图16示出了包括N-LDMOS和P-LDMOS器件的部分构造的半导体器件的实施例的简化三维图，其示出在其第二金属层中的源极金属带和漏极金属带的几何结构； 
图17示出了包括N-LDMOS和P-LDMOS器件的部分构造的半导体器件的简化三维图，其示出在其第三金属层中的源极和漏极接触的几何结构； 
图17A示出了包括N-LDMOS和P-LDMOS器件的部分构造的半导体器件的简化三维图，其示出用于重分布层的过孔的几何结构； 
图17B示出了包括N-LDMOS和P-LDMOS器件的部分构造的半导体器件的简化三维图，其示出重分布层的几何结构； 
图17C示出了包括N-LDMOS和P-LDMOS器件的部分构造的半导体器件的简化三维图，其示出用于重分布层的柱的几何结构； 
图17D示出了包括N-LDMOS和P-LDMOS器件的部分构造的 半导体器件的简化三维图，其示出传导图案化引线框架的几何结构； 
图18示出了包括N-LDMOS和P-LDMOS器件的封装的半导体器件的实施例的三维外视图； 
图19示出了包括N-LDMOS器件和/或P-LDMOS器件的半导体器件的一部分的实施例的正视图； 
图20示出了在半导体器件中体现的N-LDMOS器件或其一些部分的实施例的截面图； 
图21至图87示出了形成在半导体器件中体现的N-LDMOS器件或其一些部分的实施例的截面图； 
图88示出了在半导体器件中体现的P-LDMOS器件或其一些部分的实施例的截面图；以及 
图89示出了在半导体器件中体现的P-LDMOS器件或其一些部分的实施例的截面图。 
在不同附图中的对应数字和符号指代对应部件，除非另有指示。附图被绘制为清楚示出优选实施例的相关方面，并且并不必然按比例绘制。 
具体实施方式
下面具体论述当前优选实施例的制作和使用。然而应理解，实施例提供了可以在各种具体情形中体现的许多可应用发明构思。所论述的具体实施例仅示出用于制作和使用本发明的具体方式，并且并不限制本发明的范围。 
在具体情形中描述实施例，即，开关（例如在LDMOS器件中体现）、包括LDMOS器件的半导体器件及其形成方法。虽然将在运用LDMOS器件的功率变换器的环境中描述本发明的原理，但是可以从该器件获益并且可以以高速切换的任何应用或相关半导体技术完全位于本发明的广义范围内。 
首先参见图1，示出了包括半导体器件的功率变换器的实施例的框图。功率变换器包括功率传动装置（power train）110、控制器120、以及驱动器130，并且提供功率给诸如微处理器之类的系统。虽然在 图示的实施例中，功率传动装置110运用降压变换器拓扑，但是本领域技术人员应该理解诸如正向变换器拓扑之类的其它变换器拓扑也完全位于本发明的广义范围内。 
功率变换器的功率传动装置110在其输入处接收来自电功率源（由电池表示）的输入电压Vin并且提供经调节的输出电压Vout以为例如在功率变换器的输出处的微处理器供电。与降压变换器拓扑的原理相一致地，输出电压Vout一般低于输入电压Vin，使得功率变换器的切换操作可以调节输出电压Vout。主开关Qmn[例如，在P型横向扩散金属氧化物半导体(“P-LDMOS”)器件中体现的P沟道金属氧化物半导体场效应晶体管(“MOSFET”)]被启用以在主间隔（一般与主开关Qmn的主占空比“D”共存）期间传导并且将输入电压Vin耦合至输出滤波电感器Lout。在主间隔期间，流经输出滤波电感器Lout的电感器电流ILout随着电流从输入流至功率传动装置110的输出而增加。电感器电流ILout的ac分量由输出滤波电容器Cout滤除。 
在互补间隔（一般与主开关Qmn的互补占空比“1-D”共存）期间，主开关Qmn转变至非传导状态，并且辅助开关Qaux[例如在N型横向扩散金属氧化物半导体(“N-LDMOS”)器件中体现的N沟道MOSFET]被启用以传导。辅助开关Qaux提供用于维持流经输出滤波电感器Lout的电感器电流ILout的连续性的路径。在互补间隔期间，通过输出滤波电感器Lout的电感器电流ILout降低。总体而言，主开关和辅助开关Qmn、Qaux的相应占空比可以调整成维持对功率变换器的输出电压Vout的调节。然而本领域技术人员应该理解，主开关和辅助开关Qmn、Qaux的传导时段可以由小的时间间隔分开，以避免其间的交叉传导，并且有利地减少与功率变换器相关联的切换损耗。 
功率变换器的控制器120从内部源或外部源接收可以与微处理器相关联的期望的功率变换器特性（诸如期望系统电压Vsystem），并且接收功率变换器的输出电压Vout。根据前述特性，控制器120提供信号（例如，脉宽调制(“PWM”)信号SPWM）以控制功率传动装置110的占空比和主开关和辅助开关Qmn、Qaux的频率以调节其输出电压Vout。适配成控制功率变换器的至少一个开关的任何控制器完全位于 本发明的广义范围内。 
功率变换器也包括：驱动器130，被配置成基于由控制器120提供的PWM信号SPWM分别提供驱动信号SDRV1、SDRV2给主开关和辅助开关Qmn、Qaux。存在许多已知可行的备选以实现驱动器130，其包括用于在控制功率变换器中多个开关时提供充足信号延迟以防止逆流（crosscurrent）的技术。驱动器130典型地包括：切换电路装置，并入协作以提供驱动信号SDRV1、SDRV2给主开关和辅助开关Qmn、Qaux的多个驱动器开关。当然，能够提供驱动信号SDRV1、SDRV2以控制开关的任何驱动器130完全位于本发明的广义范围内。 
在一个实施例中，主开关和辅助开关Qmn、Qaux是可以被并入到邻近控制或信号处理器件的执行功率变换器的控制器120的控制功能的半导体器件中的功率开关。控制和信号处理器件典型地是互补金属氧化物半导体(“CMOS”)器件，诸如P型金属氧化物半导体(“PMOS”)器件和N型金属氧化物半导体(“NMOS”)器件。PMOS和NMOS器件也可以分别称为P沟道和N沟道MOSFET。控制和信号处理器件运用低电压（例如2.5伏特）（因此，该器件也称为“低电压器件”）以防止其精细线结构之间的闪络（flashover）。功率传动装置110的主开关和辅助开关Qmn、Qaux以及驱动器130的多个驱动器开关之一可以由LDMOS器件形成，LDMOS器件处理较高电压（例如10伏特），并且因此被称为较高电压器件。在半导体衬底上集成控制和信号处理器件、功率开关和驱动器开关提供功率变换器或运用类似器件的其它装置的成本和尺寸方面的实质性减少的机会。 
因此，如图1所示，控制器120的输入耦合至或接收功率变换器的输出电压Vout以调节输出电压Vout。控制器120可以运用误差放大器（使用模拟运算放大器构造），其中反相输入耦合至功率变换器的输出电压Vout。误差放大器的非反相输入耦合至代表功率变换器的期望的调节的输出电压的参考电压。功率变换器的功率开关的占空比由时钟信号初始化。为了终止占空比，由模拟比较器将误差放大器的输出与倾斜电压波形进行比较，该倾斜电压波形典型地是周 期性斜坡电压波形或者具有叠加的成比例的开关或电感器电流的周期性斜坡电压波形。当误差放大器的输出超过倾斜的电压波形时，功率开关的占空比由模拟比较器终止。该控制器结构的结果是反馈布置，其中模拟比较器连续地做出在启用功率开关以传导的时间间隔期间终止功率开关占空比的决策。该模拟控制器架构使用不基于时钟频率或数字逻辑的计算速率的精细时间粒度（temporal granularity）实现功率开关占空比的终止。也可以运用数字电路装置构造控制器。 
现在参见图2A和图2B，示出了在包封之前的电子器件/功率变换器（例如功率模块）的实施例的等距视图。功率变换器包括磁器件（例如电感器）、集成电路、以及表面安装部件。功率变换器可以包括功率变换电路装置，其包括磁器件、集成电路和至少一个表面安装部件或在其中体现。功率变换电路装置可以形成经常包括切换调节器的功率变换器或具有用于降低分量计数的集成控制电路和用于高功率变换效率的同步整流器的诸如降压切换调节器之类的功率变换器。当然，实施例不限于功率模块、功率变换器等，并且可以可应用于其它电子器件。 
传导基底（或引线框架）210被图案化和蚀刻以形成用于电感器的线圈的较低部分的电传导互连层、以及表面安装部件、集成电路和电感器之间的电互连。引线框架210的典型厚度约8密耳（千分之一英寸）。虽然引线框架210经常由铜构造，但是对其可以使用备选电传导材料。引线框架210提供用于功率模块的外部连接以及用于电感器的瓷材料的支撑基部。外部连接形成为引线框架210的指部，表示为引线框架指部（其中的两个指部标记为215、216）。 
引线框架210一般用围绕电传导图案的一体金属带构造，以提供在制造步骤期间的机械支撑，该金属带随后在制造工艺中被丢弃。围绕的金属带一般在构造电子器件之后被切断，例如从而提供未连接的迹线。一般在重复图案阵列（未示出，例如16×16阵列）中产生引线框架210，以例如形成256个基本等同的电子器件。形成引线框架210的阵列是本领域熟知的工艺，以减少生产电子器件的制造 成本。 
将焊料膏选择性地涂敷到薄层引线框架210的区域（标记为225）以用于丝网工艺，从而提供用于表面安装部件的电和机械附接。诸如电容器（其中之一标记为220）之类的表面安装部件被放置成使其传导端位于焊料膏中。焊料膏可以由基于铅的成分以及无铅成分构成。具有表面安装部件220的引线框架210的阵列在炉中回流，以将表面安装部件220机械和电附接至引线框架210。 
上述步骤一般不要求在洁净室的高度受控环境中执行。然而随后的步骤优选地在洁净室环境（诸如如本领域一般熟知的典型地用于将集成电路组装进模制塑料封装中的洁净室环境）中执行。 
将粘合剂（例如裸片附接粘合剂，诸如加利福利亚州的Rancho Dominguez的Ablestik的Abletherm2600AT）分发至引线框架210上，以保持磁芯（例如磁材料条）230和形式为半导体裸片240的集成电路。磁材料条230和半导体裸片240置于裸片附接粘合剂之上的引线框架210上。因此，磁材料条230的下表面面对引线框架210并且优选地附接至引线框架210。包括磁材料条230以增强电感器的磁属性，并且磁材料条230可以约250微米(“μm”)厚，4密耳宽和7.5密耳长。典型地在受控热工艺中固化粘合剂以将磁材料条230和半导体裸片240固定至引线框架210。 
将焊料膏涂敷至引线框架210的放置传导夹250的端部的区域（总体标记为260）。同样地，焊料膏可以由基于铅的成分以及无铅成分构成。传导夹250（例如约8-12密耳厚）在磁材料条230上方置于引线框架210上，磁材料条230的端部处于焊料膏中。传导夹250形成为其端部朝引线框架210在磁材料条230的端部周围弯曲而没有机械干扰。因此，磁材料条230的上表面面对传导夹250。绝缘间隙（例如约5密耳空气间隙）因此优选地留在磁材料条230的上表面和传导夹250的下表面之间，该间隙随后可以由包封剂填充。传导夹250在每个磁材料条230之上提供电传导电感器线圈的一部分。引线框架210在回流炉中被加热以将传导夹250机械和电键合至引线框架210。 
可以由金接线形成的键合接线（诸如第一键合接线265）附接至每个半导体裸片240和引线框架210，以将半导体裸片240上的焊盘电耦合至引线框架210的键合区域，从而提供在其间的电路连接。诸如第二键合接线266之类的键合接线也可以用于将引线框架210的多个部分选择性地电耦合，以提供在单平面布局中无法容易接线的电路互连，因此产生用于两层印刷电路板（也称为“印刷线路板”）或基底的引线框架210的拓扑布局功能性。 
当如上所述地在阵列中形成电子器件时，在模具中放置阵列，并且在其上沉积（诸如注射）诸如模制材料之类的包封剂（优选为环氧树脂），这在本领域中是熟知的，以提供环境和机械保护以及热传导涂层，从而有助于在操作期间热耗散。在没有包封剂的情形下其它模制材料和工艺以及构造的电子器件也完全位于本发明的广义范围内。 
现在参见图3，示出了半导体器件的一部分的实施例的截面图。鉴于用于构造关于图3示出的半导体器件的工艺步骤与Lotfi等人在2004年1月29日提交的名称为“Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same”的美国专利7,230,302、Lotfi等人在2009年8月28日提交的名称为“Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same”的美国专利8,212,315、Lotfi等人在2007年8月20日提交的名称为“Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same”的美国专利申请公开No.2007/0284658、Lotfi等人在2012年8月15日提交的名称为“Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same”的美国专利申请公开No.2012/0306011中描述的步骤相似，因此在此不再具体描述该工艺中的步骤。这些专利和专利申请在此通过引用整体并入本文。然而，在本文中随后将描述一些工艺步骤以用于构造相似器件。 
图3中示出的截面图示出了P-LDMOS和N-LDMOS器件的多个 单独的LDMOS单元，其中使用大量这类单元构造多个单独的LDMOS单元。在一个实施例中，图3中示出的单独单元的图案根据需要镜像重复，以产生P-LDMOS或N-LDMOS器件，其中合适额定电流以供应用。由此，衬底例如形成有多个重掺杂源极区域和重掺杂漏极区域。 
在包括在衬底315（例如P型衬底）内的浅沟槽隔离区域310的半导体裸片中形成半导体器件，以提供在PMOS、NMOS、P-LDMOS和N-LDMOS器件之间的电介质分离。在衬底315的表面上生长外延层316（例如P型外延层），优选地掺杂为1·1014和1·1016原子/cm3之间。掩埋层（例如N型掩埋层）320在衬底315内在容纳P-LDMOS和N-LDMOS器件的区域中凹陷。 
半导体器件也包括在衬底315中在容纳P-LDMOS和N-LDMOS器件的区域中并且在（用于P-LDMOS）N型掩埋层320之上的浅沟槽隔离区域310之下形成的阱（例如N型阱）325。形成N型阱325以提供用于PMOS器件和P-LDMOS器件的电隔离，并且与N型掩埋层320（在P-LDMOS器件的情形中）和浅沟槽隔离区域310协作操作以提供隔离。如图所示，在N型掩埋层320之上的N型阱325并不完全覆盖衬底315中在浅沟槽隔离区域310之间的容纳P-LDMOS器件的区域。因此出于本文阐述的原因构造用于P-LDMOS的N型阱325。 
半导体器件包括在衬底315中在浅沟槽隔离区域310之间基本上在容纳NMOS器件和N-LDMOS器件的区域中形成的附加的阱(例如P型阱)330。虽然在N型掩埋层320之上的P型阱330覆盖衬底315中在其浅沟槽隔离区域310之间的容纳N-LDMOS器件的整个区域，但是也在本发明的广义范围内限定P型阱330覆盖衬底315中的容纳N-LDMOS器件的区域的一部分。半导体器件也包括PMOS、NMOS、P-LDMOS和N-LDMOS器件的在栅极电介质层335之上的栅极340并且包括在其栅极340周围的栅极侧壁间隔物355。 
N-LDMOS器件包括用于其漏极的轻掺杂耐压增强区域（例如N型轻掺杂区域）345。P-LDMOS器件也包括用于其漏极的轻掺杂耐 压增强区域(例如P型轻掺杂区域)350。在本本实施例中并且出于与上面相似的原因，N型和P型轻掺杂区域345、350提供分别用于N-LDMOS和P-LDMOS器件的较高的额定电压。因此，N-LDMOS和P-LDMOS器件不仅应对从其漏极到源极的较高电压，器件也可以应对当源极比栅极340更为正时的从其源极到栅极的较高电压。可以意识到，N型和P型轻掺杂区域345、350的宽度可以单独地变化以更改相应N-LDMOS和P-LDMOS器件的击穿电压特性，而不偏离本发明的范围。此外，可以以与在上文引用的美国专利No.7,230,302中关于图2至图15描述和示出的相应的N-LDMOS和P-LDMOS器件相似的方式形成N型和P型轻掺杂区域345、350。 
半导体器件也包括用于NMOS器件的源极和漏极的、优选地具有与用于N-LDMOS器件的源极和漏极的掺杂区域（例如N型重掺杂区域）362不同掺杂浓度分布的重掺杂区域（例如N型重掺杂区域）360。如上所述，用于NMOS器件的N型重掺杂区域360在其P型阱330内形成，用于形成NMOS器件的源极和漏极。此外，用于N-LDMOS器件的N型重掺杂区域362在其P型阱330内形成。此外，N-LDMOS器件的漏极的N型重掺杂区域362与其N型轻掺杂漏极区域345相邻。 
半导体器件也包括用于PMOS器件的源极和漏极的、优选地具有与用于P-LDMOS器件的源极和漏极的掺杂区域（例如P型重掺杂区域）367不同掺杂浓度分布的重掺杂区域（例如P型重掺杂区域）365。如上所述，用于PMOS器件的P型重掺杂区域365在其N型阱325内形成，用于形成PMOS器件的源极和漏极。此外，用于P-LDMOS器件的P型重掺杂区域367在其N型阱325内形成。此外，P-LDMOS器件的漏极的P型重掺杂区域367与其P型轻掺杂漏极区域350相邻。 
在示出的实施例中，在N型掩埋层320之上的N型阱325并不覆盖衬底315中在其浅沟槽隔离区域310之间的容纳P-LDMOS器件的整个区域。具体而言，N型阱325位于沟道区域370之下和之内，并且N型阱325和N型掩埋层320相比于P型轻和重掺杂区域350、 367相反地掺杂。因此，与轻掺杂区域350相同掺杂类型的掺杂区域（例如P型掺杂区域）372在P-LDMOS器件的漏极的P型重掺杂区域367和N型阱325之间延伸，并且具有低于P型重掺杂区域367的掺杂浓度分布的掺杂浓度分布。虽然P型重掺杂区域367优选地具有相同掺杂浓度分布，但是在本发明的广义范围内源极的P型重掺杂区域367也可以具有与漏极掺杂区域不同的掺杂浓度分布。相同的原理应用于半导体器件的其它类似的器件区域。与轻掺杂区域350相同掺杂类型的掺杂区域372一起将漏极的重掺杂区域367与在相反掺杂N型阱325中形成的沟道区域370分开。 
P型掺杂区域372可以碰巧在具有1·1014和1·1016原子/cm3之间的掺杂浓度分布的衬底315中体现。将衬底315运用为P型掺杂区域372提供了在制造半导体器件中省略掩蔽和处理步骤的机会。在又一备选实施例中，可以在注入用于P-LDMOS器件的源极和漏极的P型重掺杂区域367之前通过离子注入工艺形成P型掺杂区域372。当然，可以使用低于P型重掺杂区域367的任何掺杂浓度分布来形成P型掺杂区域372。 
将P型掺杂区域372并入P-LDMOS器件还增加了在P-LDMOS器件的P型重掺杂区域367和N型阱325之间的击穿电压。因此，P-LDMOS器件因其较高的击穿电压展现出较高的漏极到源极电压应对能力，并且也提供了当源极相比于栅极340为正时的较高的源极到栅极电压应对能力。应该理解，虽然已经关于P-LDMOS器件描述了掺杂区域，但是原理可以等同的应用于N-LDMOS器件，以及就此而言的类似构造的其它晶体管。 
关于图3描述和示出的P-LDMOS和N-LDMOS器件称为非对称器件。换言之，图3的半导体器件的非对称性质提供了非对称器件。当然，本领域技术人员应该理解，源极和漏极的尺度（包括其轻和重掺杂区域）可以变化，并且仍然落入本发明的广义范围内。半导体器件也包括用于PMOS、NMOS、P-LDMOS和N-LDMOS器件的栅极、源极和漏极的、由在硅化物层（其中之一标记为375）之上形成的电介质区域380限定的金属接触385。 
如本文所述，半导体器件（也称为“功率半导体器件”）包括优选地以分布方式置于包括在LDMOS器件中体现的MOSFET（也称为“功率MOSFET”或“增强型MOSFET”）的半导体裸片之下的一个或多个解耦合电容器，以减少驱动器运用的电压源的阻抗。可以在半导体裸片的外围上分布驱动器，以基本上均衡耦合至MOS器件的单独MOS单元和LDMOS器件的LDMOS单元的驱动信号的时序。一般可以理解，通过在公共裸片中并联耦合大量小的LDMOS单元（例如100000个或更多单元）的源极和漏极并且从公共电路节点并联驱动LDMOS单元的单独栅极来形成LDMOS器件。设计挑战是匹配耦合至单独栅极的信号的时序，从而使得LDMOS单元基本同时地接通或断开。无法维持去往单独栅极的信号的同步可能导致半导体器件失效。在常规设计中，抑制栅极信号的高频特性，从而使得所得较低频率信号基本同时到达。 
现在针对结构描述一个实施例以有效地将信号路由进入和离开在半导体裸片内形成的LDMOS器件。一个实施例中，在半导体裸片内形成多个LDMOS单元。在半导体裸片内形成分布式周界信号路径，其中分布式三维解耦合使用金属柱（伸长的铜柱），该金属柱可以形成为具有纵横比（例如等于或大于1比1），以从LDMOS器件的漏极或源极接触（或从发射极或集电极接触）提取电流至分布式解耦合器件。这种结构并不依赖于利用单点解耦合的去往板的中介常规封装管脚和焊料接点。接触漏极和源极接触，但是无需在常规集成电路器件中使用的那样通过常规顶层芯片金属化路由漏极和源极接触。而是，使用金属柱的栅格，其接触传导图案化引线框架，诸如在印刷电路板的上表面上在具有多个小的解耦合器件（例如解耦合电容器）的多个位置中形成的传导图案化引线框架。在印刷电路板下方在第三维中分布和放置解耦合器件。在印刷电路板的在半导体裸片之下的下表面上的传导图案化引线框架上放置解耦合器件。在印刷电路板的上表面上的传导图案化引线框架通过多个过孔耦合至在印刷电路板的下表面上的传导图案化引线框架。长的电传输线的影响因此通过使用多个分布式解耦合器件来解除，该多个 分布式解耦合器件经由引线框架和在金属柱栅格之下的过孔放置第三维中。备选地，可以与半导体裸片一起封装传导图案化引线框架并且随后将其置于印刷电路板上。 
利用下方凸块金属化方案的备选凸块结构将凸块放置在每个位置中。典型地使用沉积方法（诸如气相沉积焊料材料）形成凸块，或使用引线键合设备通过焊球凸出来形成凸块。这类制造工艺的制造牵连成本可能过于昂贵以至于不被视为实际，如Simon Tam在2008年3月14日提交的名称为“Transistor Circuit Formation Substrate”的美国专利No.7,989,963中描述的那样。如Tung于2002年6月12日提交的名称为“Pillar Connections for Semiconductor Chips and Method of Manufacture”的美国专利No.6,681,982、Hwee于2001年5月18日提交的名称为“Method for Forming Flip Chip Semiconductor Package”的美国专利No.6,510,976、Chew于2001年8月21日提交的名称为“Method for Forming Flip Chip on Leadframe Semiconductor Package”的美国专利No.6,550,666、Tung于2000年4月27日提交的名称为“Pillar Connections for Semiconductor Chips and Method of Manufacture”的美国专利No.6,578,754、Tung于2001年4月26日提交的名称为“Pillar Connections for Semiconductor Chips and Method of Manufacture”的美国专利No.6,592,019中描述的那样，在封装中使用柱以及它们去往引线框架的连接被更为广泛地设立，并且是更经济有效的制造工艺，在此基础之上可以实现对分布式路由问题的实际解决方案。这些专利中的每个专利通过引用并入本文。 
现在描述功率半导体器件的一个实施例。在一个方面，在功率半导体裸片外围上定位多个驱动器（例如栅极驱动器）以均衡栅极时序并且提供用于驱动器的低的栅极驱动阻抗。在金属带和半导体裸片上产生物理结构以改进重分布层（“RDL”）和开关输出电容Coss。形成诸如铝带之类的金属带并且将其定位成将栅极信号路由至单独的LDMOS单元以减少栅极电阻并且改进栅极驱动信号的时序的均衡。栅极驱动偏置电压“VDDG”总线和接地（“GND”或“PGND”）电轨吐出以减少栅极驱动电源阻抗。 
该结构使得栅极驱动信号能够在有效地相同时间到达LDMOS单元的相应栅极。用于栅极驱动偏置电压总线的解耦合器件以分布式方式被置于在半导体裸片正下方的路径中。结果是向沿形成为金属带的栅极驱动传输线传导的信号展现出低阻抗。 
在一个实施例中，用于栅极驱动信号的金属带在半导体裸片上从用于连接的外围延伸至其中央区域中的LDMOS单元。金属带用于从裸片外围到LDMOS单元的栅极驱动连接。金属柱形成为电镀金属（例如铜）柱以将定位于半导体裸片之下的外部解耦合器件耦合至半导体裸片上的点。在一个实施例中，至少一个解耦合器件位于半导体裸片的正下方。柱和解耦合器件耦合至用于栅极驱动信号的金属带之一的端部。在一个实施例中，形成封装以提供结构支撑和对金属柱的保护。 
现在参见图4，示出了半导体器件405的实施例的正视图，其显示了由金属柱（诸如伸长的铜柱或柱490）耦合至多个解耦合器件（例如解耦合或芯片电容器440、441）的倒转半导体裸片410。通过在需要解耦合的位置处（诸如在半导体裸片410的外围处的位置处）使用金属柱490和解耦合电容器440、441来实现局部解耦合。可以将一个或多个解耦合电容器440、441基本放置在对应柱490之下，位于半导体裸片410正上方或正下方，以减少电路路径电感。将解耦合器件（例如解耦合或芯片电容器445）放置在基本位于半导体裸片410下方的低电感区域450外（例如半导体裸片区域外的区域455中）产生较高的电感，其可以减小解耦合电容器445的性能。在低电感区域450中，解耦合电容器440、441完全位于半导体器件405的半导体裸片区域之下。金属柱490也可以用于耦合至在半导体裸片410的更为中央的区域中的LDMOS器件的LDMOS单元的高电流源极和漏极端子。 
在图4中，在半导体裸片410的顶部表面上喷涂光刻胶（例如半密耳（～12μm）光刻胶），并且蚀刻以形成在其中形成金属柱490的孔。然后去除光刻胶，从而保留悬置传导柱。在半导体裸片410上，首先沉积铝，然后是锡铜或闪速/种子层铜沉积和电镀。为了提 供机械稳定性，使用塑料495（例如诸如环氧树脂或聚酰亚胺之类的包封剂）包围金属柱490，其中每个金属柱490的端部暴露在塑料495的表面上。可以在聚酰亚胺层中形成并且从其延伸金属柱490。金属柱490接触在印刷电路板430的上表面上图形限定的传导图案化引线框架420的焊区。金属柱490回流焊接至传导图案化引线框架420。在印刷电路板430中构造过孔（例如其中之一标记为461）以提供将金属柱490耦合至在印刷电路板的下表面430上的传导图案化引线框架421以及解耦合电容器440、441、445的端子。解耦合电容器440、441、445与焊料凸块阵列（例如其中之一标记为463）回流焊接至印刷电路板430的下表面上的传导图案化引线框架421的焊区。焊区是传导图案化引线框架中小的几何结构，诸如环状区域，以回流焊接操作以附接部件。焊料凸块阵列（例如其中之一标记为462）定位于在印刷电路板430的上表面上的传导图案化引线框架420的焊区上。因此，解耦合电容器440、441、445置于距离半导体410的外围上的节点短竖直距离的焊区上，以产生对用于这些节点的局部电路接地的低的阻抗。金属柱490通过焊料凸块462耦合至传导图案化引线框架420。 
如图4中所示，在附接至印刷电路板430之前翻转半导体裸片410，并且因此在半导体裸片410下方的金属柱490提供与其“顶”侧的电接触。由于器件是高功率器件，在半导体裸片410的“下”表面上（经由粘合剂480）安装散热器470，其示出为在图4的顶部部分中在半导体裸片410之上，从而解耦合电容器440、441、445可以安装在在翻转的半导体裸片410的顶部侧之下的印刷电路板430上。散热器470因此接触半导体裸片410的下表面。相应地，金属柱490使得解耦合电容器440、441、445能够置于印刷电路板430上，紧密邻近半导体裸片410的顶部侧，并且过孔461形成为通过印刷电路板430以将半导体裸片410耦合至在印刷电路板430下方的解耦合电容器440、441、445的阵列。以此方式，为功率半导体器件405提供分布式解耦合功能。在一个实施例中，可以使用相同或不同引线框架以耦合至焊料凸块或柱和其它电路元件的栅格。示 例引线框架是6毫米(“mm”)x6mm。可以封装/包封（例如用环氧树脂）图4中所示的结构，并且可以将所得组件耦合至例如具有夹式（clip）电感器的引线框架，夹式电感器如Lotfi等人于2005年10月5日提交的名称为“Magnetic Device Having a Conductive Clip”的美国专利No.7,688,172中描述的那样，该申请的全文在此通过引用整体并入本文。 
因此，倒转的半导体（例如硅）裸片通过伸长的金属柱耦合至印刷布线或电路板的上表面，并且解耦合器件耦合至半导体裸片之下的印刷电路板的下表面。在一个实施例中，多个解耦合器件的至少一个耦合至在半导体裸片正下方的印刷电路板的下表面。通过使用这种结构，通过金属路径在半导体裸片和至少一个解耦合器件之间产生减少的电路阻抗。在经济有效的回流焊接工艺中可以容易地组装倒转的半导体裸片、印刷电路板和至少一个解耦合芯片器件。这种结构避免了对在半导体裸片结构的暴露表面上产生多个交替的、小占用面积的、金属源极和漏极焊盘（否则需要提供去往附接半导体裸片的印刷电路板的低电感连接）的需要，从而有助于印刷电路板的布局。备选地，如图所示和如下文所述，传导图案化引线框架420可以与半导体裸片410和金属柱490封装在封装的半导体器件内并且然后置于在其下具有解耦合电容器440、441、445的印刷电路板430上（例如参见针对封装的半导体器件的图18）。 
现在参见图5，示出了形成有周界环分布系统的半导体器件的实施例的平面图。N-LDMOS器件530和P-LDMOS器件531表示形成例如降压或升压dc-dc功率变换器的功率级的成对的LDMOS器件。如本文之前所述，每个LDMOS器件由大量单独的LDMOS单元形成。图5显示了在（功率半导体器件的）半导体裸片的外围上的N-LDMOS器件530和P-LDMOS器件531和驱动最终级，诸如N栅极驱动最终级510和P栅极驱动最终级520。常规设计运用用于位于半导体裸片的一端上的N栅极驱动最终级510的仅一个结构和用于P栅极驱动最终级520的仅一个结构。针对LDMOS器件530和P-LDMOS器件531中的每个在半导体裸片的外围周围分布多个驱动 最终级基本上改进耦合至单独的LDMOS单元的驱动信号的时序。在每个驱动最终级内是由级联缓冲器驱动的与N-MOS单元串联耦合的P-MOS单元的推拉输出电路（totem-pole）布置。并联电耦合驱动最终级。 
在构成每个LDMOS器件的大量（例如数千个）LDMOS单元中，控制或栅极端子上的栅极驱动信号应该基本同时地到达并且具有基本相同的幅度。使用电容器衰减栅极驱动信号的高频特性以改进相对同时性折衷了高频操作的效率。在设计中包括多个解耦合器件以为栅极驱动器的栅极驱动偏置电压VDDG总线提供低阻抗，而不减缓栅极驱动器。解耦合器件减少栅极驱动偏置电压VDDG总线的供应至分布式驱动器的阻抗。针对栅极驱动信号的一些传播延迟变化仍然保留，但是其最大部分已被分布式栅极驱动结构去除。 
现在参见图6，示出了形成为在半导体裸片上沉积的重分布层的实施例的平面图。重分布层（例如铜重分布层）跨半导体裸片的表面分布功率和接地节点、以及耦合至LDMOS单元的其它一些电路节点。也运用重分布层分布去往栅极驱动器的控制和监视信号。 
小圆环（标记为“SW”、“PGND”、“PVIN”等）是将LDMOS单元和其它电路节点耦合至前面关于图4描述的传导(例如铜)图案化引线框架420或下文关于图17D描述的引线框架1179的伸长的金属(例如铜)柱的位置。标记为“SW”(其中一个指示为610)的小圆环形成将P-LDMOS和N-LDMOS单元的漏极耦合在一起并且耦合至外部输出电感器（诸如图1中示出的输出电感器Lout）的电路节点。标记为“PVIN”(其中一个指示为620)的小圆环向形成高侧P-LDMOS器件的LDMOS单元的源极提供正偏置电压，并且标记为“PGND”(其中一个指示为630)的小圆环向形成低侧N-LDMOS器件的LDMOS单元的源极提供局部电路接地。在重分布层的外围处，标记为“VDDG”的小圆环(其中一个指示为640)将正偏置电压供应至驱动LDMOS单元的栅极的栅极驱动反相器(也称为“栅极驱动器”或“驱动器”)，并且标记为“PGND”的小圆环（其中一个指示为650）向栅极驱动反相器供应局部电路接地。 
现在参见图7，示出了图6中示出的重分布层具有显示N-LDMOS器件530和P-LDMOS器件531（参见图5）的轮廓叠置的平面图。此外，也显示了N栅极驱动最终级510和P栅极驱动最终级520的位置的轮廓。在一个实施例中，N-LDMOS器件530形成有220000个带，每个带代表约为20微米宽和沟道长度约为2-3微米的N-LDMOS单元。在一个实施例中，P-LDMOS器件531形成有约相同尺寸的120000个带。 
现在参见图8和图9，示出了图6中重分布层的放大平面图。在外围周围是用于驱动N-LDMOS和P-LDMOS单元的栅极的栅极驱动反相器的三个路径。路径800为栅极驱动反相器提供正的栅极驱动偏置电压VDDG，并且路径805为反相器提供局部电路接地。路径N_Drv810是由栅极驱动反相器产生的栅极驱动信号。路径N_Drv830在另一铜/金属层上并且电学上与路径N_Drv810共用。路径N_Drv830耦合至N-LDMOS单元的栅极。路径820在重分布层之下进一步金属化（例如20μm金属化），并且路径840代表耦合至N-LDMOS单元的栅极多晶硅层或带（一般称为“栅极”）的20μm金属化。图9示出了N-LDMOS单元的栅极多晶硅带910。应该理解，栅极可以由其它材料形成，诸如电传导的金属材料。 
现在参见图10，示出了NMOS反相器链的实施例的示意图，该NMOS反相器链配置成根据PWM信号SPWM产生用于N-LDMOS器件的图1中示出的大幅栅极驱动信号SDRV2。如图10中示出的偶数（例如4）序列的反相器根据低幅占空比信号SPWM产生大幅栅极驱动信号SDRV2。NMOS反相器链在图5和图7上标记为“N栅极驱动最终级”，并且在器件外围周围分布。 
反相器链的输出级由第一和第二反相器1010、1020的并联驱动布置形成。第一反相器由PMOS器件1011和NMOS器件1012形成。第二反相器1020由PMOS器件1021和NMOS器件1022形成。第一反相器1010由第三反相器1030驱动，第三反相器1030由较小的MOS器件（典型地为第一反相器1010中MOS器件的尺寸的三分之一）形成。类似地，第三反相器1030由第四反相器1040驱动，第 四反相器1040由约为第三反相器1030中MOS器件尺寸三分之一的MOS器件形成。以此方式，低电平输入信号（图1中示出的PWM信号SPWM）在由相继更大的MOS器件形成的级中相继地放大，以产生具有充足幅度以驱动图1中所示的辅助开关Qaux的图1中示出的栅极驱动信号SDRV2。 
可以使用偶数个反相器级构造与图10中所示的NMOS反相器链对应的PMOS反相器链，以根据低幅输入信号SPWM产生大幅、相同意义（same-sense）的栅极驱动信号。PMOS反相器链因此将在与NMOS反相器链互补的时间段操作，并且具有充足的时间分隔以避免在图1中示出的主开关Qmn和辅助开关Qaux的系列电路布置中的射穿电流。虽然将NMOS和PMOS反相器链描述为运用NMOS和PMOS器件，但是应该理解，可以使用N-LDMOS和P-LDMOS器件以获益。 
因此，如上文参考附图示出和描述的那样，已经简介了半导体器件及其形成方法。在一个实施例中，半导体器件包括：形成有多个LDMOS单元的半导体裸片，电耦合至多个LDMOS单元的重分布层、在重分布层之上分布并且电耦合至重分布层的多个金属柱（例如形成为电镀柱的铜柱），以及通过多个金属柱电耦合至重分布层的传导图案化引线框架。半导体器件还包括：耦合至重分布层并且通过重分布层电耦合至多个LDMOS单元的栅极的栅极驱动器。使用包封剂封装半导体器件，其中传导图案化引线框架的一些部分露出以用做半导体器件的外部接触。外部接触中的一些耦合至印刷电路板，并且外部接触中的一些耦合至多个解耦合器件（例如通过在印刷电路板的相对表面上的过孔）。多个解耦合器件中的至少一个位于半导体裸片之下。外部接触中的一些耦合至栅极驱动器，该栅极驱动器电耦合至重分布层并且通过重分布层电耦合至多个LDMOS单元的栅极，并且外部接触中的一些通过重分布层耦合至多个LDMOS单元的漏极或源极。 
现在参见图11，示出了半导体器件中体现的部分构造的N-LDMOS器件或其一些部分的实施例的简化三维图。根据半导体工 业中的标准实践，在该图和后续附图中的各种特征未按比例绘制。出于使本文论述的清楚性的目的，各种特征的尺度可以任意地增加或减少，并且相似参考数字可以用于构成半导体器件的不同器件的相似特征。 
在包括轻掺杂P衬底1105和在轻掺杂P衬底1105中注入的P阱1108的半导体裸片中形成N-LDMOS器件。P阱1108包括交替图案的掺杂源极区域“s”和漏极区域“d”，布局为P阱1108中的并行带或当未注入可选P阱1108时直接在轻掺杂P衬底1105上。源极金属（例如铝）带（其中一些指示为1111、1112）在基本上平面的第一金属层M1（例如铝）中形成，并且位于掺杂源极区域“s”之上并与其电接触，但是并不彼此电接触。对应地，漏极金属（例如铝）带也在第一金属层M1中形成并且位于掺杂漏极区域“d”之上并且与其电接触，但是漏极金属带并不彼此电接触。因此，多个交替的源极和漏极金属带在轻掺杂P衬底1105之上在第一金属层M1中形成，并且关于多个源极和漏极区域中相应源极和漏极区域平行并且形成电接触（例如通过硅化物层）。栅极氧化物带（其中之一指示为1140）将多晶硅栅极带（其中之一指示为1150）与下层的P阱1108或与当未注入可选的P阱1108时的轻掺杂P衬底1105隔离。因此，在轻掺杂P衬底1105之上在多个源极和漏极区域中的源极和漏极区域之间并且与其平行地形成多个栅极多晶硅带1150，多个栅极多晶硅带1150定向为与多个交替的源极和漏极金属带平行。图11中未示出在P阱1108或在轻掺杂P衬底1105中形成的位于源极区域“s”和掺杂漏极区域“d”之间并且将其分开的附加的和不同的掺杂带。第一金属层M1中的栅极金属（例如铝）带1130位于栅极多晶硅带1150之上，与其垂直对准并且与其电耦合。 
现在参见图12，示出了在形成基本平面的第二金属（例如铝）层M2之后的部分构造的N-LDMOS器件的一部分的简化三维图。在诸如位于第一金属层M1中形成的相应源极金属带1111、1112和漏极金属带1121、1122之上的源极金属（例如铝）带（其中之一指示为1160）和漏极金属（例如铝）带（其中之一指示为1161）之类的 带中形成第二金属层M2。氮氧化硅的隔离或绝缘层（例如参见图19）将第一金属层与第二金属层分开或电隔离。第二金属层M2中的位于第一金属层M1中的源极金属带1111、1112之上的源极金属带1160通过电传导过孔与其耦合。类似地，第二金属层M2层中的位于第一金属层M1中的漏极金属带1121、1122之上的漏极金属带1161通过电传导过孔与其耦合。因此，在第一金属层M1之上的第二金属层M2中形成第二多个交替的源极和漏极金属带，从而与第一多个交替的源极和漏极金属带叠置并平行。第一多个源极和漏极金属带通过过孔电耦合到相应的第二多个交替的源极和漏极金属带。第二金属层M2中的源极和漏极金属带1160、1161并不耦合到第一金属层M1中的与栅极多晶硅带1150相交并且与其电耦合的栅极金属带1130。 
现在参见图13，示出了在形成第二金属层M2之后的部分构造的一部分的简化平面图。图13示出了将第一金属层M1中的源极金属带1111、1112、1113、1114电耦合到第二金属层M2中的源极金属带1160、1162的过孔（其中之一指示为1175）。类似地，过孔（其中之一指示为1176）将第一金属层M1中的漏极金属带1121、1122、1123、1124电耦合到第二金属层M2中的漏极金属带1161、1163。过孔1175、1176穿透将第一金属层M1与第二金属层M2分开并且电隔离（绝缘）的隔离或绝缘层（例如参见图19中的绝缘层1915）。注意，在一个实施例中，过孔并不将第一金属层M1中的栅极金属带1130电耦合至第二金属层M2中的源极金属带1160、1162或漏极金属带1161、1163。 
现在参见图14，示出了在形成基本平面的第三金属（例如铝）层M3之后的部分构造的N-LDMOS器件的一部分的三维图。第三金属层M3叠置在第二金属层M2之上。图14示出了在第三金属层M3中形成的N-LDMOS器件源极接触1170和也在第三金属层M3中形成的N-LDMOS器件漏极接触1171。氮氧化硅的隔离或绝缘层将第二金属层与第三金属层分开和电隔离。N-LDMOS器件漏极接触1171与在相同裸片上P-LDMOS器件漏极接触共享（也称为 “N-LDMOS/P-LDMOS器件漏极接触”1171）。N-LDMOS器件源极接触1170通过过孔（例如图14中未显示的铝过孔）电耦合至第二金属层M2中的源极金属带（其中之一指示为1160）。N-LDMOS/P-LDMOS器件漏极接触1171通过过孔（例如图14中未显示的铝过孔）电耦合至第二金属层M2中的漏极金属带(其中之一指示为1161)。因此，在第三金属层M3中形成的源极和漏极接触通过过孔电耦合至第二金属层M2中的第二多个交替的源极和漏极金属带中一些，并且基本上覆盖多个源极和漏极区域。 
现在参见图15，示出了在形成第三金属层M3之后的部分构造的N-LDMOS器件的一部分的简化平面图。图15示出了将第三金属层M3中形成的N-LDMOS器件源极接触1170电耦合至第二金属层M2中形成的源极金属带1160、1162、1164的过孔（其中之一指示为1180）。此外，图15中示出了将第三金属层M3中形成的N-LDMOS/P-LDMOS器件漏极接触1171电耦合至第二金属层M2中形成的漏极金属带1161、1163、1165的过孔（其中之一指示为1181）。还显示了将第三金属层M3中形成的N-LDMOS/P-LDMOS器件漏极接触1171电耦合至第二金属层M2中形成的P-LDMOS器件漏极金属带1185、1187、1189的过孔（其中之一指示为1182）。P-LDMOS器件的第二金属层M2中的P-LDMOS源极金属带1184、1186、1188通过过孔电耦合至第三金属层M3中的P-LDMOS器件源极接触（图15中未示出）。过孔1180、1181、1182穿透将第二金属层M2与第三金属层M3分开并且电隔离（绝缘）的隔离或绝缘层（例如参见图19中的绝缘层1915）。此外，图15中还示出了第一金属层M1中的栅极金属带1130与栅极多晶硅带1150相交并且与其电耦合（参见图14）。 
现在参见图16，示出了包括N-LDMOS和P-LDMOS器件的部分构造的半导体器件的实施例的简化三维图，其示出了其第二金属层M2中的源极金属带和漏极金属带的几何结构。图16示出了在半导体裸片的外围处的耦合至诸如N-栅极驱动器1191和P-栅极驱动器1192之类的N-LDMOS和P-LDMOS器件的栅极驱动器。因此， 在半导体裸片的外围周围，N-LDMOS器件具有多个N-栅极驱动器（诸如N-栅极驱动器1191）并且P-LDMOS器件具有多个P-栅极驱动器（诸如P-栅极驱动器1192）。此外，图16中示出了在半导体裸片的外围处的逻辑电路元件，诸如逻辑电路元件1193。第二金属层M2上的金属化通过之前描述的过孔叠置在第一金属层M1上的相应金属化上并且与其电耦合。为了简明示出，在第二金属层M2下方的第一金属层M1的一部分在图16中未示出。此外，图16中还显示了第一金属层M1中的栅极金属带1130、1131，其与N-LDMOS和P-LDMOS器件的栅极多晶硅带（未显示）相交并且电耦合。出于与前面附图一致的目的，N-LDMOS器件的第二金属层M2中的源极金属带1160和漏极金属带1161以及P-LDMOS器件的第二金属层M2中的源极金属带1184和漏极金属带1185在图16中指示。 
现在参见图17，示出了包括N-LDMOS和P-LDMOS器件的部分构造的半导体器件的简化三维图，其示出了第三金属层M3中的源极和漏极接触（即传导区域）的几何结构。图17中示出了轻的P掺杂衬底1105，但是未示出其上部中的可选P阱。N-LDMOS/P-LDMOS器件漏极接触1171位于第三金属层M3中的N-LDMOS器件源极接触1170和P-LDMOS器件源极接触1172之间。图17也示出了位于半导体器件的外围处的在第三金属层M3中的栅极驱动器和逻辑电路元件接触（其中之一指示为1173）。 
现在参见图17A，示出了包括N-LDMOS和P-LDMOS器件的部分构造的半导体器件的三维图，其示出了用于重分布层（例如铜重分布层）的过孔（例如铜过孔，其中之一指示为1174）的几何结构。铜过孔1174提供在第三金属层M3和重分布层之间的电接触。铜过孔1174穿透将第三金属层M3与重分布层分开和电隔离（绝缘）的隔离或绝缘层（例如参见图19中的聚酰亚胺层1935）。 
现在参见图17B，示出了包括N-LDMOS和P-LDMOS器件的部分构造的半导体器件的简化三维图，其示出了重分布层（例如铜重分布层）1177的几何结构。重分布层1177显示为在第三金属层M3上的相应金属化之上的图案化，并且通过铜过孔1174（参加图17A） 电耦合至第三金属层M3上的金属化。同样地，重分布层1177由隔离或绝缘层（参见图19）与第三金属层M3分开。 
现在参见图17C，示出了包括N-LDMOS和P-LDMOS器件的部分构造的半导体器件的简化三维图，其示出了用于重分布层1177的柱（例如铜柱，其中之一指示为1178）的几何结构。铜柱1178提供在重分布层1177和传导图案化引线框架之间的电接触。 
现在参见图17D，示出了包括N-LDMOS和P-LDMOS器件的部分构造的半导体器件的简化三维图，其示出了传导图案化引线框架1179的几何结构。传导图案化引线框架1179显示为在重分布层1177之上的图案化并且通过铜柱1178（参见图17C）电耦合至重分布层1177。 
现在参见图18，示出了包括N-LDMOS和P-LDMOS器件的封装半导体器件（具有诸如环氧树脂之类的包封剂）的实施例的三维外视图。引线框架1179的一部分（参见图17D）露出以用作半导体器件的外部接触。外部N-LDMOS/P-LDMOS器件漏极接触1194位于外部N-LDMOS器件源极接触1195和外部P-LDMOS器件源极接触1196之间，并且外部栅极驱动器和逻辑电路接触元件（其中之一指示为1197）位于半导体器件的外围周围。实施例中国可运用的封装材料是诸如环氧树脂之类的包封剂，但是在本发明的广义范围内构思了其它封装材料（包括具有增强热特性的封装材料）。半导体器件的外部电接触表面可以涂覆有铜闪速/种子（flash/seed）层，并且然后使用铜电镀，以形成容易焊接的金属表面。外部表面也可以使用薄层的金或其它惰性金属或合金电镀，以提供用于焊接或其它附接工艺的进一步水平的钝化。如关于图4示出和描述的那样，图18的封装半导体器件可以置于印刷电路板上邻近解耦合器件，以提供上述优势。 
现在参见图19，示出了包括N-LDMOS和/或P-LDMOS器件的半导体器件的实施例的正视图。在包括位于轻掺杂衬底1905之上的阱1910而掺杂源极区域“s”和漏极区域“d”位于其中的半导体裸片中形成N-LDMOS和/或P-LDMOS器件。第一、第二和第三金属层 M1、M2、M3由氮氧化硅层（总体指示为1915）分开并且彼此隔离，并且位于掺杂源极区域“s”和掺杂漏极区域“d”之上并且与其电接触。过孔（其中之一指示为1920）提供在第一和第二金属层M1、M2之上的金属化之间的电接触。过孔（其中之一指示为1925）提供在第二和第三金属层M2、M3之上的金属化之间的电接触。在第一聚酰亚胺层1935中形成铜过孔（其中之一指示为1930）以提供在第三金属层M3和形成于聚酰亚胺层1935之上的第一铜重分布层1940之间的电接触。在第二聚酰亚胺层1950中形成铜柱（其中之一指示为1945）以提供在铜重分布层1940和在第二聚酰亚胺层1950之上形成的铜引线框架1955之间的电接触。应该理解，用于相应层的具体材料仅是示例，并且可以运用具有相似属性的其它材料以获益。 
因此，如上面参考所附附图示出和描述的那样，简介了半导体器件及其形成方法。在一个实施例中，半导体器件包括：半导体裸片，形成有多个LDMOS单元；金属层（例如形成重分布层的多个铜层)，电耦合至多个LDMOS单元；以及栅极驱动器（例如包括形成为MOS器件的驱动器开关的栅极驱动器之一），沿半导体裸片的外围定位，并且通过金属层电耦合至多个LDMOS单元的栅极。运用金属层以将栅极驱动器中的一些耦合至栅极驱动偏置电压以及控制和监视信号。半导体器件也包括：多个金属柱，在金属层之上分布并且与其电耦合；以及传导图案化引线框架，电耦合至多个金属柱。半导体器件由包封剂封装，其中露出传导图案化引线框架的一些部分以用作半导体器件的外部接触。外部接触中的一些通过在印刷电路板的相对表面上的过孔耦合至多个解耦合器件。外部接触中的一些耦合至栅极驱动器，并且外部接触中的一些通过金属层耦合至多个LDMOS单元的漏极或源极。 
现在参见图20，示出了在半导体器件中体现的N-LDMOS器件或其一些部分的截面图。虽然关于图20简介了N-LDMOS器件的一些层，但是将关于图21以及后续图描述用于构造层的工艺的更具体说明。在包括P掺杂半导体衬底（也称为“衬底”）2005的半导体 裸片中形成N-LDMOS器件，并且在其表面上，可以生长可选的外延层（例如未示出的轻掺杂P型外延层）。虽然在示出的实施例中，衬底2005是P型衬底，但是本领域技术人员可以理解，衬底2005可以是N型衬底而不偏离本发明的范围。 
N-LDMOS器件由多个N-LDMOS单元（诸如图20中所示的N-LDMOS单元2001）形成。N-LDMOS器件包括P型阱2015和在P型阱2015之上形成的重掺杂P型区域2090。重掺杂N型区域2060、2080形成于重掺杂P型区域2090的任一侧上或者上方。重掺杂N型区域2060形成有比重掺杂N型区域2080低的掺杂浓度，尤其是在远离重掺杂N型区域2080的横向方向上。重掺杂N型区域2060、2080通过形成于其之上的硅化物层2115提供欧姆结。硅化物层2115在重掺杂N型区域2060、2080和第一金属（例如铝）层M1之间提供重传导结以最终提供用于N-LDMOS器件的源极接触（指定为“接合源极（接触）”）。位于重掺杂P型区域2090之上的重掺杂N型区域2080是薄的（例如约10至100
Figure BDA0000424085820000281
），使得由此在重掺杂N型区域2080和重掺杂P型区域2090之间形成的所得P-N结将是在两个方向上高传导的欧姆结。因此，形成于其之间的P-N结将不可作为二极管操作，硅化物层2115在重掺杂N型区域2080和第一金属层M1之间提供重传导结以最终提供用于N-LDMOS器件的漏极接触（指定为“接合漏极（接触）”）。用于源极和漏极的第一金属层M1由绝缘层（诸如非晶态氮氧化硅（“SixOyNz”））层2120分离。 
P型区域2055在P型阱2015内与重掺杂N型区域2060和重掺杂P型区域2090相邻形成。沟道区域2003在重掺杂N型区域2060和轻掺杂N型区域2070之间形成于栅极之下。P型区域2055通过在栅极之下以偏离竖直方向一定角度的离子注入形成于P型阱2015中，该栅极将形成于沟道区域2003上方并且用来控制N-LDMOS器件的阈值电压。 
栅极形成有栅极多晶硅层2025，在栅极多晶硅层2025附近具有下层和上层栅极氧化物层2020、2030和侧壁间隔物（其中之一被 指定为2040）。沟道区域2003上方的栅极多晶硅层2025控制其中的传导性水平。下层栅极氧化物层2020在栅极多晶硅层2025与P型阱2015和P型区域2055之间形成隔离层。在栅极多晶硅层2025之上去除上层栅极氧化物层2030的一部分并且在其之上形成硅化物层2115以减小栅极电阻。 
因此，栅极多晶硅层2025（具有硅化物层2115）跨N-LDMOS器件的许多N-LDMOS单元形成栅极多晶硅带1150并且耦合至第一金属层M1中的栅极金属带1130（参见例如图11）。栅极金属带1130被路由至位于半导体器件的外围处的多个栅极驱动器（参见例如图16）。去往N-LDMOS单元的栅极的基本上时间对准的切换信号由此通过将第一金属层M1中的栅极金属带1130耦合至多个栅极驱动器来启动，该第一金属层M1中的栅极金属带1130具有基本上比栅极多晶硅带1150更大的电传导性。 
鉴于在栅极与源极和漏极之间产生的大有效电容，向单独N-LDMOS单元的多个栅极提供时间对准的切换信号是重要的设计考虑，该大有效电容要求大栅极驱动电流来实现快速切换转换。未能产生去往单独N-LDMOS单元的栅极的时间对准的栅极驱动信号可以使得一些N-LDMOS单元在其它N-LDMOS单元之前接通，这迫使在前切换的单元在时间未对准的切换转换期间传导高电流脉冲。时间未对准的高电流脉冲使N-LDMOS单元面临器件失效。 
所示结构也使得N-LDMOS和P-LDMOS器件能够在公共半导体裸片中形成有基本上相同结构，并且使得每个LDMOS类型能够与去往外部电路的低电感、高电流路径耦合。每个LDMOS形成有单个大的源极接触，并且两个LDMOS形成有单个大的并且共享的漏极接触（参见例如图17），这可以简化电路板布局以及去往外部电路的附接问题。大的源极和漏极接触容易用与大的源极和漏极接触基本上相同覆盖面积（footprint）的铜重分布层覆盖（参见例如图17B），并且最终用引线框架（参见例如图17D）覆盖，这提供传导性的进一步改进以及将封装半导体器件（参见例如图18）耦合至外 部电路。源极接触和共享的漏极接触接触基本上覆盖N-LDMOS和P-LDMOS器件的整个有源区域，很小的裸片区域被并不覆盖有源切换区域的高电流接触浪费。 
关于N-LDMOS单元2001，源极（或者源极区域）在至少重掺杂N型区域2060中被体现，并且漏极（或者漏极区域）在轻掺杂N型区域2070（例如轻掺杂漏极（“LDD”）区域）以及相邻的与沟道区域2003相对的重掺杂N型区域2080中被体现。栅极利用这里所引入的层居于沟道区域2003上方。LDD区域相对于常规设计提供用于N-LDMOS器件的更高击穿电压。这些区域以“重掺杂源极区域”、“栅极”、“轻掺杂漏极区域”和“重掺杂漏极区域”的顺序形成。在参照图88所描述的P-LDMOS器件以及下列P-LDMOS器件中采用相似结构。 
现在转到图21至87，图示形成在半导体器件中体现的N-LDMOS器件或者其部分的实施例的截面图。开始为图21，N-LDMOS器件形成于包括P掺杂半导体衬底（也被称作“衬底”）2005的半导体裸片中，并且在其表面上可以生长可选外延层（例如轻掺杂P型外延层，未示出）。衬底2005优选在约1·1014和1·1016原子/cm3之间（例如利用硼）轻掺杂。可能不需要在衬底2005上生长的选择外延层，特别是如果衬底2005是轻掺杂P型衬底。尽管在所示实施例中，衬底2005是P型衬底，本领域技术人员理解衬底2005可以是N型衬底而未背离本发明的范围。 
衬底2005形成有隔离区域（例如浅沟槽隔离区域2010）。浅沟槽隔离区域2010也可以形成于衬底内或者形成于在其上生长的外延层内，以在实施于衬底上或者外延层上的器件之间提供电介质隔离。浅沟槽隔离区域2010通过用光刻胶涂敷、图案化和蚀刻衬底2005来限定其中的相应区域。示例光刻胶是AZ电子材料光刻胶。随后利用电介质（诸如二氧化硅、氮化硅其组合或者其它合适的电介质材料）蚀刻和回填浅沟槽隔离区域2010。随后通过研磨工艺（诸如化学机械平坦化（“CMP”）研磨工艺）平坦化衬底2005的外延 层和浅沟槽隔离区域2010来平坦化器件，而限制对裸片的表面损坏。利用电介质的掩蔽、蚀刻、回填步骤以及研磨步骤在本领域中是众所周知的，并且在下文中将不再具体描述。 
浅沟槽隔离区域2010将P型衬底2005划分成电介质分离区域以在所示实施例中容纳多个N-LDMOS和P-LDMOS器件以及在位于其上的控制电路中体现的作为低压器件操作的栅极驱动器和其它PMOS和NMOS器件。低压器件例如在功率变换器的控制器内（例如在可以在半导体器件的衬底上形成的控制和信号处理器件内）可操作。此外，P型衬底2005可以容纳例如在功率传动装置以及功率变换器的驱动器（即功率开关和驱动器开关）中作为较高压器件操作的N-LDMOS和P-LDMOS器件。 
现在转到图22，通过涂敷和图案化光刻胶掩膜（未示出）、随后通过蚀刻光刻胶掩膜以限定由P型阱2015占据的区域来形成P型阱2015。通过对适当P型掺杂剂种类（诸如硼）的离子注入工艺（例如以约100至300千电子伏（“keV”）的受控能量）形成P型阱2015，并且致使掺杂浓度分布优选在约1·1017至2·1019原子/cm3的范围内。 
现在转到图23，栅极氧化物层2020（绝缘层）形成于半导体器件的表面之上，厚度符合栅极的期望操作电压。栅极氧化物层2020通常为例如通过将在其上正在形成硅器件的晶片放置在炉中并且使晶片的暴露表面与氧或者其它合适材料在500至900℃反应10至100分钟（以便产生高k（介电常数）堆叠）而形成的二氧化硅，对于采用约0.25微米（“μm”）特征尺寸并且操作于低栅极电压（例如2.5伏）的器件而言具有约30至50埃（“
Figure BDA0000424085820000311
”）的厚度。假设将N-LDMOS和P-LDMOS器件的栅极到源极电压限制限制到（例如约2.5伏的）电压，那么栅极氧化物层2020可以形成有以上提出的栅极电介质层厚度。优选地，栅极氧化物层2020被构造为具有均匀厚度以提供近似2.5伏的对于器件额定的栅极到源极电压，其使器件的正向传导属性完全或者接近完全饱和。当然，用于器件的前述栅极电压范围仅 出于示例目的而提供，并且在本发明的宽范围内可以预期其它电压范围。 
现在转到图24，栅极多晶硅层2025沉积于栅极氧化物层2020之上并且在后续处理步骤中使用具有在约1·1019至5·1020的范围内的掺杂浓度的适当掺杂种类（诸如砷）进行N型（或者P型）掺杂以获得合适水平的传导性。栅极多晶硅层2025在炉中以提高的温度（例如在800至1000摄氏度（“℃”）进行2至60分钟）进行退火以适当扩散并且激活掺杂剂。栅极多晶硅层2025可以具有可以范围从约100至500纳米的厚度范围，但是也可以根据应用甚至更小或者更大。 
现在转到图25，通过将在其上正在形成硅器件的晶片放置在炉中并且使栅极多晶硅层2025的暴露表面与氧在提升的温度（例如在500至900℃进行1至60分钟）反应而在栅极多晶硅层2025的上表面之上形成上层栅极氧化物层2030（绝缘层）。上层栅极氧化物层2030可以形成有约50至500
Figure BDA0000424085820000321
的厚度。 
现在转到图26，图案化并且蚀刻栅极氧化物层2020、栅极多晶硅层2025和上层栅极氧化物层2030以因此限定并且形成水平尺度。利用蚀刻采用光刻胶掩膜来限定栅极多晶硅层2025以及栅极氧化物层2020和上层栅极氧化物层2030的横向尺度。在以下图中仅利用用于栅极多晶硅层2025和栅极氧化物层2020、2030的参考标号指定栅极之一。示例光刻胶是AZ电子材料光刻胶。图案化和蚀刻以限定并且形成栅极多晶硅层2025以及栅极氧化物层2020、2030的水平尺度的步骤在本领域中是众所周知的，并且在下文中将不再进一步详述。在备选实施例中，栅极多晶硅层2025可以包括并且另外可以形成有宽范围的材料，包括各种材料、其它掺杂半导体或者其它传导材料。注意到可以在相同处理步骤中掩蔽和蚀刻栅极多晶硅层2025和栅极氧化物层2020、2030的水平尺度以及用于形成于相同硅上的N-LDMOS和P-LDMOS器件二者的多个其它结构。 
现在转到图27，已经在半导体器件之上沉积上层氮化硅 （Si3N4）层2035。在半导体器件之上沉积上层氮化硅层2035在本领域中是众所周知的，并且在下文中将不再进一步详述。 
现在转到图28，除了氮化硅层2035的与由栅极多晶硅层2025以及下层和上层氧化物层2020、2030形成的侧壁相邻的竖直厚部分之外几乎在任何地方回蚀上层氮化硅层2035。以这一方式，在自对准工艺中，从与栅极多晶硅层2025以及下层和上层氧化物层2020、2030相邻的氮化硅层2035形成侧壁间隔物（其中之一指定为2040），而无需掩蔽和蚀刻光刻胶。 
现在转到图29，已经涂敷、图案化和蚀刻光刻胶2045以限定用于N-LDMOS器件的源极区域，从而使得P型离子（诸如硼离子）在后续处理步骤中能够被注入到半导体器件的选择的区域中。蚀刻光刻胶以暴露一半栅极宽度，其约为0.2μm（指定为2050）以在图案化和蚀刻光刻胶时适应公差问题。因此，使用本领域中众所周知的技术通过光刻胶掩膜控制P型离子注入的横向位置。涂敷、图案化和蚀刻光刻胶的步骤在本领域中是众所周知的，并且在下文中将不再进一步详述。 
现在转到图30，已经（例如以约20至100keV的受控能量约5·1017至1·1019原子/cm3）注入P型离子以形成P型区域2055。P型区域2055利用合适的原子种类（诸如硼）进行离子注入以实现用于正在形成的N-LDMOS器件的可用栅极阈值电压。 
现在转到图31，已经注入N型离子（例如砷）以形成重掺杂N型区域2060。重掺杂N型区域2060（例如以约5至50keV的受控能量）利用优选在5·1018至1·1020原子/cm3的范围内的掺杂浓度分布进行注入以实现用于正在形成的N-LDMOS器件的低源极电阻。如图32中所示在剥离光刻胶2045之后，（例如在炉中以700至1000℃进行1至60分钟）对半导体器件进行退火以将P型区域2055和重掺杂N型区域2060转变成有源衬底位置。 
现在转到图33，涂敷、图案化和蚀刻光刻胶2065，使得在后续处理步骤可以在由栅极多晶硅层2025以及下层和上层氧化物层 2020、2030形成的栅极之间的区域中选择性地注入N型离子。如图34中所示，在栅极之间注入N型离子（例如砷离子）以形成轻掺杂N型区域2070。在一个实施例中，轻掺杂N型区域2070的离子浓度优选在1·1017至1·1019原子/cm3的范围内，并且以10至200keV的受控能量进行注入。 
如图35中所示，在剥离光刻胶2065之后，在炉中对半导体器件进行退火以将轻掺杂N型区域2070转变成有源衬底位置（例如在700至1000℃的温度进行1-60分钟）。现在转到图36，涂敷、图案化和蚀刻光刻胶2075，以用于在由栅极多晶硅层2025以及下层和上层氧化物层2020、2030形成的栅极之间的区域中后续选择性注入离子。 
现在转到图37，对半导体器件注入重掺杂N型区域2080。在一个实施例中，例如利用砷将重掺杂N型区域2080掺杂至在约1·1019至5·1020原子/cm3的范围内的浓度，并且以10至100keV的受控能量进行注入。同时，用约1·1019至5·1020原子/cm3的掺杂浓度利用砷类似地N型掺杂栅极多晶硅层2025，以获得合适的栅极传导性水平。如图38中所示，在剥离光刻胶2075之后，在炉中（例如以700至1000℃的温度进行1至60分钟）对半导体器件进行退火以将重掺杂N型区域2080转变成有源衬底位置。 
现在转到图39，涂敷、图案化和蚀刻光刻胶2085，用于在N-LDMOS器件的源极和漏极区域之间在后续步骤中在选择的区域中后续选择性注入P型离子。如图40中所示，利用例如离子注入硼形成重掺杂P型区域2090。在一个实施例中，重掺杂P型区域2090被掺杂至约1·1019至5·1020原子/cm3的浓度，并且以5至50keV的受控能量进行注入。如图41中所示，在剥离光刻胶2085之后，在炉中（例如以700至1000℃的温度进行1至60分钟）对半导体器件进行退火以将重掺杂P型区域2090转变成有源衬底位置。在重掺杂P型区域2090上方的重掺杂N型区域2080相对地薄（例如约10至100
Figure BDA0000424085820000341
）。 
现在转到图42，在室中利用氧和硅源气体在半导体器件的衬底上以550至900℃进行30至90分钟来形成低温二氧化硅（SiO2）层2095。为了避免硅化物化表面上的N型区域，沉积低温二氧化硅层2095，并且随后涂敷和处理光刻胶以限定具有自对准区块（SAB，自对准硅化物/自对准多晶硅化物区块）的区域，其中将形成硅化物。硅化物仅形成于暴露的硅上。在其中硅被SiO2层覆盖的区域中，将不形成硅化物层。 
现在转到图43，图案化和蚀刻光刻胶2100以使得硅化物区域形成于半导体器件的选择的区域（示出一半栅极宽度2050用于后续处理）之上。如图44所示，在蚀刻低温二氧化硅层2095之后，留下二氧化硅区域2105。如图44中所示，也部分地去除了上层栅极氧化物层2030。如图45所示，在半导体器件的表面之上涂敷不反应的难熔金属2110。示例难熔金属包括钨、钛和钴。利用低温烘焙（例如以400至550℃的温度进行1至20分钟）、随后进行高温退火（例如以600至800℃的温度进行1至20分钟）在暴露的硅和多晶硅表面之上形成硅化物（例如优选在100-800
Figure BDA0000424085820000351
的范围内的厚度）以减小硅化物薄层电阻。 
现在转到图46，利用湿法蚀刻对不反应的难熔金属2110进行蚀刻，从而留下硅化物层2115。硅化物层2115的形成于硅和多晶硅的暴露区域之上的部分基本上不与湿法蚀刻反应，并且未被湿法蚀刻去除。示例湿法蚀刻是王水，王水是硝酸和盐酸的混合物。在一个实施例中，覆盖在栅极多晶硅层2025上面的硅化物层2115电耦合至参照图11以及下文讨论的形成于第一金属层M1中的栅极金属带1130。 
现在转到图47，采用等离子体沉积工艺在半导体器件的表面之上沉积非晶态氮氧化硅（SixOyNz）层2120（绝缘层）。采用等离子体沉积工艺形成非晶态氮氧化硅层2120在本领域中是众所周知的，并且在下文中将不再详述。如图48中所示，在氮氧化硅层2120之上沉积光刻胶层2125。图案化和蚀刻光刻胶层2125以在后续处理 步骤中暴露硅化物层2115的部分。 
现在转到图49，利用合适的蚀刻（诸如反应离子蚀刻（RIE））对氮氧化硅层2120进行蚀刻以暴露硅化物层2115的一部分。如图50中所示，剥离光刻胶层2125的剩余部分。如图51中所示，随后在半导体器件的表面之上真空沉积第一金属（例如铝）层M1。现在转到图52，在第一金属层M1之上沉积蚀刻停止难熔层2130。在一个实施例中，蚀刻停止难熔层2130是氮化钛、氮化钴或者氮化钨。用于在铝层之上沉积蚀刻停止难熔层的工艺在本领域中是众所周知的，并且在下文中将不再详述。如图53中所示，在半导体器件之上沉积光刻胶层2135，随后图案化和蚀刻光刻胶层2135以覆盖第一金属层M1的将被保留的区域。随后，如图54中所示，利用合适的蚀刻（诸如RIE）去除蚀刻停止难熔层2130的暴露区域和第一金属层M1的暴露区域。此外，如图55中所示，剥离光刻胶层2135的剩余部分，由此暴露蚀刻停止难熔层2130和氮氧化硅层2120的剩余部分。 
现在转到图56，在半导体器件之上沉积另一氮氧化硅层2140（绝缘层），并且通过化学机械平坦化进行平坦化。如图57中所示，在氮氧化硅层2140之上沉积和图案化光刻胶层2145，以使得在处理步骤序列中能够形成用于N-LDMOS的低电阻金属源极和漏极接触。随后，如图58中所示，向下蚀刻氮氧化硅层2140至蚀刻停止难熔层2130。示例氮氧化硅蚀刻剂装置在感应耦合等离子体蚀刻装置中采用六氟乙烷（C2F6）气体。 
现在转到图59，剥离光刻胶层2145。随后，如图60所示，在半导体器件的表面之上真空沉积第二金属（例如铝）层M2。如图61所示，在第二金属层M2之上沉积蚀刻停止难熔层2150。在一个实施例中，蚀刻停止难熔层2130是氮化钛、氮化钴或者氮化钨。如图62中所示，在蚀刻停止难熔层2150之上之上沉积和图案化光刻胶层2155以覆盖第二金属层M2的将被保留的区域。随后，如图63所示，利用合适的蚀刻（诸如RIE）去除蚀刻停止难熔层2150的暴 露区域和第二金属层M2的暴露区域。此外，如图64中所示，剥离光刻胶层2155的剩余部分，由此暴露蚀刻停止难熔层2150和氮氧化硅层2140的剩余部分。 
现在转到图65，在半导体器件之上沉积另一氮氧化硅层2160（绝缘层），并且通过化学机械平坦化进行平坦化。如图66中所示，在氮氧化硅层2160之上沉积和图案化光刻胶层2165，以覆盖氮氧化硅层2160的将被保留的区域。图67示出在向下蚀刻氮氧化硅层2160至蚀刻停止难熔层2150之后部分完成的半导体器件。随后，如图68所示，剥离光刻胶层2165。 
现在转到图69，随后在半导体器件的表面之上真空沉积第三金属（例如铝）层M3。如图70所示，沉积和图案化光刻胶层2165以覆盖第三金属层M3的将被保留的区域。随后，如图71所示，利用合适的蚀刻（诸如RIE）去除第二金属层M3的暴露区域。此外，如图72所示，剥离光刻胶层2165的剩余部分，由此暴露第三金属层M3和氮氧化硅层2160的剩余部分。 
现在转到图73，在半导体器件之上沉积最终氮氧化硅层2170（绝缘层）并且通过化学机械平坦化进行平坦化。如图74中所示，在氮氧化硅层2170之上沉积和图案化光刻胶层2175以覆盖将被保留的区域。随后，如图75中所示，利用合适的蚀刻（诸如RIE）去除氮氧化硅层2170的暴漏区域，由此暴露第三金属层M3的剩余部分。此外，如图76中所示，剥离光刻胶层2175的剩余部分，由此暴露氮氧化硅层2170的剩余部分。 
现在转到图77，在半导体器件之上沉积聚酰亚胺涂层2180（绝缘层）。如图78中所示，在聚酰亚胺涂层2180之上沉积和图案化光刻胶层2185以覆盖第三金属层M3的在N-LDMOS器件的漏极之上的区域。随后，如图79中所示，利用合适的蚀刻去除聚酰亚胺涂层2180的暴露区域，由此暴露第三金属层M3的在N-LDMOS器件的源极上方的剩余部分。此外，剥离光刻胶层2185的剩余部分，由此暴露聚酰亚胺涂层2180的剩余部分。 
现在转到图80，在半导体器件之上沉积难熔阻挡层2190（例如氮化钛、氮化钽或者氮化钴）。如图81中所示，随后在难熔阻挡层2190之上沉积薄金属（例如铜）种子层2195。如图82所示，随后电镀铜种子层2195以形成电镀的铜层2200。随后，如图83所示，在铜层2200之上沉积另一聚酰亚胺涂层2205（绝缘层）。 
现在转到图84，随后在聚酰亚胺涂层2205之上沉积和图案化光刻胶层2210。蚀刻光刻胶层2210并且蚀刻下层聚酰亚胺涂层2205以暴露在N-LDMOS器件的源极之上的下层铜层2200。随后，在半导体器件之上沉积另一薄金属（例如铜）种子层2215。沉积铜种子层2215是可选步骤，以产生用于后续电沉积金属（例如铜）柱的新鲜表面。随后，如图86中所示，从半导体器件去掉光刻胶层2210以及铜种子层2215的覆盖在光刻胶层2210上面的部分。 
现在转到图87，采用酸溶液通过电镀工艺形成金属（例如铜）柱2220。铜柱2220用作去往传导图案化引线框架的低电阻源极接触，完成的半导体器件的端子可焊接地附接该图案化引线框架的迹线，如在上文中参照图4所示和描述的那样。可以根据上文描述的用于构建源极接触的步骤采用对应的步骤来形成用于N-LDMOS器件的低电阻漏极接触。此外，可以选择性地在铜柱2200和放置于其上的图案化引线框架2230之间沉积包封剂（例如环氧树脂）2225，以创建用于封装的半导体器件的外部接触（例如参见图18）。 
转到图88，示出在半导体器件中体现的P-LDMOS器件或者其部分的实施例的截面图。虽然将参照图88介绍P-LDMOS的一些层，但是将参照图89描述这些层的更具体解释。此外，由于构造包括P-LDMOS器件的半导体器件的许多处理步骤与构造上文提到的包括N-LDMOS器件的半导体器件的处理步骤类似，所以以下讨论将限于形成P-LDMOS器件的层。 
P-LDMOS器件形成于包括P掺杂半导体衬底（也被称作衬底）8005的半导体裸片中以及其表面上，可以生长可选外延层（例如轻掺杂P型外延层，未示出）。尽管在所示实施例中衬底8005是P型 衬底，但是本领域技术人员将理解衬底8006可以是N型衬底而未背离本发明的范围。 
P-LDMOS由多个P-LDMOS单元形成，诸如图88中所示的P-LDMOS单元8001。P-LDMOS器件包括在其上形成有N型阱8017的轻掺杂N型阱8015。在N型阱8017内是形成于其中的重掺杂N型区域8090。重掺杂P型区域8060、8080形成于重掺杂N型区域8090的任一侧上或者上方。重掺杂P型区域8060形成有重掺杂P型区域8080低的掺杂浓度，尤其是在远离重掺杂P型区域8080的横向方向上。重掺杂P型区域8060、8080通过形成于其之上的硅化物层8115提供欧姆结。硅化物层8115在重掺杂P型区域8060、8080和第一金属（例如铝）层M1之间提供重传导结以最终提供用于P-LDMOS器件的源极接触（指定为“接合源极（接触）”）。位于重掺杂N型区域8090之上的重掺杂P型区域8080是薄的（例如约10至100
Figure BDA0000424085820000391
），使得由此在重掺杂P型区域8080和重掺杂N型区域8090之间形成的所得P-N结将是在两个方向上高传导的欧姆结。因此，形成于其之间的P-N结将不可作为二极管操作，硅化物层8115在重掺杂P型区域8080和第一金属层M1之间提供重传导结以最终提供用于P-LDMOS器件的漏极接触（指定为“接合漏极（接触）”）。用于源极和漏极的第一金属层M1由绝缘层（诸如非晶态氮氧化硅（“SixOyNz”））层8120分离。 
N型区域8055在N型阱8017内与重掺杂P型区域2060和重掺杂N型区域8090相邻形成。沟道区域8003在重掺杂P型区域8060和轻掺杂P型区域8070之间形成于栅极之下。N型区域8055通过在栅极之下以偏离竖直方向的一定角度离子注入形成于N型阱8017中，该栅极将形成于沟道区域8003上方并且用来控制P-LDMOS器件的阈值电压。 
栅极形成有栅极多晶硅层8025，在栅极多晶硅层8025附近具有下层和上层栅极氧化物层8020、8030和侧壁间隔物（其中之一被指定为8040）。沟道区域8003上方的栅极多晶硅层8025控制其中 的传导性水平。下层栅极氧化物层8020在栅极多晶硅层8025与N型阱8017和N型区域8055之间形成隔离层。在栅极多晶硅层8025之上去除上层栅极氧化物层8030的一部分，并且在其之上形成硅化物层8115以减小栅极电阻。 
因此，栅极多晶硅层8025（具有硅化物层8115）跨P-LDMOS器件的许多P-LDMOS单元形成栅极多晶硅带并且耦合至第一金属层M1中的栅极金属带1131（参见例如图16）。栅极金属带1131被路由至位于半导体器件的外围处的多个栅极驱动器（参见例如图16）。去往P-LDMOS单元的栅极的基本上时间对准的切换信号由此通过将第一金属层M1中的栅极金属带1131耦合至多个栅极驱动器来启动，该第一金属层M1中的栅极金属带1131具有基本上比栅极多晶硅带更大的电传导性。 
鉴于在栅极与源极和漏极之间产生的大有效电容，向单独P-LDMOS单元的多个栅极提供时间对准的切换信号是重要的设计考虑，该大有效电容要求大栅极驱动电流来实现快速切换转换。未能产生去往单独P-LDMOS单元的栅极的时间对准的栅极驱动信号可以使得一些P-LDMOS单元在其它P-LDMOS单元之前接通，这迫使在前切换的单元在时间未对准的切换转换期间传导高电流脉冲。时间未对准的高电流脉冲使P-LDMOS单元面临器件失效。 
所示结构也使得N-LDMOS和P-LDMOS器件能够在公共半导体裸片中形成有基本上相同结构，并且使得每个LDMOS类型能够与去往外部电路的低电感、高电流路径耦合。每个LDMOS形成有单个大的源极接触，并且两个LDMOS形成有单个大的并且共享的漏极接触（参见例如图17），这可以简化电路板布局以及去往外部电路的附接问题。大的源极和漏极接触容易用与大的源极和漏极接触基本上相同覆盖面积的铜重分布层覆盖（参见例如图17B），并且最终用引线框架（参见例如图17D）覆盖，这提供传导性的进一步改进以及将封装半导体器件（参见例如图18）耦合至外部电路。源极接触和共享的漏极接触接触基本上覆盖N-LDMOS和P-LDMOS 器件的整个有源区域，很小的裸片区域被并不覆盖有源切换区域的高电流接触浪费。 
关于P-LDMOS单元8001，源极（或者源极区域）在至少重掺杂P型区域8060中被体现，并且漏极（或者漏极区域）在轻掺杂P型区域8070（例如轻掺杂漏极（“LDD”）区域）以及相邻的与沟道区域8003相对的重掺杂P型区域8080中被体现。栅极利用这里所引入的层居于沟道区域8003上方。LDD区域相对于常规设计提供用于P-LDMOS器件的更高击穿电压。这些区域以“重掺杂源极区域”、“栅极”、“轻掺杂漏极区域”和“重掺杂漏极区域”的顺序形成。 
现在转到图89，图示在半导体器件中体现的P-LDMOS器件或者其部分的实施例的截面图。P-LDMOS器件形成于包括P掺杂半导体衬底（也被称作衬底）8005的半导体裸片中以及其表面上，可以生长可选外延层（例如轻掺杂P型外延层，未示出）。衬底8005优选在约1·1014和1·1016原子/cm3之间（例如利用硼）轻掺杂。可能不需要在衬底8005上生长的选择外延层，特别是如果衬底8005是轻掺杂P型衬底。尽管在所示实施例中，衬底8005是P型衬底，本领域技术人员理解衬底8005可以是N型衬底而未背离本发明的范围。 
衬底8005形成有隔离区域（例如浅沟槽隔离区域8010）。浅沟槽隔离区域8010也可以形成于衬底内或者形成于在其上生长的外延层内以在实施于衬底上或者外延层上的器件之间提供电介质隔离。浅沟槽隔离区域8010通过用光刻胶涂敷、图案化和蚀刻衬底8005来限定其中的相应区域。示例光刻胶是AZ电子材料光刻胶。随后利用电介质（诸如二氧化硅、氮化硅其组合或者其它合适的电介质材料）蚀刻和回填浅沟槽隔离区域8010。随后通过研磨工艺（诸如化学机械平坦化（“CMP”）研磨工艺）平坦化衬底8005的外延层和浅沟槽隔离区域8010来平坦化器件，而限制对裸片的表面损坏。利用电介质的掩蔽、蚀刻、回填步骤以及研磨步骤在本领域中是众所周知的，并且在下文中将不再具体描述。 
浅沟槽隔离区域8010将P型衬底8005划分成电介质分离区域 以在所示实施例中容纳多个N-LDMOS和P-LDMOS器件以及在位于其上的控制电路中体现的作为低压器件操作的栅极驱动器和其它PMOS和NMOS器件。低压器件例如在功率变换器的控制器内（例如在可以在半导体器件的衬底上形成的控制和信号处理器件内）可操作。此外，P型衬底8005可以容纳例如在功率传动装置以及功率变换器的驱动器（即功率开关和驱动器开关）中作为高压器件操作的N-LDMOS和P-LDMOS器件。 
通过涂敷和图案化光刻胶掩膜（未示出）、随后通过蚀刻光刻胶掩膜以限定由N型阱8015占据的区域来形成N型阱8015。示例光刻胶为AZ电子材料光刻胶。图案化和蚀刻以限定轻掺杂N型阱8015的步骤在本领域中是众所周知的，并且在下文中将不再详述。通过对适当N型掺杂剂种类（诸如砷）的离子注入工艺（例如以约100至300keV的受控能量）形成轻掺杂N型阱8015，并且致使掺杂浓度分布优选在约1·1014至1·1016原子/cm3的范围内。 
通过涂敷和图案化光刻胶掩膜（未示出）、随后通过蚀刻光刻胶掩膜以限定由N型阱8017占据的区域来形成N型阱8017。通过对适当N型掺杂剂种类（诸如磷）的离子注入工艺（例如以约100至300keV的受控能量）形成N型阱8017，并且致使掺杂浓度分布优选在约1·1017至2·1019原子/cm3的范围内。 
栅极形成于栅极氧化物层8020（绝缘层）上方，栅极氧化物层8020形成于半导体器件的表面之上，厚度符合栅极的期望操作电压。栅极氧化物层8020通常为例如通过将在其上正在形成硅器件的晶片放置在炉中并且使晶片的暴露表面与氧或者其它合适材料在500至900℃反应10至100分钟（以便产生高k（介电常数）堆叠）而形成的二氧化硅，对于采用约0.25微米（“μm”）特征尺寸并且操作于低栅极电压（例如2.5伏）的器件而言具有约30至50埃（“
Figure BDA0000424085820000421
”）的厚度。假设将N-LDMOS和P-LDMOS器件的栅极到源极电压限制到（例如约2.5伏的）电压，那么栅极氧化物层8020可以形成有以上提出的栅极电介质层厚度。优选地，栅极氧化物层8020被构造为 具有均匀厚度以提供近似2.5伏的对于器件额定的栅极到源极电压，其使器件的正向传导属性完全或者接近完全饱和。当然，用于器件的前述栅极电压范围仅出于示例目的而提供，并且在本发明的宽范围内可以预期其它电压范围。 
栅极包括栅极多晶硅层8025，栅极多晶硅层8025沉积于栅极氧化物层8020的表面上并且在后续处理步骤中使用具有在约1·1019至5·1020的范围内的掺杂浓度的适当掺杂种类（诸如砷）进行N型（或者P型）掺杂以获得合适水平的传导性。栅极多晶硅层8025在炉中以提高的温度（例如在800至1000摄氏度（“℃”）进行2至60分钟）进行退火以适当扩散并且激活掺杂剂。栅极多晶硅层8025可以具有可以范围从约100至500纳米的厚度范围，但是也可以根据引用甚至更小或者更大。 
栅极形成有上层栅极氧化物层8030（绝缘层），通过将在其上正在形成硅器件的晶片放置在炉中并且使栅极多晶硅层8025的暴露表面与氧在提升的温度（例如在500至900℃进行1至60分钟）反应而在栅极多晶硅层8025的上表面之上形成该上层栅极氧化物层8030。上层栅极氧化物层8030可以形成有约50至500
Figure BDA0000424085820000431
的厚度。 
图案化并且蚀刻栅极氧化物层8020、栅极多晶硅层8025和上层栅极氧化物层8030以因此限定并且形成水平尺度。利用蚀刻采用光刻胶掩膜来限定栅极多晶硅层8025以及栅极氧化物层8020和上层栅极氧化物层8030的横向尺度。在图89中仅利用用于栅极多晶硅层8025和栅极氧化物层8020、8030的参考标号指定栅极之一。示例光刻胶是AZ电子材料光刻胶。图案化和蚀刻以限定并且形成栅极多晶硅层8025以及栅极氧化物层8020、8030的水平尺度的步骤在本领域中是众所周知的，并且在下文中将不再进一步详述。在备选实施例中，栅极多晶硅层8025可以包括并且另外可以形成有宽范围的材料，包括各种材料、其它掺杂半导体或者其它传导材料。注意到可以在相同处理步骤中掩蔽和蚀刻栅极多晶硅层8025和栅极氧化物层8020、8030的水平尺度以及用于形成于相同硅上的 N-LDMOS和P-LDMOS器件二者的多个其它结构。此外，在自对准工艺中从绝缘层（诸如与栅极多晶硅层8025以及下层和上层氧化物层8020、8030相邻的氮化硅）形成侧壁间隔物（其中之一指定为8040），而无需掩蔽和蚀刻光刻胶。应当注意从栅极多晶硅层8025上方去除上层栅极氧化物层8030的一部分（约一半栅极宽度，其约为0.2μm）。 
在N型阱8017内是利用例如砷的离子注入形成的重掺杂N型区域8090。在一个实施例中，重掺杂N型区域8090被掺杂至约1·1019至5·1020原子/cm3的浓度，并且以5至50keV的受控能量进行注入。在重掺杂N型区域8090附近是N型区域8055，N型区域8055用合适的原子种类（诸如磷）进行离子注入以实现用于正在形成的P-LDMOS的可用的栅极阈值电压。N型区域8055具有在约5·1017至1·1019原子/cm3的范围内的掺杂浓度分布，并且以约20至100keV的受控能量进行注入。在N型区域8055上方是P型离子（例如硼）的重掺杂P型区域8060。重掺杂P型区域8060利用优选在5·1018至1·1020原子/cm3的范围内的掺杂浓度分布进行注入（例如以约5至50keV的受控能量），以实现用于正在形成的P-LDMOS的低源极电阻。 
在重掺杂N型区域8090上方（并且在轻掺杂N型阱8015内的其它位置内）是重掺杂P型区域8080，重掺杂P型区域8080例如用硼掺杂至约1·1019至5·1020原子/cm3的浓度，并且以10至100keV的受控能量进行注入。在重掺杂N型区域8090上方的重掺杂P型区域8080相对地薄（例如约10至100）。同样，以在约1·1019至5·1020原子/cm3的范围内的掺杂浓度类似地P型掺杂栅极多晶硅层8025以获得合适的栅极传导性水平。在重掺杂P型区域8080上方（位于轻掺杂N型阱8015内）是轻掺杂P型区域8070，轻掺杂P型区域8070例如利用硼掺杂至在1·1017至1·1019原子/cm3的范围内的浓度，并且以10至200keV的受控能量进行注入。 
在栅极的部分和轻掺杂P型区域8070之上是二氧化硅区域8015（绝缘区域）。硅化物仅形成于暴露的硅上。在其中硅被二氧 化硅区域8105覆盖的区域中，将不形成硅化物层。硅化物层8115随后形成于硅和多晶硅的暴露区域之上，基本上不与湿法蚀刻反应，并且未被湿法蚀刻去除。示例湿法蚀刻是王水，王水是硝酸和盐酸的混合物。在一个实施例中，覆盖在栅极多晶硅层8025上面的硅化物层8115电耦合至形成于第一金属层M1（参见图16）中的栅极金属带1131。硅化物层8115可以用具有优选在100-800
Figure BDA0000424085820000451
的范围内的厚度的难熔金属（诸如钨、钛和钴）形成。 
在栅极和二氧化硅区域8105之上沉积和图案化非晶态氮氧化硅（“SixOyNz”）层8120（绝缘层）。第一金属（例如铝）层M1（例如经由真空沉积）位于氮氧化硅区域8120之间向下至在用于源极和漏极接触的区域中硅化物层8115的部分。蚀刻停止难熔层8130沉积于第一金属层M1之上。在一个实施例中，蚀刻停止难熔层8130是氮化钛、氮化钴或者氮化钨。在氮氧化硅层8120之上沉积并且图案化另一氮氧化硅层8140（绝缘层）。氮氧化硅层8120、8140使得在处理步骤序列中能够形成用于P-LDMOS的低电阻、金属源极和漏极接触。第二金属（例如铝）层M2（例如经由真空沉积）位于氮氧化硅区域8140之间向下至在用于源极和漏极接触的区域中在第一金属层M1之上的蚀刻停止难熔层8130。蚀刻停止难熔层8150沉积于第二金属层M2之上。在一个实施例中，蚀刻停止难熔层8150是氮化钛、氮化钴或者氮化钨。 
在氮氧化硅层8140之上沉积和图案化另一氮氧化硅层8160（绝缘层）。氮氧化硅层8120、8140、8160使得在处理步骤序列中能够形成用于P-LDMOS的低电阻、金属源极和漏极接触。第三金属（例如铝）层M3（例如经由真空沉积）位于氮氧化硅区域8160之间向下至在用于源极和漏极接触的区域中在第二金属层M2之上的蚀刻停止难熔层8150。在氮氧化硅层8160之上沉积和图案化最终氮氧化硅层8170（绝缘层）。氮氧化硅层8120、8140、8160、8170使得在处理步骤序列中能够形成用于P-LDMOS的低电阻、金属源极和漏极接触。在氮氧化硅层8170和第三金属层M3之上沉积和图案 化聚酰亚胺涂层8180（绝缘层）。在半导体器件之上沉积难熔阻挡层8190（例如氮化钛、氮化钽或者氮化钴）。 
随后在难熔阻挡层8190之上沉积薄金属（例如铜）种子层，随后电镀难熔阻挡层8190以形成电镀的铜层8200。在由聚酰亚胺涂层8180限定的区域中在铜层8200上方沉积另一聚酰亚胺涂层8205（绝缘层）。在P-LDMOS器件的源极的区域中的另一聚酰亚胺图层8215之间在电镀的铜层8200上方沉积和图案化另一薄金属（例如铜）种子层8215。沉积铜种子层8215是可选步骤，以产生用于后续电沉积金属（例如铜）柱的新鲜表面。 
采用酸溶液通过电镀工艺形成金属（例如铜）柱8220，金属柱8220位于铜种子层8215之上。铜柱8220用作去往传导图案化引线框架的低电阻源极接触，完成的半导体器件的端子可焊接地附接该图案化引线框架的迹线，如在上文中参照图4所示和所描述的那样。可以根据上文描述的用于构建源极接触的步骤采用对应的步骤来形成用于P-LDMOS器件的低电阻漏极接触。此外，可以选择性地在铜柱8200和放置于其上的图案化引线框架8230之间沉积包封剂（例如环氧树脂）8225，以创建用于封装的半导体器件的外部接触（例如参见图18）。 
在表1中以下列出的步骤示出可以用来在公共裸片中形成N-LDMOS和P-LDMOS器件工艺步骤序列。预期在本发明的广泛范围内可以修改特定工艺步骤序列以在公共裸片中产生N-LDMOS和P-LDMOS器件。 
最左边列中对步骤和进行编号。在向右下一列中，标识应用于N-LDMOS和P-LDMOS器件二者的工艺步骤。在第三和第四列中，分别标识仅应用于N-LDMOS和P-LDMOS器件的工艺步骤。 
表1: 
Figure BDA0000424085820000471
Figure BDA0000424085820000481
Figure BDA0000424085820000491
Figure BDA0000424085820000501
Figure BDA0000424085820000511
Figure BDA0000424085820000521
Figure BDA0000424085820000531
本领域技术人员应当理解半导体开关和功率变换器的之前描述的实施例以及制造它们的相关方法仅出于示例性目的而提出。此外，可采用其它开关模式功率变换器技术的能够产生半导体开关和功率变换器的其它实施例也在本发明的广泛范围内。虽然已经在包 括用于控制输出特性以为负载供电的控制器的功率变换器的环境中描述半导体开关和功率变换器的构造，但是半导体开关和功率变换器的构造也可以应用于其它系统，诸如功率放大器、电动机控制器和用于根据步进电动机或者其它电机设备来控制致动器的系统。 
为了更好地理解集成电路，半导体器件和半导体器件制造方法参见“Semiconductor Device Fundamentals,”by R.F.Pierret,Addison-Wesley(1996)，以及“Handbook of Sputter Deposition Technology,”by K.Wasa and S.Hayakawa,Noyes Publications(1992)。为了更好地理解功率变换器，参见“Modern DC-to-DC Switchmode Power Converter Circuits,”by Rudolph P.Severns and Gordon Bloom,Van Nostrand Reinhold Company,New York,New York(1985)以及“Principles of Power Electronics,”by J.G.Kassakian,M.F.Schlecht,and G.C.Verghese,Addison-Wesley（1991）。前述参考文献通过整体引用并入本文。 
同样，尽管已经具体描述本发明及其优点，但是应当理解可以进行各种变化、替换或者更改，而未背离如权利要求限定的本发明的精神和范围。例如，以上讨论的许多工艺可以以不同方法实施，并且可以由其它工艺或者其组合替代。 
此外，本申请的范围并不旨在限于说明书中所描述的工艺、机器、制造、物质构成、装置、方法和步骤的特定实施例。本领域技术人员将容易从本发明的公开理解到，可以开发当前存在的或者以后的工艺、机器、制造、物质构成、装置、方法和步骤，这与根据本发明可以利用的本文中描述的对应的实施例基本上执行相同功能或者基本上实现相同结果。因此，权利要求旨在在它们的范围内包括这样的工艺、机器、制造、物质构成、装置、方法和步骤。 

Claims (15)

1.一种半导体器件，包括：
衬底；
多个源极区域和漏极区域，在所述衬底上被形成为交替图案；
多个栅极，在所述多个源极区域和漏极区域中的源极区域和漏极区域之间并且与其平行地形成于所述衬底之上；以及
第一多个交替的源极金属带和漏极金属带，形成于在所述衬底上方的第一金属层中，并且与所述多个源极区域和漏极区域中的相应源极区域和漏极区域平行并且形成电接触。
2.根据权利要求1所述的半导体器件，其中所述第一多个交替的源极金属带和漏极金属带中的所述源极金属带和漏极金属带被定向为平行于所述多个栅极。
3.根据权利要求1所述的半导体器件，还包括第二多个交替的源极金属带和漏极金属带，形成于在所述第一金属层上方的第二金属层中，所述第二多个交替的源极金属带和漏极金属带覆在所述第一多个交替的源极金属带和漏极金属带中的所述源极金属带和漏极金属带上面并且与其平行，所述第一多个交替的源极金属带和漏极金属带中的所述源极金属带和漏极金属带通过穿过第一绝缘层的过孔电耦合至所述第二多个交替的源极金属带和漏极金属带中的相应所述源极金属带和漏极金属带。
4.根据权利要求3所述的半导体器件，还包括形成于在所述第二金属层上方的第三金属层中的源极接触和漏极接触，形成于所述第三金属层中的所述源极接触和漏极接触通过穿过第二绝缘层的过孔电耦合至所述第二金属层中的所述第二多个交替的源极金属带和漏极金属带中的源极金属带和漏极金属带。
5.根据权利要求4所述的半导体器件，还包括重分布层，形成于所述第三金属层上方并且通过穿过第三绝缘层的过孔电耦合至所述第三金属层。
6.根据权利要求5所述的半导体器件，还包括多个金属柱，形成于所述重分布层上方并且与所述重分布层接触。
7.根据权利要求6所述的半导体器件，还包括传导图案化引线框架，通过所述多个金属柱电耦合至所述重分布层。
8.根据权利要求7所述的半导体器件，其中所述半导体器件用包封剂进行封闭并且所述传导图案化引线框架的多个部分被暴露以用作用于所述半导体器件的外部接触。
9.根据权利要求1所述的半导体器件，还包括栅极金属带，形成于所述第一金属层中，并且被定向为垂直于所述多个栅极并且电耦合至所述多个栅极。
10.根据权利要求9所述的半导体器件，还包括在所述衬底的外围处的多个栅极驱动器，电耦合至所述栅极金属带。
11.一种形成半导体器件的方法，包括：
提供衬底；
在所述衬底上将多个源极区域和漏极区域形成为交替图案；
在所述多个源极区域和漏极区域中的源极区域和漏极区域之间并且与其平行地在所述衬底之上形成多个栅极；并且
在所述衬底上方的第一金属层中形成第一多个交替的源极金属带和漏极金属带，并且所述第一多个交替的源极金属带和漏极金属带与所述多个源极区域和漏极区域中的相应源极区域和漏极区域平行并且形成电接触。
12.根据权利要求11所述的方法，还包括在所述第一金属层上方的第二金属层中形成第二多个交替的源极金属带和漏极金属带，所述第二多个交替的源极金属带和漏极金属带覆在所述第一多个交替的源极金属带和漏极金属带中的所述源极金属带和漏极金属带上面并且与其平行，所述第一多个交替的源极金属带和漏极金属带中的所述源极金属带和漏极金属带通过过孔电耦合至所述第二多个交替的源极金属带和漏极金属带中的相应所述源极金属带和漏极金属带。
13.根据权利要求12所述的方法，还包括在所述第二金属层上方的第三金属层中形成源极接触和漏极接触，形成于所述第三金属层中的所述源极接触和漏极接触通过过孔电耦合至所述第二金属层中的所述第二多个交替的源极金属带和漏极金属带中的源极金属带和漏极金属带。
14.根据权利要求13所述的方法，还包括：
在所述第三金属层上方形成重分布层；
在所述重分布层上方并且与所述重分布层接触形成多个金属柱；
将传导图案化引线框架通过所述多个金属柱耦合至所述重分布层；并且
用包封剂封闭所述半导体器件，其中所述传导图案化引线框架的多个部分被暴露以用作用于所述半导体器件的外部接触。
15.根据权利要求11所述的方法，还包括:
形成栅极金属带，所述栅极金属带在所述第一金属层中，并且被定向为垂直于所述多个栅极并且电耦合至所述多个栅极；以及
将在所述衬底的外围处的多个栅极驱动器耦合至所述栅极金属带。
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