WO2017091152A1 - Wafer level integration of high power switching devices on cmos driver integrated circuit - Google Patents

Wafer level integration of high power switching devices on cmos driver integrated circuit Download PDF

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Publication number
WO2017091152A1
WO2017091152A1 PCT/SG2016/050577 SG2016050577W WO2017091152A1 WO 2017091152 A1 WO2017091152 A1 WO 2017091152A1 SG 2016050577 W SG2016050577 W SG 2016050577W WO 2017091152 A1 WO2017091152 A1 WO 2017091152A1
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WIPO (PCT)
Prior art keywords
accordance
driver
semiconductor package
devices
highly conductive
Prior art date
Application number
PCT/SG2016/050577
Other languages
French (fr)
Inventor
Daniel Minwoo RHEE
Tai Chong Chai
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Agency For Science, Technology And Research
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Application filed by Agency For Science, Technology And Research filed Critical Agency For Science, Technology And Research
Publication of WO2017091152A1 publication Critical patent/WO2017091152A1/en

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention generally relates to semiconductor devices and their fabrication, and more particularly relates to devices and fabrication methods for wafer level integration of high power switching devices on a driver integrated circuit (IC).
  • IC driver integrated circuit
  • New wide bandgap power devices like silicon carbide (SiC) and gallium nitride (GaN) high power devices have been introduced to meet consumer and industry requirements for increasingly demanding electronic systems.
  • high power switching wide band gap device such as GaN or SiC have high power and high frequency capability with lower ON resistance and high temperature endurance
  • GaN and SiC devices are relatively expensive as compared to conventional silicon based devices.
  • a semiconductor package module includes a substrate, a driver integrated circuit (IC), one or more power switching devices and one or more highly conductive clips.
  • IC driver integrated circuit
  • Each of the one or more switching devices is physically integrated in the semiconductor package module at a wafer level and has a gate connected to the driver IC by a gate-to-driver interconnection.
  • Each of the one or more highly conductive clips is connected to a source of a corresponding one of the one or more power switching devices by a source-to-clip interconnection.
  • each of the one or more highly conductive clips has a first surface planarly located in the semiconductor package with a similar first surface of the driver IC for co-bonding of the source-to-clip interconnections and the gate-to-driver interconnections .
  • a semiconductor high power package fabrication method for wafer level device integration includes CMOS fabrication of a CMOS device and one or more highly conductive clips such that a first surface of each of the one or more highly conductive clips is planarly located with a similar first surface of the CMOS device, and thereafter co-bonding a source-to-clip interconnection between each of one or more high power devices and a corresponding one of the one or more highly conductive clips simultaneously with a gate-to-driver interconnection between the one or more high power devices and the CMOS device.
  • FIG. 1 depicts planar views of a CMOS integrated driver IC and power switching module in accordance with a present embodiment
  • FIG. 1A is a side planar cross- sectional view of a double-side cooled silicon (Si) CMOS wafer level embedded system in a flip-chip quad flat no lead (QFN) package
  • Si double-side cooled silicon
  • QFN quad flat no lead
  • IB is a side planar cross-sectional view of a double-side cooled Si CMOS wafer level embedded system in a flip-ship QFN package with a bottom pad connected heat spreader
  • FIG. 1C is a bottom planar view of the pad/heat spreader arrangement of the module package of FIG. 1.
  • FIG. 2 depicts side planar cross-sectional views of a double-side cooled Si CMOS wafer level embedded integrated driver IC and power switching module in a flip- ship QFN package with integrated thermoelectric cooler (TEC) in accordance with the present embodiment, wherein FIG. 2A is a Si CMOS wafer level embedded system in a QFN package and FIG. 2B is a Si CMOS wafer level embedded system in a QFN package with a bottom pad connected heat spreader.
  • TEC thermoelectric cooler
  • FIG. 3 depicts side planar cross-sectional views of a double-side cooled CMOS wafer level embedded integrated driver IC and power switching module in a package fabricated with a double fan-out redistribution layer (RDL) process in accordance with the present embodiment, wherein FIG. 3A is a Si CMOS wafer level embedded system in a package and FIG. 3B is a Si CMOS wafer level embedded system in a package with a bottom pad connected heat spreader.
  • RDL redistribution layer
  • FIG. 4 depicts side planar cross- sectional views of a double-side cooled CMOS and gallium nitride (GaN) dual fan-out module in accordance with the present embodiment.
  • FIG. 5, comprising FIGs. 5A to 5K, depicts side planar cross-sectional views of wafer level embedded integrated driver IC and power switching module fabrication steps in a QFN-style packaging process in accordance with the present embodiment.
  • FIG. 6 comprising FIGs. 6A to 6L, depicts side planar cross-sectional views of wafer level embedded integrated driver IC and power switching module fabrication steps in a molded wafer level chip scale package (CSP) process in accordance with the present embodiment.
  • CSP chip scale package
  • FIG. 7 depicts graphs of dual-side cooling thermal management in relation to mold thermal conductivity and package thickness in accordance with the present embodiment, wherein FIG. 7A depicts dual- side cooling thermal management when using a low conductive mold, FIG. 7B depicts dual-side cooling thermal management when using a high conductive mold, FIG. 7C depicts dual-side cooling thermal management when using a thin mold and FIG. 7D depicts dual-side cooling thermal management when using a thick mold.
  • FIG. 8 comprising FIGs. 8A and 8B, illustrates thermal management by dual-side cooling versus thermal management by bottom-only cooling in accordance with the present embodiment, wherein FIG. 8A illustrates thermal management by dual-side cooling and FIG. 8B thermal management by bottom-only cooling.
  • CMOS driver integrated circuits present methods and devices for wafer level integration of CMOS driver ICs and power devices (including silicon (Si), gallium nitride (GaN), gallium arsenic (GaAs) and silicon carbide (SiC) power devices).
  • Si silicon
  • GaN gallium nitride
  • GaAs gallium arsenic
  • SiC silicon carbide
  • High power switching wide bandgap devices such as GaN or SiC power devices have greater functionality than silicon-based power devices, providing high power and high frequency capabilities as well as high temperature endurance and lower ON resistance.
  • driver ICs for control of wide band gap devices typically utilize silicon-based well-established CMOS technologies while high power and high frequency switching performance is delivered by GaN and SiC devices with minimized feature size for cost control.
  • Integration in lead frame based packaging technologies such as quad flat no lead (QFN) packages is accomplished by side-by-side integration using wire bonding interconnection technology.
  • Fabrication in accordance with the present embodiment defines a flip-chip bonding area for power switching devices by a redistribution layer (RDL) process on a CMOS wafer or a molded wafer of a CMOS array then attaches power switching devices through the flip-chip bonding area.
  • RDL redistribution layer
  • the flipped power devices' backside are directly attached to a heat spreader on their bottom side, thereby providing a direct thermal path through the on-board cooling structure.
  • an active thermoelectric cooler can be embedded and electrically connected through the RDL structure for active cooling thereby further enhancing thermal management.
  • the bottom substrate could be either a lead- frame (e.g., QFN) or a copper (Cu) RDL layer with some thickness. Smaller form factors with enhanced functionalities can be achieved in accordance with the present embodiment by embedding passive components during CMOS wafer fabrication fan- out molding steps.
  • devices and fabrication methods in accordance with the present embodiment can provide better performance, smaller form factors and higher cost effective scalability.
  • High performance in accordance with the present embodiment is provided by shortened integration between the driver IC and the power devices through the RDL using a fan-out driver IC structure.
  • Better productivity and higher scalability in accordance with the present embodiment is provided by wafer level integration of the driver IC and the power devices.
  • Smaller form factors in accordance with the present embodiment are provided by three-dimensionally integrating the passive components inside of the integrated package structure.
  • enhanced thermal management in accordance with the present embodiment is provided by backside interconnection/bumping of the power devices to provide shortened thermal dissipation paths.
  • a side planar cross-sectional view 100 depicts a double-side cooled Si CMOS wafer level integrated structure in a flip-chip QFN power module package in accordance with the present embodiment.
  • the power module package includes a QFN lead frame 101 with a silicon CMOS substrate 102. Embedded in the silicon substrate 102, there are power switching devices 104, 106 and a driver IC 108. Each of the power switching devices 104, 106 includes a gate, a drain and a source and is connected to the driver IC by a gate-to-driver interconnection 109.
  • the gate-to-driver interconnections 109 can be flip-chip micro- bump bonding pads defined by fan-in or fan-out technology.
  • the power module package also includes embedded highly conductive clips 110, 112, such as copper (Cu) clips, and each of the highly conductive clips 110, 112 is connected to a corresponding one of the power switching devices 104, 106 by a source-to-clip interconnection 113.
  • the embedded highly conductive clips 110, 112 advantageously provide high power delivery for power switching and other purposes.
  • the power module package also includes lead frame pads 114, 116, 118, 120.
  • the three-dimensional (3D) power module package structure includes embedded passive devices 122, 124 in a fan-in or fan-out area 126 as shown in a top planar view 180 of FIG. IC.
  • the passive components 122, 124 are connected to the highly conductive clips 110, 112, respectively, to provide passive component functionality (e.g., electrostatic discharge protection) for the integrated power module package structure.
  • the package could be attached by a thermal management device 128, such as a heat spreader, connected on a top side of the driver IC.
  • a first RDL process is performed with wafer level lithography on the molded wafer surface to form a RDL 130 or to define the flip-chip bonding pads 114, 116, 118, 120 for power switching device integration.
  • a wafer bumping process is performed to create solder micro-bumps or copper pillars 109 for integration of the power switching devices 104, 106 with the driver IC 108, the solder micro-bumps or copper pillars forming the gate-to-driver interconnections 109.
  • Solder balls or copper pillars 132 can beaded to the substrate 102 to create a joint area for the QFN lead frame 101 and could alternatively be wafer level copper pads patterned by a subtractive method.
  • Si CMOS fan-out power module devices can be fabricated with power switching device flip-chip integration and attached to the QFN lead frame 101.
  • the drains of the power switching devices 104, 106 can be attached to the metal pads 116, 118 by drain-to-pad interconnections in the RDL 130, the pads 116, 118 also acting as thermal management devices (e.g., heat spreaders) for heat dissipation through a connected printed circuit board (PCB) or equivalent cooling structures.
  • PCB printed circuit board
  • the embedded highly conductive clips 110, 112 are formed in a planar structure with a surface of the driver IC 108 to provide high power flip-chip interconnections for sources of the power switching devices 104, 106 in the same plane as interconnections for signal bonding of the gates of the power switching devices 104, 106 to the driver IC 108.
  • the driver IC 108 is flip-chipped interconnected using fan-in or fan-out RDL layer interconnects to QFN pads while the power switching devices 104, 106 have their drains interconnected to the pads 116, 118.
  • the view 100 depicts two power switching devices 104, 106 connected to one driver IC 108 as normally two power switching devices need to be integrated with one driver IC for single phase applications.
  • FIG. IB a variant of the present embodiment is depicted in a side planar cross-sectional view 150.
  • one power switching device 104 is connected to the driver IC 108.
  • solder balls or copper pillars 152 connect the driver IC 108 and a passive device 154 to signal pads 156, 158.
  • the pad 156 can be formed in a fan-in pattern and the pad 158 can be formed in a fan-out pattern to accommodate one another.
  • side planar cross-sectional views 200, 250 depict the same structure as shown in the views 100, 150 of FIGs. 1A and IB except that a thermal electric cooling module 202 (e.g., a thermoelectric cooler (TEC)) replaces the bottom heat spreaders 116, 118.
  • TEC thermoelectric cooler
  • Thermoelectric cooling uses the Peltier effect to create a heat flux between the junctions of two different types of materials.
  • a Peltier cooler, heater, or thermoelectric heat pump is a solid-state active heat pump which transfers heat from one side of the device to the other, with consumption of electrical energy depending on the direction of the current.
  • FIGs. 3A and 3B Side planar cross-sectional views 300, 350 of FIGs. 3A and 3B, respectively, depict the same structure as shown in the views 100, 150 of FIGs. 1A and IB but instead of using the QFN type lead frame 101 and the thick metal heat spreaders 116, 118, the structures depicted in the views 300, 350 are fabricated using a wafer level second fan-out process to generate a ball grid array (BGA) 302, a RDL 304, and bumping interconnects 306.
  • BGA ball grid array
  • RDL RDL
  • the backside (or drain side) of the power switching devices 104, 106 are connected through an under bump metallization (UBM) process which forms the bumping interconnects 306 and this structure provides a thermal path for heat dissipation of the power switching devices 104, 106 to a PCB board or to equivalent board level cooling structures.
  • UBM under bump metallization
  • an additional top side wafer level RDL process can interconnect the additional passive components 402 as shown in side planar cross-sectional views 400, 450 in FIG. 4.
  • the top side components (the passive components 122, 124 and the additional passive component 402) are interconnected to other devices (e.g., the power switching devices 104, 106) in the package by through silicon vias (TSVs) 404.
  • TSVs through silicon vias
  • TSVs through mold vias
  • the semiconductor packages depicted in both views 400, 450, the embedded Cu clips 110, 112 have lower surfaces planarly located in the semiconductor package with a lower surface of the driver IC 108 thereby advantageously enabling integration of the source-to-clip high power flip-chip interconnection and the gate-to-driver signal interconnection bonding 113 for integration of the power switching devices 104, 106 in the semiconductor package module.
  • FIG. 5 comprising FIGs. 5A to 5K, side planar cross-sectional views of semiconductor fabrication steps in a QFN-style packaging process for wafer level integration of the driver IC 108 and the power switching devices 104, 106 in accordance with the present embodiment are depicted.
  • FIG. 5A depicts a first step in the process where the CMOS driver IC 108, the passive components 122, 124 and the thick copper clips 110, 112 are attached on a surface of a temporary adhesive 502 laminated on a carrier wafer 504 of silicon, glass or metal.
  • FIG. 5B depicts an optional step of attaching the heat spreader 128 on the backside of the CMOS driver IC 108 using a thermally adhesive material 506, such as a thermally conductive adhesive or solder, on the metalized backside surface of the CMOS driver IC 108.
  • FIG. 5C depicts a first molding process which molds a non-conductive material 508 on and over the components on the substrate 504 and, as depicted in FIG. 5D, the molding surface is ground off to expose a surface of the heat spreader 128.
  • FIG 5E depicts detachment of the molded wafer from the carrier wafer (i.e., the substrate 504. The molded wafer is then flipped and a first active layer dielectric 510 is fabricated on the surface.
  • FIG. 5F depicts the fan-out metallization patterns of the RDL and the micro-bumps 109, 113 defined and developed on interconnection pads on the active layer 510 on the driver IC 108 and the passive components 122, 124 through a lithography process as a redistribution layer (RDL).
  • RDL redistribution layer
  • the power switching devices 104, 106, additional components and interconnection bumps 132 or other TMVs are also depicted in FIG. 5F integrated on the RDL layer.
  • an optional under-fill 512 could be applied.
  • the integrated package module needs to be individualized through a wafer sawing process (FIG. 5H) and each individualized devices are assembled by flip-chip bonding to conventional QFN lead-frames (FIG. 51).
  • the flip-chip bonding and bonding of the drain side interconnection (or thermal interconnection) of the power switching devices 104, 106 are processed simultaneously.
  • a QFN molding process FIG. 5J
  • a backend sawing and singulation process FIG. 5K
  • FIG. 6 depicts side planar cross-sectional views of wafer level embedded integrated driver IC and power switching module fabrication steps in a molded wafer level chip scale package (CSP) process in accordance with the present embodiment.
  • the steps depicted in FIGs. 6A to 6G are the same as the steps depicted in FIGs. 5A to 5G and described above.
  • the highly conductive metal clips 110, 112 e.g. copper
  • passive components 122, 124 are attached on the surface of the temporary adhesive 502 laminated on the carrier wafer 504 (FIG. 6A).
  • the heat spreader 128 could be attached on the backside of the CMOS wafer using thermally conductive adhesive or solder (FIG.
  • the first molding process is applied (FIG. 6C) and the molding 508 surface is ground off to expose the heat spreader 128 surface (FIG. 6D).
  • the molded wafer is detached from the carrier wafer 504 and a dielectric layer 510 is deposited (FIG. 6E) and the fan-out metallization patterns (RDL) and micro bumps are defined and developed on the active interconnection pads on driver IC 108 and the passive components 122, 124 through lithography (FIG. 6F).
  • the power switching devices 104, 106, additional components and interconnection bumps or other TMV are integrated onto this RDL layers as also shown in FIG. 6F.
  • an under-filling process could be applied (FIG. 6G).
  • a second molding process is performed and, after molding, a top surface of the second mold 614 is ground off in order to expose the TMVs 132 (e.g., solder, metal core solder balls, or copper pillars) and a backside surface of the power switching devices 104, 106 as seen in FIG. 6H.
  • a second layer dielectric 616 is deposited (FIG. 61) on the exposed TMVs 132 and the backside surfaces of the power switching devices 104, 106; and a second RDL process (FIG. 6J) defines interconnections such as ball attach pads 306 and metallization 306 on the backside of power switching devices 104, 106 to provide electrical and/or thermal paths to the PCB or the system level cooling.
  • After fan-out wafer level integration is finished by formation of the solder balls 302 of the ball grid array (FIG. 6K) and the integrated CSP package modules are singulated by a wafer sawing process (FIG. 6L).
  • FIG. 7 depicts graphs 700 (FIG. 7A), 720 (FIG. 7B), 740 (FIG. 7C), 760 (FIG. 7D) of dual-side cooling thermal management in relation to mold thermal conductivity and package thickness in accordance with the present embodiment as measured in the thermal performance simulations where an isothermal cooling boundary condition was added to the top side of the molded surface and the system's ambient temperature was set to 85°C.
  • mold thermal conductivity is plotted along the x-axis 702, 722, 742, 762 and thermal resistance is plotted along the y-axis 704, 724, 744, 764.
  • the graph 700 depicts dual-side cooling thermal management when using a low conductive mold.
  • the thermal resistance of the bottom of the die -junction at mold thicknesses from 0.5mm to 0.7mm for a die-attach thermal conductivity of 30W/mK (dotted trace 710) and a die- attach thermal conductivity of 2W/mK (dotted trace 712) shows that increasing the mold thickness can make a slight increase in thermal resistance.
  • the thermal resistance of the top of the die -junction at mold thicknesses from 0.5mm to 0.7mm for a die-attach thermal conductivity of 30W/mK (solid trace 714) and a die-attach thermal conductivity of 2W/mK (solid trace 716) shows that increasing the mold thickness can make a greater increase in thermal resistance.
  • the graph 720 depicts dual-side cooling thermal management when using a high conductive mold.
  • the graph 740 depicts dual-side cooling thermal management when using a thin mold.
  • the thermal resistance of the bottom of the die -junction at mold thermal conductivities from l.OW/mK to 3.0W/mK for a die-attach thermal conductivity of 30W/mK (dotted trace 750) and a die-attach thermal conductivity of 2W/mK (dotted trace 752) shows that increasing the mold thermal conductivity can make a slight decrease in thermal resistance.
  • the thermal resistance of the top of the die- junction at mold thermal conductivities from l.OW/mK to 3.0W/mK for a die-attach thermal conductivity of 30W/mK (solid trace 754) and a die-attach thermal conductivity of 2W/mK (solid trace 756) shows that increasing the mold thermal conductivity can make a greater decrease in thermal resistance.
  • the graph 760 depicts dual-side cooling thermal management when using a thick mold. Similar mold thermal conductivity variations can be seen at the bottom of the die -junction (thermal conductivity of 30W/mK (dotted trace 770) and thermal conductivity of 2W/mK (dotted trace 772)) and the top of the die -junction (thermal conductivity of 30W/mK (solid trace 774) and thermal conductivity of 2W/mK (solid trace 776)).
  • thermal management by dual-side cooling versus thermal management by bottom-only cooling in accordance with the present embodiment is depicted in an illustration 800 (FIG. 8A) depicting dual-side cooling temperatures at a die-junction 802 and an illustration 850 (FIG. 8B) depicting bottom- only cooling temperatures at a die-junction 852.
  • the die-junction temperature is cooler for dual-sided cooling (99°C vs 121°C). This cooling is due to air bottleneck removal at the power module top-side as a result of the structure of the semiconductor package module in accordance with the present embodiment.
  • the present embodiment provides a novel and advantageous semiconductor package design and fabrication method for wafer level integrated Si based CMOS driver devices and high power switching devices.
  • the active components, along with passive components can be integrated at the wafer level using fan-out wafer level integration.
  • first wafer level molding and first RDL defining integration of the CMOS driver IC, the GaN high power devices, and passive components in a single 3D integrated semiconductor package module can be achieved no matter what the size ratio of the components.
  • the system level package integration in accordance with the present embodiment can be either QFN lead frame style or BGA style and the wafer level packaging in accordance with the present embodiment provides a scalable, cost effective wafer level system integration package.
  • the semiconductor package modules in accordance with the present embodiment provide enhanced thermal performance by utilizing a double side cooling design, especially for the GaN device backsides which can additionally be interconnected to board level thermal dissipation paths through copper heat spreader and/or solder ball interconnections.
  • Modules and fabrication methods in accordance with the present embodiment enable cost effective heterogeneous wafer level processing with a highly miniaturized structure having heightened efficiency in view of thermal electrical and mechanical reliability, thereby providing reliable, cost effective, scalable solutions for automotive motor control, generator power inversion, aerospace high power devices, home appliances and other high-power control applications.

Abstract

A semiconductor package module and the method for its fabrication are provided. The semiconductor package module includes a substrate, a driver integrated circuit (IC), one or more power switching devices and one or more highly conductive clips. Each of the one or more switching devices is physically integrated in the semiconductor package module at a wafer level and has a gate connected to the driver IC by a gate-to-driver interconnection. Each of the one or more highly conductive clips is connected to a source of a corresponding one of the one or more power switching devices by a source-to-clip interconnection. Also, each of the one or more highly conductive clips has a first surface planarly located in the semiconductor package with a similar first surface of the driver IC for co-bonding of the source-to- clip interconnections and the gate-to-driver interconnections.

Description

WAFER LEVEL INTEGRATION OF HIGH POWER SWITCHING DEVICES ON CMOS DRIVER INTEGRATED CIRCUIT
PRIORITY CLAIM
[0001] This application claims priority from Singapore Patent Application No. 10201509627U filed on November 23, 2015.
TECHNICAL FIELD
[0002] The present invention generally relates to semiconductor devices and their fabrication, and more particularly relates to devices and fabrication methods for wafer level integration of high power switching devices on a driver integrated circuit (IC).
BACKGROUND OF THE DISCLOSURE
[0003] The requirements of high power electronics for automotive, aerospace and green renewable energy applications have dramatically drastically increased and semiconductor-based power inverters and converters are essential to these requirements to provide efficient power delivery for these high power applications. Contemporary high power modules need to operate at high junction temperatures with high frequency switching, requiring effective thermal management and heat dissipation solutions in highly scalable cost effective miniaturized structures.
[0004] Conventional semiconductor power devices have small feature ranges and, because of the advancement of CMOS technology, driver integrated circuits (ICs) are also becoming smaller. Yet interconnections between power devices and driver ICs need to be short for high performance switching application and direct interconnections are limited. Further, multi-phase applications require two power switching devices to be integrated with one driver IC for each phase. Because of size limitations, power switching devices and driver ICs are integrated in side-by-side packaging on a substrate. Yet, this arrangement limits performance requirements due to longer interconnections. When power ICs are directly flip-chip bonded onto driver ICs, the interconnections can be shortened, yet the flip-chip interconnection still requires thermal dissipation paths.
[0005] New wide bandgap power devices like silicon carbide (SiC) and gallium nitride (GaN) high power devices have been introduced to meet consumer and industry requirements for increasingly demanding electronic systems. Yet, while high power switching wide band gap device such as GaN or SiC have high power and high frequency capability with lower ON resistance and high temperature endurance, GaN and SiC devices are relatively expensive as compared to conventional silicon based devices.
[0006] Thus, what are needed are designs and fabrication methods for high power and driver device integration which at least partially overcomes the drawbacks of present approaches and provides better performance in smaller form factors with better scalability and cost effectiveness. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.
SUMMARY
[0007] According to at least one embodiment of the present invention, a semiconductor package module is provided. The semiconductor package module includes a substrate, a driver integrated circuit (IC), one or more power switching devices and one or more highly conductive clips. Each of the one or more switching devices is physically integrated in the semiconductor package module at a wafer level and has a gate connected to the driver IC by a gate-to-driver interconnection. Each of the one or more highly conductive clips is connected to a source of a corresponding one of the one or more power switching devices by a source-to-clip interconnection. Also, each of the one or more highly conductive clips has a first surface planarly located in the semiconductor package with a similar first surface of the driver IC for co-bonding of the source-to-clip interconnections and the gate-to-driver interconnections .
[0008] According to a further embodiment of the present invention a semiconductor high power package fabrication method for wafer level device integration is provided. The method includes CMOS fabrication of a CMOS device and one or more highly conductive clips such that a first surface of each of the one or more highly conductive clips is planarly located with a similar first surface of the CMOS device, and thereafter co-bonding a source-to-clip interconnection between each of one or more high power devices and a corresponding one of the one or more highly conductive clips simultaneously with a gate-to-driver interconnection between the one or more high power devices and the CMOS device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to illustrate various embodiments and to explain various principles and advantages in accordance with a present invention, by way of non- limiting example only, wherein: [0010] FIG. 1, comprising FIGs. 1A, IB and 1C, depicts planar views of a CMOS integrated driver IC and power switching module in accordance with a present embodiment, wherein FIG. 1A is a side planar cross- sectional view of a double-side cooled silicon (Si) CMOS wafer level embedded system in a flip-chip quad flat no lead (QFN) package, FIG. IB is a side planar cross-sectional view of a double-side cooled Si CMOS wafer level embedded system in a flip-ship QFN package with a bottom pad connected heat spreader, and FIG. 1C is a bottom planar view of the pad/heat spreader arrangement of the module package of FIG. 1.
[0011] FIG. 2, comprising FIGs. 2A and 2B, depicts side planar cross-sectional views of a double-side cooled Si CMOS wafer level embedded integrated driver IC and power switching module in a flip- ship QFN package with integrated thermoelectric cooler (TEC) in accordance with the present embodiment, wherein FIG. 2A is a Si CMOS wafer level embedded system in a QFN package and FIG. 2B is a Si CMOS wafer level embedded system in a QFN package with a bottom pad connected heat spreader.
[0012] FIG. 3, comprising FIGs. 3A and 3B, depicts side planar cross-sectional views of a double-side cooled CMOS wafer level embedded integrated driver IC and power switching module in a package fabricated with a double fan-out redistribution layer (RDL) process in accordance with the present embodiment, wherein FIG. 3A is a Si CMOS wafer level embedded system in a package and FIG. 3B is a Si CMOS wafer level embedded system in a package with a bottom pad connected heat spreader.
[0013] FIG. 4 depicts side planar cross- sectional views of a double-side cooled CMOS and gallium nitride (GaN) dual fan-out module in accordance with the present embodiment. [0014] FIG. 5, comprising FIGs. 5A to 5K, depicts side planar cross-sectional views of wafer level embedded integrated driver IC and power switching module fabrication steps in a QFN-style packaging process in accordance with the present embodiment.
[0015] FIG. 6, comprising FIGs. 6A to 6L, depicts side planar cross-sectional views of wafer level embedded integrated driver IC and power switching module fabrication steps in a molded wafer level chip scale package (CSP) process in accordance with the present embodiment.
[0016] FIG. 7, comprising FIGs. 7A, 7B, 7C and 7D, depicts graphs of dual-side cooling thermal management in relation to mold thermal conductivity and package thickness in accordance with the present embodiment, wherein FIG. 7A depicts dual- side cooling thermal management when using a low conductive mold, FIG. 7B depicts dual-side cooling thermal management when using a high conductive mold, FIG. 7C depicts dual-side cooling thermal management when using a thin mold and FIG. 7D depicts dual-side cooling thermal management when using a thick mold.
[0017] And FIG. 8, comprising FIGs. 8A and 8B, illustrates thermal management by dual-side cooling versus thermal management by bottom-only cooling in accordance with the present embodiment, wherein FIG. 8A illustrates thermal management by dual-side cooling and FIG. 8B thermal management by bottom-only cooling.
[0018] Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been depicted to scale.
DETAILED DESCRIPTION
[0019] The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description. It is the intent of this invention to present devices and methods for fabrication for novel power module structures which integrate at the wafer level power switching devices with CMOS driver integrated circuits (ICs). In short, present embodiments present methods and devices for wafer level integration of CMOS driver ICs and power devices (including silicon (Si), gallium nitride (GaN), gallium arsenic (GaAs) and silicon carbide (SiC) power devices).
[0020] High power switching wide bandgap devices such as GaN or SiC power devices have greater functionality than silicon-based power devices, providing high power and high frequency capabilities as well as high temperature endurance and lower ON resistance. However, as GaN and SiC devices are relatively more expensive than conventional silicon based devices, driver ICs for control of wide band gap devices typically utilize silicon-based well-established CMOS technologies while high power and high frequency switching performance is delivered by GaN and SiC devices with minimized feature size for cost control. Integration in lead frame based packaging technologies such as quad flat no lead (QFN) packages is accomplished by side-by-side integration using wire bonding interconnection technology.
[0021] In accordance with a present embodiment, better performance in smaller form factors can be achieved with better productivity and cost effectiveness as compared to conventional integration solutions. Fabrication in accordance with the present embodiment defines a flip-chip bonding area for power switching devices by a redistribution layer (RDL) process on a CMOS wafer or a molded wafer of a CMOS array then attaches power switching devices through the flip-chip bonding area. To enhance thermal management in accordance with the present embodiment, the flipped power devices' backside are directly attached to a heat spreader on their bottom side, thereby providing a direct thermal path through the on-board cooling structure. Instead of passive metal pads, an active thermoelectric cooler (TEC) can be embedded and electrically connected through the RDL structure for active cooling thereby further enhancing thermal management. The bottom substrate could be either a lead- frame (e.g., QFN) or a copper (Cu) RDL layer with some thickness. Smaller form factors with enhanced functionalities can be achieved in accordance with the present embodiment by embedding passive components during CMOS wafer fabrication fan- out molding steps.
[0022] Thus, devices and fabrication methods in accordance with the present embodiment can provide better performance, smaller form factors and higher cost effective scalability. High performance in accordance with the present embodiment is provided by shortened integration between the driver IC and the power devices through the RDL using a fan-out driver IC structure. Better productivity and higher scalability in accordance with the present embodiment is provided by wafer level integration of the driver IC and the power devices. Smaller form factors in accordance with the present embodiment are provided by three-dimensionally integrating the passive components inside of the integrated package structure. And enhanced thermal management in accordance with the present embodiment is provided by backside interconnection/bumping of the power devices to provide shortened thermal dissipation paths.
[0023] Referring to FIG. 1A, a side planar cross-sectional view 100 depicts a double-side cooled Si CMOS wafer level integrated structure in a flip-chip QFN power module package in accordance with the present embodiment. The power module package includes a QFN lead frame 101 with a silicon CMOS substrate 102. Embedded in the silicon substrate 102, there are power switching devices 104, 106 and a driver IC 108. Each of the power switching devices 104, 106 includes a gate, a drain and a source and is connected to the driver IC by a gate-to-driver interconnection 109. The gate-to-driver interconnections 109 can be flip-chip micro- bump bonding pads defined by fan-in or fan-out technology. The power module package also includes embedded highly conductive clips 110, 112, such as copper (Cu) clips, and each of the highly conductive clips 110, 112 is connected to a corresponding one of the power switching devices 104, 106 by a source-to-clip interconnection 113. The embedded highly conductive clips 110, 112 advantageously provide high power delivery for power switching and other purposes. The power module package also includes lead frame pads 114, 116, 118, 120.
[0024] In accordance with the present embodiment, the three-dimensional (3D) power module package structure includes embedded passive devices 122, 124 in a fan-in or fan-out area 126 as shown in a top planar view 180 of FIG. IC. The passive components 122, 124 are connected to the highly conductive clips 110, 112, respectively, to provide passive component functionality (e.g., electrostatic discharge protection) for the integrated power module package structure. The package could be attached by a thermal management device 128, such as a heat spreader, connected on a top side of the driver IC.
[0025] A first RDL process is performed with wafer level lithography on the molded wafer surface to form a RDL 130 or to define the flip-chip bonding pads 114, 116, 118, 120 for power switching device integration. After fabricating the RDL 130, a wafer bumping process is performed to create solder micro-bumps or copper pillars 109 for integration of the power switching devices 104, 106 with the driver IC 108, the solder micro-bumps or copper pillars forming the gate-to-driver interconnections 109. Solder balls or copper pillars 132 can beaded to the substrate 102 to create a joint area for the QFN lead frame 101 and could alternatively be wafer level copper pads patterned by a subtractive method. Thus, in accordance with the present embodiment, Si CMOS fan-out power module devices can be fabricated with power switching device flip-chip integration and attached to the QFN lead frame 101. Note also that the drains of the power switching devices 104, 106 can be attached to the metal pads 116, 118 by drain-to-pad interconnections in the RDL 130, the pads 116, 118 also acting as thermal management devices (e.g., heat spreaders) for heat dissipation through a connected printed circuit board (PCB) or equivalent cooling structures.
[0026] Thus, advantageously the embedded highly conductive clips 110, 112 are formed in a planar structure with a surface of the driver IC 108 to provide high power flip-chip interconnections for sources of the power switching devices 104, 106 in the same plane as interconnections for signal bonding of the gates of the power switching devices 104, 106 to the driver IC 108. Additionally, the driver IC 108 is flip-chipped interconnected using fan-in or fan-out RDL layer interconnects to QFN pads while the power switching devices 104, 106 have their drains interconnected to the pads 116, 118.
[0027] The view 100 depicts two power switching devices 104, 106 connected to one driver IC 108 as normally two power switching devices need to be integrated with one driver IC for single phase applications. Referring to FIG. IB, a variant of the present embodiment is depicted in a side planar cross-sectional view 150. In the view 150, one power switching device 104 is connected to the driver IC 108. In this variant, solder balls or copper pillars 152 connect the driver IC 108 and a passive device 154 to signal pads 156, 158. The pad 156 can be formed in a fan-in pattern and the pad 158 can be formed in a fan-out pattern to accommodate one another. [0028] Referring to FIGs. 2A and 2B, side planar cross-sectional views 200, 250 depict the same structure as shown in the views 100, 150 of FIGs. 1A and IB except that a thermal electric cooling module 202 (e.g., a thermoelectric cooler (TEC)) replaces the bottom heat spreaders 116, 118. Thermoelectric cooling uses the Peltier effect to create a heat flux between the junctions of two different types of materials. A Peltier cooler, heater, or thermoelectric heat pump is a solid-state active heat pump which transfers heat from one side of the device to the other, with consumption of electrical energy depending on the direction of the current.
[0029] Side planar cross-sectional views 300, 350 of FIGs. 3A and 3B, respectively, depict the same structure as shown in the views 100, 150 of FIGs. 1A and IB but instead of using the QFN type lead frame 101 and the thick metal heat spreaders 116, 118, the structures depicted in the views 300, 350 are fabricated using a wafer level second fan-out process to generate a ball grid array (BGA) 302, a RDL 304, and bumping interconnects 306. The backside (or drain side) of the power switching devices 104, 106 are connected through an under bump metallization (UBM) process which forms the bumping interconnects 306 and this structure provides a thermal path for heat dissipation of the power switching devices 104, 106 to a PCB board or to equivalent board level cooling structures.
[0030] If more passive components are required to be assembled into the package, an additional top side wafer level RDL process can interconnect the additional passive components 402 as shown in side planar cross-sectional views 400, 450 in FIG. 4. In the view 400, the top side components (the passive components 122, 124 and the additional passive component 402) are interconnected to other devices (e.g., the power switching devices 104, 106) in the package by through silicon vias (TSVs) 404. In the view 452, through mold vias (TMVs) 452 are utilized to interconnect the top side components 402, 122, 124, thereby providing for more passive component integration in the semiconductor package module. In accordance with the present embodiment, the semiconductor packages depicted in both views 400, 450, the embedded Cu clips 110, 112 have lower surfaces planarly located in the semiconductor package with a lower surface of the driver IC 108 thereby advantageously enabling integration of the source-to-clip high power flip-chip interconnection and the gate-to-driver signal interconnection bonding 113 for integration of the power switching devices 104, 106 in the semiconductor package module.
[0031] Referring to FIG. 5, comprising FIGs. 5A to 5K, side planar cross-sectional views of semiconductor fabrication steps in a QFN-style packaging process for wafer level integration of the driver IC 108 and the power switching devices 104, 106 in accordance with the present embodiment are depicted.
[0032] FIG. 5A depicts a first step in the process where the CMOS driver IC 108, the passive components 122, 124 and the thick copper clips 110, 112 are attached on a surface of a temporary adhesive 502 laminated on a carrier wafer 504 of silicon, glass or metal. FIG. 5B depicts an optional step of attaching the heat spreader 128 on the backside of the CMOS driver IC 108 using a thermally adhesive material 506, such as a thermally conductive adhesive or solder, on the metalized backside surface of the CMOS driver IC 108. Then, FIG. 5C depicts a first molding process which molds a non-conductive material 508 on and over the components on the substrate 504 and, as depicted in FIG. 5D, the molding surface is ground off to expose a surface of the heat spreader 128.
[0033] FIG 5E depicts detachment of the molded wafer from the carrier wafer (i.e., the substrate 504. The molded wafer is then flipped and a first active layer dielectric 510 is fabricated on the surface. FIG. 5F depicts the fan-out metallization patterns of the RDL and the micro-bumps 109, 113 defined and developed on interconnection pads on the active layer 510 on the driver IC 108 and the passive components 122, 124 through a lithography process as a redistribution layer (RDL). The power switching devices 104, 106, additional components and interconnection bumps 132 or other TMVs are also depicted in FIG. 5F integrated on the RDL layer. At FIG. 5G, to protect flip-chip joints of the power switching devices 104, 106, an optional under-fill 512 could be applied.
[0034] After fan-out wafer level integration is finished, the integrated package module needs to be individualized through a wafer sawing process (FIG. 5H) and each individualized devices are assembled by flip-chip bonding to conventional QFN lead-frames (FIG. 51). In accordance with the present embodiment, the flip-chip bonding and bonding of the drain side interconnection (or thermal interconnection) of the power switching devices 104, 106 are processed simultaneously. After the system is attached to the QFN lead frame, a QFN molding process (FIG. 5J) and a backend sawing and singulation process (FIG. 5K) complete fabrication of the QFN-style semiconductor package module which wafer level integration of the driver IC 108 and the power switching devices 104, 106 in accordance with the present embodiment.
[0035] FIG. 6, comprising FIGs. 6A to 6L, depicts side planar cross-sectional views of wafer level embedded integrated driver IC and power switching module fabrication steps in a molded wafer level chip scale package (CSP) process in accordance with the present embodiment. The steps depicted in FIGs. 6A to 6G are the same as the steps depicted in FIGs. 5A to 5G and described above. The highly conductive metal clips 110, 112 (e.g. copper) and passive components 122, 124 are attached on the surface of the temporary adhesive 502 laminated on the carrier wafer 504 (FIG. 6A). Optionally, the heat spreader 128 could be attached on the backside of the CMOS wafer using thermally conductive adhesive or solder (FIG. 6B). Then, the first molding process is applied (FIG. 6C) and the molding 508 surface is ground off to expose the heat spreader 128 surface (FIG. 6D). Next, the molded wafer is detached from the carrier wafer 504 and a dielectric layer 510 is deposited (FIG. 6E) and the fan-out metallization patterns (RDL) and micro bumps are defined and developed on the active interconnection pads on driver IC 108 and the passive components 122, 124 through lithography (FIG. 6F). The power switching devices 104, 106, additional components and interconnection bumps or other TMV are integrated onto this RDL layers as also shown in FIG. 6F. Optionally, to protect the flip-chip joints of the power switching devices 104, 106, an under-filling process could be applied (FIG. 6G).
[0036] A second molding process is performed and, after molding, a top surface of the second mold 614 is ground off in order to expose the TMVs 132 (e.g., solder, metal core solder balls, or copper pillars) and a backside surface of the power switching devices 104, 106 as seen in FIG. 6H. A second layer dielectric 616 is deposited (FIG. 61) on the exposed TMVs 132 and the backside surfaces of the power switching devices 104, 106; and a second RDL process (FIG. 6J) defines interconnections such as ball attach pads 306 and metallization 306 on the backside of power switching devices 104, 106 to provide electrical and/or thermal paths to the PCB or the system level cooling. After fan-out wafer level integration is finished by formation of the solder balls 302 of the ball grid array (FIG. 6K) and the integrated CSP package modules are singulated by a wafer sawing process (FIG. 6L).
[0037] Mold thickness and thermal conductivity play a large role in the package's thermal resistance junction-to-case (theta-JC) in both top and bottom directions. Results of dual-side cooling thermal performance simulations are shown in FIG. 7, comprising FIGs. 7A, 7B, 7C and 7D. FIG. 7 depicts graphs 700 (FIG. 7A), 720 (FIG. 7B), 740 (FIG. 7C), 760 (FIG. 7D) of dual-side cooling thermal management in relation to mold thermal conductivity and package thickness in accordance with the present embodiment as measured in the thermal performance simulations where an isothermal cooling boundary condition was added to the top side of the molded surface and the system's ambient temperature was set to 85°C. In the graphs 700, 720, 740, 760, mold thermal conductivity is plotted along the x-axis 702, 722, 742, 762 and thermal resistance is plotted along the y-axis 704, 724, 744, 764.
[0038] The graph 700 depicts dual-side cooling thermal management when using a low conductive mold. The thermal resistance of the bottom of the die -junction at mold thicknesses from 0.5mm to 0.7mm for a die-attach thermal conductivity of 30W/mK (dotted trace 710) and a die- attach thermal conductivity of 2W/mK (dotted trace 712) shows that increasing the mold thickness can make a slight increase in thermal resistance. However, the thermal resistance of the top of the die -junction at mold thicknesses from 0.5mm to 0.7mm for a die-attach thermal conductivity of 30W/mK (solid trace 714) and a die-attach thermal conductivity of 2W/mK (solid trace 716) shows that increasing the mold thickness can make a greater increase in thermal resistance. The graph 720 depicts dual-side cooling thermal management when using a high conductive mold. Similar mold thickness variations can be seen at the bottom of the die -junction (thermal conductivity of 30W/mK (dotted trace 730) and thermal conductivity of 2W/mK (dotted trace 732)) and the top of the die-junction (thermal conductivity of 30W/mK (solid trace 734) and thermal conductivity of 2W/mK (solid trace 736)). [0039] The graph 740 depicts dual-side cooling thermal management when using a thin mold. The thermal resistance of the bottom of the die -junction at mold thermal conductivities from l.OW/mK to 3.0W/mK for a die-attach thermal conductivity of 30W/mK (dotted trace 750) and a die-attach thermal conductivity of 2W/mK (dotted trace 752) shows that increasing the mold thermal conductivity can make a slight decrease in thermal resistance. However, the thermal resistance of the top of the die- junction at mold thermal conductivities from l.OW/mK to 3.0W/mK for a die-attach thermal conductivity of 30W/mK (solid trace 754) and a die-attach thermal conductivity of 2W/mK (solid trace 756) shows that increasing the mold thermal conductivity can make a greater decrease in thermal resistance. The graph 760 depicts dual-side cooling thermal management when using a thick mold. Similar mold thermal conductivity variations can be seen at the bottom of the die -junction (thermal conductivity of 30W/mK (dotted trace 770) and thermal conductivity of 2W/mK (dotted trace 772)) and the top of the die -junction (thermal conductivity of 30W/mK (solid trace 774) and thermal conductivity of 2W/mK (solid trace 776)).
[0040] Thus it can be seen from the graphs 700, 720, 740, 760 that increasing mold thermal conductivity and decreasing mold thickness can reduce theta-JC by up to 38% in the top direction and up to 30% in the bottom direction. Increasing die attach conductivity can decrease theta-JC by up to 18% in the top direction and 90% in the bottom direction. However, it can also be seen that beyond a die-attach thermal conductivity of 30W/mK there are diminishing returns for thermal performance.
[0041] Referring to FIG. 8, thermal management by dual-side cooling versus thermal management by bottom-only cooling in accordance with the present embodiment is depicted in an illustration 800 (FIG. 8A) depicting dual-side cooling temperatures at a die-junction 802 and an illustration 850 (FIG. 8B) depicting bottom- only cooling temperatures at a die-junction 852. When compared with bottom-only cooling, despite bottom-only cooling set to a lower fixed temperature (25°C) vs the dual-sided cooling (85°C) as shown in the illustrations 850, 800, the die-junction temperature is cooler for dual-sided cooling (99°C vs 121°C). This cooling is due to air bottleneck removal at the power module top-side as a result of the structure of the semiconductor package module in accordance with the present embodiment.
[0042] Thus, the present embodiment provides a novel and advantageous semiconductor package design and fabrication method for wafer level integrated Si based CMOS driver devices and high power switching devices. The active components, along with passive components can be integrated at the wafer level using fan-out wafer level integration. Using first wafer level molding and first RDL defining, integration of the CMOS driver IC, the GaN high power devices, and passive components in a single 3D integrated semiconductor package module can be achieved no matter what the size ratio of the components. The system level package integration in accordance with the present embodiment can be either QFN lead frame style or BGA style and the wafer level packaging in accordance with the present embodiment provides a scalable, cost effective wafer level system integration package. The semiconductor package modules in accordance with the present embodiment provide enhanced thermal performance by utilizing a double side cooling design, especially for the GaN device backsides which can additionally be interconnected to board level thermal dissipation paths through copper heat spreader and/or solder ball interconnections. Modules and fabrication methods in accordance with the present embodiment enable cost effective heterogeneous wafer level processing with a highly miniaturized structure having heightened efficiency in view of thermal electrical and mechanical reliability, thereby providing reliable, cost effective, scalable solutions for automotive motor control, generator power inversion, aerospace high power devices, home appliances and other high-power control applications.
[0043] It should further be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, operation, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements and method of operation described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims.

Claims

CLAIMS What is claimed is:
1. A semiconductor package module comprising:
a substrate;
a driver integrated circuit (IC);
one or more power switching devices, each of the one or more switching devices physically integrated in the semiconductor package module at a wafer level and having a gate connected to the driver IC by a gate-to-driver interconnection; and one or more highly conductive clips, wherein each of the one or more highly conductive clips is connected to a source of a corresponding one of the one or more power switching devices by a source-to-clip interconnection, and wherein each of the one or more highly conductive clips has a first surface planarly located in the semiconductor package with a similar first surface of the driver IC for co-bonding of the source-to-clip interconnections and the gate-to-driver interconnections.
2. The semiconductor package module in accordance with Claim 1 wherein the gate-to-driver interconnections comprise micro-bumps or copper pillars.
3. The semiconductor package module in accordance with Claim 1 further comprising a redistribution layer (RDL) formed in the substrate, the source-to- clip interconnections formed in the RDL.
4. The semiconductor package module in accordance with Claim 2 wherein the gate-to-driver interconnections are also formed in the RDL.
5. The semiconductor package module in accordance with Claim 1 further comprising one or more first thermal management devices, wherein each of the one or more first thermal management devices is connected to a corresponding one of the one or more power switching devices by a drain-to-pad interconnection.
6. The semiconductor package module in accordance with Claim 5 further comprising a redistribution layer (RDL) formed in the substrate, the gate-to- driver interconnections, the source-to-clip interconnections and the drain-to-pad interconnections formed in the RDL.
7. The semiconductor package module in accordance with Claim 5 wherein each of the drain-to-pad interconnections comprises a shortened thermal dissipation path for direct interconnect of each of the one or more first thermal management devices to the corresponding one of the one or more power switching devices.
8. The semiconductor package module in accordance with Claim 5 wherein each of the one or more first thermal management devices comprises a heat spreader connected to the corresponding one of the one or more power switching devices, each heat spreader also serving as a pad for the semiconductor package.
9. The semiconductor package module in accordance with Claim 5 further comprising one or more second thermal management devices connected to the driver IC, wherein each of the one or more first thermal management devices comprises an active thermoelectric cooler (TEC) device or a heat spreader.
10. The semiconductor package module in accordance with Claim 9 each of the one or more first thermal management devices comprises an active thermoelectric cooler (TEC) device selected from the group comprising a Peltier cooler, a heater, and a solid-state active heat pump.
11. The semiconductor package module in accordance with Claim 1 further comprising a QFN lead frame or a ball grid array (BGA) for physically and electrically connecting the semiconductor package module to external devices.
12. The semiconductor package module in accordance with Claim 1 wherein the one or more highly conductive clips comprise one or more embedded copper clips.
13. A semiconductor high power package fabrication method for wafer level device integration comprising:
CMOS fabrication of a CMOS device and one or more highly conductive clips such that a first surface of each of the one or more highly conductive clips is planarly located with a similar first surface of the CMOS device; and
thereafter co-bonding a source-to-clip interconnection between each of one or more high power devices and a corresponding one of the one or more highly conductive clips simultaneously with a gate-to-driver interconnection between the one or more high power devices and the CMOS device.
14. The method in accordance with Claim 13 wherein the CMOS device is a CMOS driver integrated circuit (IC) and the high power device is a gallium nitride power switching device.
15. The method in accordance with Claim 13 further comprising connecting passive components to second surfaces of the one or more highly conductive clips, and wherein the step of providing the highly conductive clips comprises providing the highly conductive clips interconnected with the passive components.
16. The method in accordance with Claim 13 further comprising directly connecting the each of the one or more high power devices to a thermal management device for thermal and electrical connection of the one or more high power devices with external thermal dissipation paths.
17. The method in accordance with Claim 13 further comprising connecting a bottom substrate to each of the one or more high power devices for external interconnection of the semiconductor high power package.
18. The method in accordance with Claim 17 wherein the bottom substrate comprises a lead frame or a redistribution layer.
19. The method in accordance with Claim 15 wherein the step of connecting passive components comprises connecting the passive components to the one or more highly conductive clips is performed during the step of CMOS fabrication.
20. The method in accordance with Claim 19 wherein the step of connecting the passive components to the one or more highly conductive clips during the step of CMOS fabrication comprises connecting the passive components to the one or more highly conductive clips during a CMOS device fan-out molding step of the CMOS fabrication.
PCT/SG2016/050577 2015-11-23 2016-11-23 Wafer level integration of high power switching devices on cmos driver integrated circuit WO2017091152A1 (en)

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CN113316841A (en) * 2018-12-20 2021-08-27 Qorvo美国公司 Electronic package arrangement and related method
WO2022025821A1 (en) * 2020-07-30 2022-02-03 Agency For Science, Technology And Research Power module package and method of forming the same

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