DE69528961T2 - Verfahren zur Herstellung von intergrierten Schaltungen mit Hochspannungs- und Niederspannungs-lateralen-DMOS-Leistungsbauelementen und nichtflüchtigen Speicherzellen - Google Patents

Verfahren zur Herstellung von intergrierten Schaltungen mit Hochspannungs- und Niederspannungs-lateralen-DMOS-Leistungsbauelementen und nichtflüchtigen Speicherzellen

Info

Publication number
DE69528961T2
DE69528961T2 DE69528961T DE69528961T DE69528961T2 DE 69528961 T2 DE69528961 T2 DE 69528961T2 DE 69528961 T DE69528961 T DE 69528961T DE 69528961 T DE69528961 T DE 69528961T DE 69528961 T2 DE69528961 T2 DE 69528961T2
Authority
DE
Germany
Prior art keywords
regions
dopant
power devices
lateral dmos
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69528961T
Other languages
English (en)
Other versions
DE69528961D1 (de
Inventor
Claudio Contiero
Paola Galbiati
Michele Palmieri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69528961D1 publication Critical patent/DE69528961D1/de
Application granted granted Critical
Publication of DE69528961T2 publication Critical patent/DE69528961T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69528961T 1995-03-09 1995-03-09 Verfahren zur Herstellung von intergrierten Schaltungen mit Hochspannungs- und Niederspannungs-lateralen-DMOS-Leistungsbauelementen und nichtflüchtigen Speicherzellen Expired - Fee Related DE69528961T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95830088A EP0731504B1 (de) 1995-03-09 1995-03-09 Verfahren zur Herstellung von intergrierten Schaltungen mit Hochspannungs- und Niederspannungs-lateralen-DMOS-Leistungsbauelementen und nichtflüchtigen Speicherzellen

Publications (2)

Publication Number Publication Date
DE69528961D1 DE69528961D1 (de) 2003-01-09
DE69528961T2 true DE69528961T2 (de) 2003-09-04

Family

ID=8221873

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69528961T Expired - Fee Related DE69528961T2 (de) 1995-03-09 1995-03-09 Verfahren zur Herstellung von intergrierten Schaltungen mit Hochspannungs- und Niederspannungs-lateralen-DMOS-Leistungsbauelementen und nichtflüchtigen Speicherzellen

Country Status (4)

Country Link
US (1) US6022778A (de)
EP (1) EP0731504B1 (de)
JP (1) JP2987098B2 (de)
DE (1) DE69528961T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004001713A1 (de) * 2004-01-13 2005-08-04 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung einer EPROM-Speicherzelle in einer BiCMOS-Technologie

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0789401A3 (de) * 1995-08-25 1998-09-16 Matsushita Electric Industrial Co., Ltd. LD-MOSFET oder MOSFET mit einer diese enthaltenden integrierten Schaltung und Verfahren zur Herstellung
KR100220252B1 (ko) * 1996-12-28 1999-09-15 김영환 반도체 소자의 제조방법
JP3196714B2 (ja) * 1998-03-05 2001-08-06 日本電気株式会社 トリプルウェル構造の半導体集積回路の製造方法
JP2000077532A (ja) 1998-09-03 2000-03-14 Mitsubishi Electric Corp 半導体装置およびその製造方法
EP0986100B1 (de) * 1998-09-11 2010-05-19 STMicroelectronics Srl Elektronisches Bauteil mit EEPROM-Speicherzellen, Hochspannungstransistoren und Niederspannungstransistoren mit Silizidanschlüssen, sowie Herstellungsverfahren desselben
EP0996152A1 (de) * 1998-10-23 2000-04-26 STMicroelectronics S.r.l. Herstellungsverfahren für elektronische Bauelemente mit Festwertspeicherzellen und Hochspannungstransistoren die alle unsiliziert sind, sowie Niederspannungstransistoren die einen selbstjustierten Silizidübergang aufweisen
US6114194A (en) * 1998-11-17 2000-09-05 United Microelectronics Corp. Method for fabricating a field device transistor
US6174778B1 (en) * 1998-12-15 2001-01-16 United Microelectronics Corp. Method of fabricating metal oxide semiconductor
EP1045440A1 (de) * 1999-04-14 2000-10-18 STMicroelectronics S.r.l. Herstellungsverfahren von Festwertspeichern mit elektrischer Kontinuität gemeinsamer Source-Leitungen
JP2000340684A (ja) * 1999-05-31 2000-12-08 Sony Corp 半導体装置の製造方法
US6287920B1 (en) * 1999-09-07 2001-09-11 Texas Instruments Incorporated Method of making multiple threshold voltage integrated of circuit transistors
US6849491B2 (en) * 2001-09-28 2005-02-01 Dalsa Semiconductor Inc. Method of making high-voltage bipolar/CMOS/DMOS (BCD) devices
KR100867572B1 (ko) * 2002-03-09 2008-11-10 페어차일드코리아반도체 주식회사 고전압 섬 영역 내에 바이폴라 트랜지스터가 내장된고전압 집적 회로
JP2005039125A (ja) * 2003-07-17 2005-02-10 Renesas Technology Corp 半導体可変容量ダイオードおよび半導体装置の製造方法
US8253196B2 (en) 2004-01-29 2012-08-28 Enpirion, Inc. Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same
US7230302B2 (en) 2004-01-29 2007-06-12 Enpirion, Inc. Laterally diffused metal oxide semiconductor device and method of forming the same
DE102004043284A1 (de) * 2004-09-08 2006-03-23 X-Fab Semiconductor Foundries Ag DMOS-Transistor für hohe Drain- und Sourcespannungen
US7208795B2 (en) * 2005-05-24 2007-04-24 Atmel Corporation Low-cost, low-voltage single-layer polycrystalline EEPROM memory cell integration into BiCMOS technology
KR100732759B1 (ko) * 2005-06-22 2007-06-27 주식회사 하이닉스반도체 반도체 소자의 비트라인 및 그 형성 방법
EP1804285B1 (de) * 2005-12-27 2018-10-24 Semiconductor Components Industries, LLC Verfahren zur Herstellung eines Transistors mit selbstausgerichtetem Kanal
US7544558B2 (en) * 2006-03-13 2009-06-09 Bcd Semiconductor Manufacturing Limited Method for integrating DMOS into sub-micron CMOS process
CN100466256C (zh) * 2006-08-07 2009-03-04 崇贸科技股份有限公司 高压集成电路
KR100917216B1 (ko) * 2007-02-02 2009-09-16 삼성전자주식회사 반도체 소자 및 그 형성방법
US7727838B2 (en) * 2007-07-27 2010-06-01 Texas Instruments Incorporated Method to improve transistor Tox using high-angle implants with no additional masks
JP4956351B2 (ja) * 2007-09-28 2012-06-20 オンセミコンダクター・トレーディング・リミテッド Ｄｍｏｓトランジスタの製造方法
US8125051B2 (en) * 2008-07-03 2012-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Device layout for gate last process
US8610220B2 (en) * 2012-05-16 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with self-aligned interconnects
EP2738807A3 (de) 2012-11-30 2017-01-11 Enpirion, Inc. Vorrichtung mit einer an eine Entkopplungsvorrichtung gekoppelte Halbleitervorrichtung
US9536938B1 (en) 2013-11-27 2017-01-03 Altera Corporation Semiconductor device including a resistor metallic layer and method of forming the same
US10020739B2 (en) 2014-03-27 2018-07-10 Altera Corporation Integrated current replicator and method of operating the same
US9673192B1 (en) 2013-11-27 2017-06-06 Altera Corporation Semiconductor device including a resistor metallic layer and method of forming the same
US20150200295A1 (en) * 2014-01-10 2015-07-16 Cypress Semiconductor Corporation Drain Extended MOS Transistors With Split Channel
CN104851803A (zh) * 2014-02-17 2015-08-19 无锡华润上华半导体有限公司 横向扩散金属氧化物半导体器件的制造方法
CN105374686A (zh) * 2014-09-02 2016-03-02 无锡华润上华半导体有限公司 一种ldmos器件的制作方法
US10103627B2 (en) 2015-02-26 2018-10-16 Altera Corporation Packaged integrated circuit including a switch-mode regulator and method of forming the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4417385A (en) * 1982-08-09 1983-11-29 General Electric Company Processes for manufacturing insulated-gate semiconductor devices with integral shorts
JPS59106152A (ja) * 1982-12-10 1984-06-19 Nec Corp 半導体装置
JPS6464365A (en) * 1987-09-04 1989-03-10 Nec Corp Semiconductor integrated circuit device
US5057448A (en) * 1988-02-26 1991-10-15 Hitachi, Ltd. Method of making a semiconductor device having DRAM cells and floating gate memory cells
JPH02143454A (ja) * 1988-11-25 1990-06-01 Hitachi Ltd 半導体デバイス
JPH03105971A (ja) * 1989-09-20 1991-05-02 Hitachi Ltd 半導体集積回路装置
US5045492A (en) * 1989-09-25 1991-09-03 Allegro Microsystems, Inc. Method of making integrated circuit with high current transistor and CMOS transistors
JP2909760B2 (ja) * 1990-06-07 1999-06-23 セイコーインスツルメンツ株式会社 Ｄｍｏｓｆｅｔの製造方法
JP2632101B2 (ja) * 1990-11-05 1997-07-23 三菱電機株式会社 半導体装置の製造方法
US5296393A (en) * 1990-11-23 1994-03-22 Texas Instruments Incorporated Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods
JPH05211358A (ja) * 1991-12-19 1993-08-20 Nec Corp ガラス基板の製造方法
DE69429915D1 (de) * 1994-07-04 2002-03-28 St Microelectronics Srl Verfahren zur Herstellung von Leistungsbauteilen hoher Dichte in MOS-Technologie

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004001713A1 (de) * 2004-01-13 2005-08-04 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung einer EPROM-Speicherzelle in einer BiCMOS-Technologie
DE102004001713B4 (de) * 2004-01-13 2005-12-01 X-Fab Semiconductor Foundries Ag Herstellung von EPROM-Zellen in BiCMOS-Technologie

Also Published As

Publication number Publication date
EP0731504A1 (de) 1996-09-11
US6022778A (en) 2000-02-08
JP2987098B2 (ja) 1999-12-06
DE69528961D1 (de) 2003-01-09
JPH08321556A (ja) 1996-12-03
EP0731504B1 (de) 2002-11-27

Similar Documents

Publication Publication Date Title
DE69528961T2 (de) Verfahren zur Herstellung von intergrierten Schaltungen mit Hochspannungs- und Niederspannungs-lateralen-DMOS-Leistungsbauelementen und nichtflüchtigen Speicherzellen
US6809383B2 (en) Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure
US4705759A (en) High power MOSFET with low on-resistance and high breakdown voltage
US4314857A (en) Method of making integrated CMOS and CTD by selective implantation
KR980013095A (ko) 플레쉬 이이피롬(eeprom) 장치 및 그 제조방법
ATE170668T1 (de) Spannungsdurchbruchfeste halbleiterbauelemente aus einkristall-siliziumkarbid und verfahren zu deren herstellung
ITMI972399A1 (it) Processo per la fabbricazione di dispositivo a gate mos con celle autoallineate
DE3071648D1 (en) Process for producing a high-density integrated read-only memory
KR930000605B1 (ko) 절연 게이트 mosfet의 제조방법
KR960026463A (ko) 모스 전계 효과 트랜지스터(mosfet) 제조 방법
KR970053087A (ko) 반도체 소자의 트랜지스터 제조방법
KR100650901B1 (ko) 매립 게이트를 갖는 금속 산화물 반도체 트랜지스터
JPS5662333A (en) Mos type semiconductor memory device and production thereof
JPS6433970A (en) Field effect semiconductor device
JPS56125875A (en) Semiconductor integrated circuit device
JPS56104473A (en) Semiconductor memory device and manufacture thereof
JPS6448464A (en) Semiconductor device
JPS56115558A (en) Semiconductor integrated circuit and manufacture thereof
KR970018259A (ko) 반도체 소자의 트랜지스터 제조방법
JPS57102073A (en) Semiconductor memory and manufacture thereof
KR100248824B1 (ko) 플래시 메모리 장치 및 그 제조 방법
JPS61292318A (ja) 半導体装置の製造方法
JPS57202773A (en) Silicon integrated circuit device
JPS63142866A (ja) 絶縁ゲ−ト電界効果トランジスタの製造方法
JPS5511307A (en) Method of manufacturing semiconductor integrated circuit

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee