DE69429915D1 - Verfahren zur Herstellung von Leistungsbauteilen hoher Dichte in MOS-Technologie - Google Patents

Verfahren zur Herstellung von Leistungsbauteilen hoher Dichte in MOS-Technologie

Info

Publication number
DE69429915D1
DE69429915D1 DE69429915T DE69429915T DE69429915D1 DE 69429915 D1 DE69429915 D1 DE 69429915D1 DE 69429915 T DE69429915 T DE 69429915T DE 69429915 T DE69429915 T DE 69429915T DE 69429915 D1 DE69429915 D1 DE 69429915D1
Authority
DE
Germany
Prior art keywords
production
power components
mos technology
density power
density
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69429915T
Other languages
English (en)
Inventor
Giuseppe Ferla
Ferruccio Frisina
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Original Assignee
STMicroelectronics SRL
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69429915D1 publication Critical patent/DE69429915D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/126—Power FETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69429915T 1994-07-04 1994-07-04 Verfahren zur Herstellung von Leistungsbauteilen hoher Dichte in MOS-Technologie Expired - Lifetime DE69429915D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830331A EP0696054B1 (de) 1994-07-04 1994-07-04 Verfahren zur Herstellung von Leistungsbauteilen hoher Dichte in MOS-Technologie

Publications (1)

Publication Number Publication Date
DE69429915D1 true DE69429915D1 (de) 2002-03-28

Family

ID=8218487

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69429915T Expired - Lifetime DE69429915D1 (de) 1994-07-04 1994-07-04 Verfahren zur Herstellung von Leistungsbauteilen hoher Dichte in MOS-Technologie

Country Status (4)

Country Link
US (2) US5670392A (de)
EP (1) EP0696054B1 (de)
JP (1) JP3032138B2 (de)
DE (1) DE69429915D1 (de)

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US5798554A (en) * 1995-02-24 1998-08-25 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno MOS-technology power device integrated structure and manufacturing process thereof
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EP0768714B1 (de) * 1995-10-09 2003-09-17 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Herstellungsverfahren für Leistungsanordnung mit Schutzring
EP0772242B1 (de) * 1995-10-30 2006-04-05 STMicroelectronics S.r.l. Leistungsbauteil in MOS-Technologie mit einer einzelnen kritischen Grösse
EP0772241B1 (de) * 1995-10-30 2004-06-09 STMicroelectronics S.r.l. Leistungsbauteil hoher Dichte in MOS-Technologie
US6228719B1 (en) 1995-11-06 2001-05-08 Stmicroelectronics S.R.L. MOS technology power device with low output resistance and low capacitance, and related manufacturing process
EP0772244B1 (de) * 1995-11-06 2000-03-22 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Leistungsbauelement in MOS-Technologie mit niedrigem Ausgangswiderstand und geringer Kapazität und dessen Herstellungsverfahren
DE69518653T2 (de) * 1995-12-28 2001-04-19 St Microelectronics Srl MOS-Technologie-Leistungsanordnung in integrierter Struktur
US5913130A (en) * 1996-06-12 1999-06-15 Harris Corporation Method for fabricating a power device
EP0817247A1 (de) * 1996-06-26 1998-01-07 STMicroelectronics S.r.l. Verfahren zur Herstellung von integrierten Schaltkreisen mit zu den aktiven Gebieten selbstjustierten Kontakten
EP0841702A1 (de) * 1996-11-11 1998-05-13 STMicroelectronics S.r.l. Lateraler oder vertikaler DMOSFET mit hoher Durchbruchspannung
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DE69839439D1 (de) 1998-05-26 2008-06-19 St Microelectronics Srl MOS-Technologie-Leistungsanordnung mit hoher Integrationsdichte
US6312997B1 (en) 1998-08-12 2001-11-06 Micron Technology, Inc. Low voltage high performance semiconductor devices and methods
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EP1009036B1 (de) * 1998-12-09 2007-09-19 STMicroelectronics S.r.l. Leistungsbauelement mit MOS-Gate für hohe Spannungen und diesbezügliches Herstellungsverfahren
US6211018B1 (en) * 1999-08-14 2001-04-03 Electronics And Telecommunications Research Institute Method for fabricating high density trench gate type power device
EP1187220A3 (de) * 2000-09-11 2007-10-10 Kabushiki Kaisha Toshiba MOS-Feldeffekttransistor mit reduziertem Anschaltwiderstand
US6509241B2 (en) 2000-12-12 2003-01-21 International Business Machines Corporation Process for fabricating an MOS device having highly-localized halo regions
US6882053B1 (en) 2001-12-28 2005-04-19 Micrel, Inc. Buried power buss utilized as a ground strap for high current, high power semiconductor devices and a method for providing the same
US7183193B2 (en) * 2001-12-28 2007-02-27 Micrel, Inc. Integrated device technology using a buried power buss for major device and circuit advantages
US6894393B1 (en) 2001-12-28 2005-05-17 Micrel, Inc. Buried power bus utilized as a sinker for high current, high power semiconductor devices and a method for providing the same
EP1420457B1 (de) * 2002-11-14 2012-01-11 STMicroelectronics Srl Herstellungsverfahren eines Leistungs-Halbleiterbauelements mit isoliertem Gate und mit Schottky-Diode
US6864145B2 (en) * 2003-06-30 2005-03-08 Intel Corporation Method of fabricating a robust gate dielectric using a replacement gate flow
KR100538101B1 (ko) * 2004-07-07 2005-12-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR100687108B1 (ko) * 2005-05-31 2007-02-27 라이톤 세미컨덕터 코퍼레이션 기생 바이폴라 트랜지스터의 턴온을 억제할 수 있는 고전력반도체 소자
US6965146B1 (en) * 2004-11-29 2005-11-15 Silicon-Based Technology Corp. Self-aligned planar DMOS transistor structure and its manufacturing methods
EP1742271A1 (de) * 2005-07-08 2007-01-10 STMicroelectronics S.r.l. Leistungsfeldeffekttransistor und Verfahren zu seiner Herstellung
KR100760010B1 (ko) 2006-09-04 2007-09-19 주식회사 파워디바이스 시간에 따른 전압의 변화율 특성을 향상시킨 전력 반도체소자
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CN102820338B (zh) * 2008-02-06 2016-05-11 罗姆股份有限公司 半导体装置
US9087774B2 (en) * 2013-09-26 2015-07-21 Monolithic Power Systems, Inc. LDMOS device with short channel and associated fabrication method
DE102016114389B3 (de) * 2016-08-03 2017-11-23 Infineon Technologies Austria Ag Halbleitervorrichtung mit Driftzone und rückseitigem Emitter und Verfahren zur Herstellung
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Also Published As

Publication number Publication date
JP3032138B2 (ja) 2000-04-10
EP0696054A1 (de) 1996-02-07
US5670392A (en) 1997-09-23
US6369425B1 (en) 2002-04-09
JPH0897168A (ja) 1996-04-12
EP0696054B1 (de) 2002-02-20

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