DE69429913D1 - Verfahren zur Herstellung eines Leistungsbauteils in MOS-Technik - Google Patents

Verfahren zur Herstellung eines Leistungsbauteils in MOS-Technik

Info

Publication number
DE69429913D1
DE69429913D1 DE69429913T DE69429913T DE69429913D1 DE 69429913 D1 DE69429913 D1 DE 69429913D1 DE 69429913 T DE69429913 T DE 69429913T DE 69429913 T DE69429913 T DE 69429913T DE 69429913 D1 DE69429913 D1 DE 69429913D1
Authority
DE
Germany
Prior art keywords
production
power component
mos technology
mos
technology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69429913T
Other languages
English (en)
Other versions
DE69429913T2 (de
Inventor
Giuseppe Ferla
Ferruccio Frisina
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Original Assignee
STMicroelectronics SRL
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno filed Critical STMicroelectronics SRL
Publication of DE69429913D1 publication Critical patent/DE69429913D1/de
Application granted granted Critical
Publication of DE69429913T2 publication Critical patent/DE69429913T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69429913T 1994-06-23 1994-06-23 Verfahren zur Herstellung eines Leistungsbauteils in MOS-Technik Expired - Fee Related DE69429913T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830315A EP0689238B1 (de) 1994-06-23 1994-06-23 Verfahren zur Herstellung eines Leistungsbauteils in MOS-Technik

Publications (2)

Publication Number Publication Date
DE69429913D1 true DE69429913D1 (de) 2002-03-28
DE69429913T2 DE69429913T2 (de) 2002-10-31

Family

ID=8218475

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69429913T Expired - Fee Related DE69429913T2 (de) 1994-06-23 1994-06-23 Verfahren zur Herstellung eines Leistungsbauteils in MOS-Technik

Country Status (4)

Country Link
US (1) US5874338A (de)
EP (1) EP0689238B1 (de)
JP (1) JPH0817848A (de)
DE (1) DE69429913T2 (de)

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FR2767964B1 (fr) * 1997-09-04 2001-06-08 St Microelectronics Sa Procede de realisation de la zone de canal d'un transistor dmos
US6492232B1 (en) 1998-06-15 2002-12-10 Motorola, Inc. Method of manufacturing vertical semiconductor device
EP0993033A1 (de) * 1998-10-06 2000-04-12 STMicroelectronics S.r.l. Gate-Isolierungsstruktur für Leistungs-MOS-Transistor und Herstellungsverfahren dafür
US6207508B1 (en) * 1999-08-03 2001-03-27 Stmicroelectronics, Inc. Method for fabricating a radio frequency power MOSFET device having improved performance characteristics
US7701001B2 (en) * 2002-05-03 2010-04-20 International Rectifier Corporation Short channel trench power MOSFET with low threshold voltage
WO2008087763A1 (ja) * 2007-01-16 2008-07-24 Panasonic Corporation 半導体装置およびその製造方法
CN101630683B (zh) * 2008-07-15 2011-03-23 中芯国际集成电路制造(上海)有限公司 集成静电放电器件
JP2011086643A (ja) * 2009-10-13 2011-04-28 Panasonic Corp 不純物注入方法及びイオン注入装置
US9337270B2 (en) * 2013-12-19 2016-05-10 Infineon Technologies Ag Semiconductor device
US9337185B2 (en) * 2013-12-19 2016-05-10 Infineon Technologies Ag Semiconductor devices
JP2015008328A (ja) * 2014-09-09 2015-01-15 株式会社東芝 半導体装置
TWI655746B (zh) * 2015-05-08 2019-04-01 創意電子股份有限公司 二極體與二極體串電路

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JPH0766968B2 (ja) * 1987-08-24 1995-07-19 株式会社日立製作所 半導体装置及びその製造方法
JPH0828506B2 (ja) * 1988-11-07 1996-03-21 三菱電機株式会社 半導体装置およびその製造方法
JPH02239670A (ja) * 1989-03-14 1990-09-21 Fujitsu Ltd 半導体装置
JPH02312280A (ja) * 1989-05-26 1990-12-27 Mitsubishi Electric Corp 絶縁ゲート型バイポーラトランジスタ
JPH0334468A (ja) * 1989-06-30 1991-02-14 Hitachi Ltd 絶縁ゲート型電界効果半導体装置及び製造法
TW399774U (en) * 1989-07-03 2000-07-21 Gen Electric FET, IGBT and MCT structures to enhance operating characteristics
JP2949745B2 (ja) * 1990-01-19 1999-09-20 日本電気株式会社 縦型ｍｏｓ電界効果トランジスタの製造方法
EP0481153B1 (de) * 1990-10-16 1997-02-12 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Verfahren zur Herstellung von MOS-Leistungstransistoren mit vertikalem Strom

Also Published As

Publication number Publication date
US5874338A (en) 1999-02-23
EP0689238A1 (de) 1995-12-27
DE69429913T2 (de) 2002-10-31
JPH0817848A (ja) 1996-01-19
EP0689238B1 (de) 2002-02-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee