DE69029942T2 - Verfahren zur Herstellung von MOS-Leistungstransistoren mit vertikalem Strom - Google Patents

Verfahren zur Herstellung von MOS-Leistungstransistoren mit vertikalem Strom

Info

Publication number
DE69029942T2
DE69029942T2 DE69029942T DE69029942T DE69029942T2 DE 69029942 T2 DE69029942 T2 DE 69029942T2 DE 69029942 T DE69029942 T DE 69029942T DE 69029942 T DE69029942 T DE 69029942T DE 69029942 T2 DE69029942 T2 DE 69029942T2
Authority
DE
Germany
Prior art keywords
power transistors
vertical current
mos power
current mos
manufacturing vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69029942T
Other languages
English (en)
Other versions
DE69029942D1 (de
Inventor
Raffaele Zambrano
Carmelo Magro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Original Assignee
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno, SGS Thomson Microelectronics SRL filed Critical CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Publication of DE69029942D1 publication Critical patent/DE69029942D1/de
Application granted granted Critical
Publication of DE69029942T2 publication Critical patent/DE69029942T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/126—Power FETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69029942T 1990-10-16 1990-10-16 Verfahren zur Herstellung von MOS-Leistungstransistoren mit vertikalem Strom Expired - Fee Related DE69029942T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP90830462A EP0481153B1 (de) 1990-10-16 1990-10-16 Verfahren zur Herstellung von MOS-Leistungstransistoren mit vertikalem Strom

Publications (2)

Publication Number Publication Date
DE69029942D1 DE69029942D1 (de) 1997-03-27
DE69029942T2 true DE69029942T2 (de) 1997-08-28

Family

ID=8206028

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69029942T Expired - Fee Related DE69029942T2 (de) 1990-10-16 1990-10-16 Verfahren zur Herstellung von MOS-Leistungstransistoren mit vertikalem Strom

Country Status (4)

Country Link
US (2) US5382538A (de)
EP (1) EP0481153B1 (de)
JP (1) JP3205361B2 (de)
DE (1) DE69029942T2 (de)

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DE59504562D1 (de) * 1994-03-04 1999-01-28 Siemens Ag Mis-struktur auf siliciumcarbid-basis mit hoher latch-up-festigkeit
EP0689239B1 (de) * 1994-06-23 2007-03-07 STMicroelectronics S.r.l. Verfahren zur Herstellung von Leistungsbauteilen in MOS-Technologie
EP0689238B1 (de) * 1994-06-23 2002-02-20 STMicroelectronics S.r.l. Verfahren zur Herstellung eines Leistungsbauteils in MOS-Technik
EP0696054B1 (de) * 1994-07-04 2002-02-20 STMicroelectronics S.r.l. Verfahren zur Herstellung von Leistungsbauteilen hoher Dichte in MOS-Technologie
US5798554A (en) * 1995-02-24 1998-08-25 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno MOS-technology power device integrated structure and manufacturing process thereof
EP0735591B1 (de) * 1995-03-31 1999-09-08 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno DMOS-Anordnung-Struktur und Verfahren zur Herstellung
US5777362A (en) * 1995-06-07 1998-07-07 Harris Corporation High efficiency quasi-vertical DMOS in CMOS or BICMOS process
US5719423A (en) * 1995-08-31 1998-02-17 Texas Instruments Incorporated Isolated power transistor
EP0768714B1 (de) * 1995-10-09 2003-09-17 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Herstellungsverfahren für Leistungsanordnung mit Schutzring
DE69534919T2 (de) 1995-10-30 2007-01-25 Stmicroelectronics S.R.L., Agrate Brianza Leistungsvorrichtung in MOS-Technologie mit einer einzigen kritischen Größe
EP0772241B1 (de) * 1995-10-30 2004-06-09 STMicroelectronics S.r.l. Leistungsbauteil hoher Dichte in MOS-Technologie
US6228719B1 (en) 1995-11-06 2001-05-08 Stmicroelectronics S.R.L. MOS technology power device with low output resistance and low capacitance, and related manufacturing process
DE69515876T2 (de) * 1995-11-06 2000-08-17 St Microelectronics Srl Leistungsbauelement in MOS-Technologie mit niedrigem Ausgangswiderstand und geringer Kapazität und dessen Herstellungsverfahren
EP0782201B1 (de) * 1995-12-28 2000-08-30 STMicroelectronics S.r.l. MOS-Technologie-Leistungsanordnung in integrierter Struktur
JPH09248912A (ja) * 1996-01-11 1997-09-22 Canon Inc インクジェットヘッド及びヘッド用基体、インクジェットカートリッジ、並びにインクジェット装置
EP1895595B8 (de) * 1996-10-18 2013-11-06 Hitachi, Ltd. Halbleitervorrichtung und elektrische Stromwandlervorrichtung
EP0961325B1 (de) 1998-05-26 2008-05-07 STMicroelectronics S.r.l. MOS-Technologie-Leistungsanordnung mit hoher Integrationsdichte
EP1009036B1 (de) * 1998-12-09 2007-09-19 STMicroelectronics S.r.l. Leistungsbauelement mit MOS-Gate für hohe Spannungen und diesbezügliches Herstellungsverfahren
ITVA20010045A1 (it) * 2001-12-14 2003-06-16 St Microelectronics Srl Flusso di processo per la realizzazione di un vdmos a canale scalato e basso gradiente di body per prestazioni ad elevata densita' di corren
US6656845B2 (en) * 2002-02-15 2003-12-02 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming semiconductor substrate with convex shaped active region
KR100873419B1 (ko) * 2002-06-18 2008-12-11 페어차일드코리아반도체 주식회사 높은 항복 전압, 낮은 온 저항 및 작은 스위칭 손실을갖는 전력용 반도체 소자
JP5239548B2 (ja) * 2008-06-25 2013-07-17 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
ES2364870T3 (es) * 2008-12-12 2011-09-15 Abb Technology Ag Método para la fabricación de un dispositivo semiconductor de energía.
CN101710586B (zh) * 2009-01-09 2011-12-28 深超光电（深圳）有限公司 提高开口率的储存电容及其制作方法
CN102544083B (zh) * 2010-12-10 2015-02-04 比亚迪股份有限公司 一种mos型功率器件及其制造方法
JP6700648B2 (ja) 2012-10-18 2020-05-27 富士電機株式会社 半導体装置の製造方法
JP6268404B2 (ja) * 2013-06-20 2018-01-31 富士電機株式会社 半導体装置、スイッチング電源用制御ｉｃおよびスイッチング電源装置
CN107331617B (zh) * 2016-04-29 2019-12-31 北大方正集团有限公司 平面型vdmos器件的制作方法

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US4803532A (en) * 1982-11-27 1989-02-07 Nissan Motor Co., Ltd. Vertical MOSFET having a proof structure against puncture due to breakdown
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JPS6021571A (ja) * 1983-07-15 1985-02-02 Tdk Corp 半導体装置及びその製造方法
US4587713A (en) * 1984-02-22 1986-05-13 Rca Corporation Method for making vertical MOSFET with reduced bipolar effects
JPS60196974A (ja) * 1984-03-19 1985-10-05 Toshiba Corp 導電変調型ｍｏｓｆｅｔ
US4672407A (en) * 1984-05-30 1987-06-09 Kabushiki Kaisha Toshiba Conductivity modulated MOSFET
US4860072A (en) * 1986-03-05 1989-08-22 Ixys Corporation Monolithic semiconductor device and method of manufacturing same
IT1204243B (it) * 1986-03-06 1989-03-01 Sgs Microelettronica Spa Procedimento autoallineato per la fabbricazione di celle dmos di piccole dimensioni e dispositivi mos ottenuti mediante detto procedimento
DE3788470T2 (de) * 1986-08-08 1994-06-09 Philips Nv Verfahren zur Herstellung eines Feldeffekttransistors mit isoliertem Gate.
JPH0834311B2 (ja) * 1987-06-10 1996-03-29 日本電装株式会社 半導体装置の製造方法
JPH01132167A (ja) * 1987-11-17 1989-05-24 Mitsubishi Electric Corp 半導体装置
JPH0734474B2 (ja) * 1988-03-03 1995-04-12 富士電機株式会社 伝導度変調型ｍｏｓｆｅｔの製造方法
JPH01245557A (ja) * 1988-03-28 1989-09-29 Toshiba Corp 半導体装置の製造方法
JPH01253281A (ja) * 1988-04-01 1989-10-09 Fuji Electric Co Ltd 伝導度変調型ｍｏｓｆｅｔの製造方法
JPH0687504B2 (ja) * 1988-04-05 1994-11-02 株式会社東芝 半導体装置
JPH0247874A (ja) * 1988-08-10 1990-02-16 Fuji Electric Co Ltd Ｍｏｓ型半導体装置の製造方法
JP2787921B2 (ja) * 1989-01-06 1998-08-20 三菱電機株式会社 絶縁ゲート型バイポーラトランジスタ
JPH0744276B2 (ja) * 1989-02-20 1995-05-15 シャープ株式会社 Ｍｉｓ型半導体装置
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US5179032A (en) * 1990-02-01 1993-01-12 Quigg Fred L Mosfet structure having reduced capacitance and method of forming same
US5155052A (en) * 1991-06-14 1992-10-13 Davies Robert B Vertical field effect transistor with improved control of low resistivity region geometry

Also Published As

Publication number Publication date
EP0481153A1 (de) 1992-04-22
US5382538A (en) 1995-01-17
DE69029942D1 (de) 1997-03-27
EP0481153B1 (de) 1997-02-12
US6093948A (en) 2000-07-25
JPH06112493A (ja) 1994-04-22
JP3205361B2 (ja) 2001-09-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee