CN105374686A - 一种ldmos器件的制作方法 - Google Patents

一种ldmos器件的制作方法 Download PDF

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CN105374686A
CN105374686A CN201410443311.5A CN201410443311A CN105374686A CN 105374686 A CN105374686 A CN 105374686A CN 201410443311 A CN201410443311 A CN 201410443311A CN 105374686 A CN105374686 A CN 105374686A
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manufacture method
semiconductor substrate
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韩广涛
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CSMC Technologies Corp
Wuxi CSMC Semiconductor Co Ltd
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Wuxi CSMC Semiconductor Co Ltd
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Priority to CN201410443311.5A priority Critical patent/CN105374686A/zh
Priority to PCT/CN2015/087399 priority patent/WO2016034043A1/zh
Priority to US15/313,233 priority patent/US20170186856A1/en
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Abstract

本发明提供一种LDMOS器件的制作方法，包括：提供半导体衬底，在所述半导体衬底内形成有漂移区；在所述半导体衬底上形成栅极材料层，在所述栅极材料层上形成负性光刻胶层；图案化所述负性光刻胶层，以图案化的所述负性光刻胶层为掩膜刻蚀所述栅极材料层，以形成栅极；在所述半导体衬底和图案化的所述负性光刻胶层上形成具有开口的光刻胶层，所述开口对应预定形成体区的位置；以所述栅极和位于所述栅极上方的所述负性光刻胶层作为自对准层，进行体区注入。根据本发明的制作方法，形成的LDMOS沟道区更短，总尺寸更小，使总的Rdson更低，与传统的NLDMOS相比，其Rdson可以低10％至30％，且不影响击穿电压off-BV，进而提高了器件的性能。

Description

一种LDMOS器件的制作方法
技术领域
本发明涉及半导体技术领域，具体而言涉及一种LDMOS器件的制作方法。
背景技术
随着LDMOS在集成电路中的应用越来越广泛，对于击穿电压(off-BV)更高，导通电阻(Rdson)更小的LDMOS的需求越来越迫切。
通常来说，降低LDMOS导通电阻Rdson的方法，是在不断提高漂移区浓度的同时，通过各种RESURF理论，使其能够完全耗尽，从而获得低Rdson，并维持很高的off-BV。目前此方法已经能够使Rdson与off-BV之间的关系，接近了理论极限。
以NLDMOS为例，传统的缩短沟道长度的方法是在多晶硅栅极及场板刻蚀后，去除光刻胶，然后重新涂胶，曝光出体区注入区，利用栅极自对准工艺进行P型体区注入，然后通过一定的热过程，使P型体区横扩形成沟道区，此方法可以使靠近源端的沟道区浓度最高，从而在获得较短的沟道长度的同时，保持较高的穿通电压。
上述传统的做法中，在体区注入后需要经历较长的热过程，才能形成沟道区，因为受限于多晶硅栅极厚度，注入能量不可能太高，无法形成所需长度的沟道区。这就使得此层多晶硅只能作为LDMOS的栅极，因为低压器件的阈值电压Vt注入不易经历较长的热过程。此外，如果P型体区经历较长的热过程，其横扩后的P型杂质也会使漂移区的N型杂质浓度降低，导致Rdson升高。
因此，为了解决上述技术问题，有必要提出一种新的LDMOS器件的制作方法。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
为了克服目前存在的问题，本发明提供一种LDMOS器件的制作方法，包括：
提供半导体衬底，在所述半导体衬底内形成有漂移区；
在所述半导体衬底上形成栅极材料层，在所述栅极材料层上形成负性光刻胶层；
图案化所述负性光刻胶层，以图案化的所述负性光刻胶层为掩膜刻蚀所述栅极材料层，以形成栅极；
在所述半导体衬底和图案化的所述负性光刻胶层上形成具有开口的光刻胶层，所述开口对应预定形成体区的位置；
以所述栅极和位于所述栅极上方的所述负性光刻胶层作为自对准层，进行体区注入。
进一步，在形成所述栅极材料之前，还包括在所述漂移区上方形成场氧化层的步骤。
进一步，所述栅极延伸至部分所述场氧化层上方，形成场板。
进一步，所述体区注入具有很高的注入能量，所述注入能量为100KeV～800KeV。
进一步，通过斜角度注入方式，进行所述体区注入。
进一步，在所述体区注入步骤后，不执行退火推阱的热过程。
进一步，在所述体区注入步骤完成后，还包括同时去除所述栅极上的所述负性光刻胶层和所述具有开口的光刻胶层的步骤。
进一步，所述方法适用于带有场区的NLDMOS，无场区或无浅沟槽隔离结构的NLDMOS，以及PLDMOS。
进一步，所述栅极的材料为多晶硅。
综上所述，根据本发明的制作方法，形成的LDMOS沟道区更短，总尺寸更小，使总的Rdson更低，与传统的NLDMOS相比，其Rdson可以低10％至30％，且不影响击穿电压off-BV，进而提高了器件的性能。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A-1B为现有NLDMOS器件的制作方法依次实施所获得器件的剖面示意图；
图2A-2C为根据本发明示例性实施例的方法依次实施所获得NLDMOS器件的剖面示意图；
图3为根据本发明示例性实施例的方法依次实施步骤的流程图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本发明，将在下列的描述中提出详细的步骤，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
下面结合附图1A-1B对现有的NLDMOS的制作方法做简单描述。
参考图1A，首先，提供半导体衬底100，在所述半导体衬底100内形成有漂移区，在所述漂移区上形成有场氧化层101，在所述半导体衬底100和场氧化层101的表面形成多晶硅层，在所述多晶硅层上形成掩膜层103，所述掩膜层103为正性光刻胶。利用多晶硅层的刻蚀光刻版，图案化所述掩膜层103和并对所述多晶硅层进行刻蚀，形成多晶硅栅极及场板102。
参考图1B，去除位于多晶硅栅极及场板102上方的掩膜层103。在所述半导体衬底100、场氧化层101和多晶硅栅极及场板102的上方涂覆光刻胶层104，然后再使用P型体区注入的光刻版，图案化所述光刻胶层104形成P型注入区图案，再利用栅极自对准工艺进行P型体区注入，然后通过一定的热过程，使P型体区横扩形成沟道区，以在半导体衬底100内形成P型体区。
上述传统的做法中，在体区注入后需要经历较长的热过程，才能形成沟道区，因为受限于多晶硅栅极厚度，注入能量不可能太高，无法形成所需长度的沟道区。这就使得此层多晶硅只能作为LDMOS的栅极，因为低压器件的阈值电压Vt注入不易经历较长的热过程。此外，如果P型体区经历较长的热过程，其横扩后的P型杂质也会使漂移区的N型杂质浓度降低，导致Rdson升高。
鉴于上述问题的存在，本发明提出了一种新的LDMOS器件的制作方法。
[示例性实施例]
在该实施例中，LDMOS为N型LDMOS，以下结合图2A-2C对该实施例的N型LDMOS的制作方法进行具体说明。
首先，参考图2A，包括半导体衬底200，其中所述半导体衬底200可以硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。对于N型LDMOS，半导体衬底200为P型衬底。
对所述半导体衬底200进行N型离子掺杂，以在衬底内形成N型漂移区201。
掺杂一般是通过注入的方法实现。所需要的掺杂浓度越高，则注入过程中的注入剂量相应地也应该越高。一般来说，漂移区的掺杂浓度较低，相当于在源极和漏极之间形成一个高阻层，能够提高击穿电压，并减小了源极和漏极之间的寄生电容，有利于提高频率特性。例如，在根据本发明的一个实施例中，注入杂质为磷，漂移区201的注入剂量可以为1.0×1012～1.0×1013cm-2。
在所述漂移区201的上方形成场氧化层202。在一个示例中，利用局部场氧化(Locos)工艺形成场氧化层202。具体的，在漂移区上生长薄垫氧化层(未示出)并沉积氮化硅(未示出)，热氧化生长场氧化层202，做有源区光刻，刻蚀薄垫氧化层和氮化硅，去除光刻胶，热生长形成场氧化层，去除薄垫氧化层和氮化硅，既得到最终的场氧化层202。
在所述半导体衬底200和场氧化层202上方形成栅极材料层，在所述栅极材料层上形成负性光刻胶层204，图案化所述负性光刻胶层204，以所述图案化的负性光刻胶层204为掩膜，刻蚀所述栅极材料层，以形成栅极和覆盖部分所述场氧化层的场板203。
进一步地，在形成所述栅极材料层之前，还包括在所述半导体衬底200表面形成栅氧化层的步骤，可采用热氧化方法形成栅氧化层(未示出)。
在一个示例中，当所述栅极材料层为多晶硅层时，在所述多晶硅层上方形成负性光刻胶层，利用多晶硅刻蚀的光刻板，图案化所述负性光刻胶层，刻蚀所述多晶硅层，形成栅极以及位于部分场氧化层上方的场板。在此使用负性光刻胶，而非常用的正性光刻胶。此步骤中所涂的光刻胶之所以是负胶，是因为在多晶硅栅极刻蚀完成后，需进行P型体区曝光过程，而在P型体区曝光过程中必须保证多晶硅栅极及场板上的光刻胶层不被去除，而只有负性光刻胶才可以在被曝光后的显影过程中保留下来。故在此步骤时并不去除位于栅极及场板上方的负性光刻胶层。
参考图2B，在所述半导体衬底200、场氧化层201及图案化的负性光刻胶层204的表面上形成具有开口的光刻胶层205，所述开口对应预定形成P型体区的位置。
具体地，形成具有开口的光刻胶层205的步骤包括：在所述半导体衬底200、场氧化层201及图案化的负性光刻胶层204的表面上涂覆光刻胶层，然后通过曝光形成具有开口的光刻胶层205，所述开口对应预定形成P型体区的位置。由于栅极上方的光刻胶层为负性光刻胶层，负性光刻胶可以在被曝光后的显影过程中保留下来。
继续参考图2B，以栅极203及其上的负性光刻胶层204作为自对准层，进行P型体区注入。体区与所述漂移区具有不同的导电类型，当为N型漂移区时，则体区的导电类型应为P型。由于以栅极203及其上的负性光刻胶层204作为自对准层，所以此步骤时P型体区的注入能量可以很高，完全可以通过斜角度注入方式形成沟道区。体区的掺杂浓度相对较高，注入剂量相应地也高。例如，在根据本发明的一个实施例中，体区的注入剂量可以为1×1013～1×1014cm-2。可选地，形成体区时的很高的注入能量为100KeV～800KeV。可选地，还可通过斜角度注入方式，进行P型体区注入。
推阱一般为高温长时间的热退火过程，用以提高注入离子的扩散速率，现有技术中往往会在离子注入后进行退火推阱的热过程以完全形成体区。而由于本发明采用高注入能量或斜角度注入方式进行所述体区的注入，因此上述P型体区完全通过注入形成沟道区，不需要经历太多额外的退火推阱的热过程，甚至可以不执行退火推阱的热过程，因此多晶硅层可以同时作为低压部分的栅极，此外，P型体区的P型杂质横扩较少，N型漂移区201浓度不会降低，Rdson更小。
由于P型体区使用栅极203及其上负性光刻胶层204作为自对准注入，所以对P型体区的对位、曝光等精度要求都很低，栅极203上的负性光刻胶层204可以在P型体区注入完成后，与P型体区注入时的具有开口的光刻胶层205一起去除。
之后，如图2C所示，在P型体区206的内部注入N型掺杂离子(例如，磷)形成N型源极207，在远离P型体区206的一侧形成N型漏极208，所述漏极208位于所述场氧化层202的外侧。接着，在P型体区206内形成P型体引出区209。之后，采用快速热退火对掺杂进行激活。还可继续后道工艺形成接触孔，以及填充金属，做金属互连线，形成源极207、漏极208、P型体引出区209和栅极203的引出。
经过上述步骤，已经基本完成对NLDMOS的制作，尽管上述步骤只示出了带有场区的NLDMOS，但是此方法同样适用于无场区(或STI)的NLDMOS，以及与此对应的PLDMOS。
综上所述，根据本发明的制作方法，通过调整多晶硅层刻蚀前光刻胶的类型为负性光刻胶，使其在后续曝光过程中，不会由于曝光而被去除，并将其一直保留至紧随其后的P型体区光刻胶层曝光及注入过程中，从而使该负性光刻胶层与栅极一起，作为P型体区注入时的自对准层，使P型体区可以通过高能斜角度注入形成沟道区。因此形成的LDMOS沟道区更短，总尺寸更小，使总的Rdson更低，与传统的NLDMOS相比，其Rdson可以低10％至30％，且不影响击穿电压off-BV，进而提高了LDMOS器件的性能。
参照图3，其中示出了根据本发明示例性实施例的方法依次实施的步骤的流程图，用于简要示出整个制造工艺的流程。
在步骤301中，提供半导体衬底，在所述半导体衬底内形成有漂移区；
在步骤302中，在所述半导体衬底上形成栅极材料层，在所述栅极材料层上形成负性光刻胶层；
在步骤303中，图案化所述负性光刻胶层，以图案化的所述负性光刻胶层为掩膜刻蚀所述栅极材料层，以形成栅极；
在步骤304中，在所述半导体衬底和图案化的所述负性光刻胶层上形成具有开口的光刻胶层，所述开口对应预定形成体区的位置；
在步骤305中，以所述栅极和位于所述栅极上方的所述负性光刻胶层作为自对准层，进行体区注入。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (9)

1.一种LDMOS器件的制作方法，包括：
提供半导体衬底，在所述半导体衬底内形成有漂移区；
在所述半导体衬底上形成栅极材料层，在所述栅极材料层上形成负性光刻胶层；
图案化所述负性光刻胶层，以图案化的所述负性光刻胶层为掩膜刻蚀所述栅极材料层，以形成栅极；
在所述半导体衬底和图案化的所述负性光刻胶层上形成具有开口的光刻胶层，所述开口对应预定形成体区的位置；
以所述栅极和位于所述栅极上方的所述负性光刻胶层作为自对准层，进行体区注入。
2.根据权利要求1所述的制作方法，其特征在于，在形成所述栅极材料之前，还包括在所述漂移区上方形成场氧化层的步骤。
3.根据权利要求2所述的制作方法，其特征在于，所述栅极延伸至部分所述场氧化层上方，形成场板。
4.根据权利要求1所述的制作方法，其特征在于，所述体区注入具有很高的注入能量，所述注入能量为100KeV～800KeV。
5.根据权利要求1所述的制作方法，其特征在于，通过斜角度注入方式，进行所述体区注入。
6.根据权利要求1所述的制作方法，其特征在于，在所述体区注入步骤后，不执行退火推阱的热过程。
7.根据权利要求1所述的制作方法，其特征在于，在所述体区注入步骤完成后，还包括同时去除所述栅极上的所述负性光刻胶层和所述具有开口的光刻胶层的步骤。
8.根据权利要求1所述的制作方法，其特征在于，所述方法适用于带有场区的NLDMOS，无场区或无浅沟槽隔离结构的NLDMOS，以及PLDMOS。
9.根据权利要求1所述的制作方法，其特征在于，所述栅极的材料为多晶硅。
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