WO2016034043A1 - Ldmos器件的制作方法 - Google Patents

Ldmos器件的制作方法 Download PDF

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Publication number
WO2016034043A1
WO2016034043A1 PCT/CN2015/087399 CN2015087399W WO2016034043A1 WO 2016034043 A1 WO2016034043 A1 WO 2016034043A1 CN 2015087399 W CN2015087399 W CN 2015087399W WO 2016034043 A1 WO2016034043 A1 WO 2016034043A1
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gate
layer
photoresist layer
negative photoresist
body region
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PCT/CN2015/087399
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English (en)
French (fr)
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韩广涛
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无锡华润上华半导体有限公司
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Priority to US15/313,233 priority Critical patent/US20170186856A1/en
Publication of WO2016034043A1 publication Critical patent/WO2016034043A1/zh

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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to an LDMOS (Laternally Diffused Metal) Oxide Semiconductor) device manufacturing method.
  • LDMOS Longly Diffused Metal Oxide Semiconductor
  • the method of lowering the LDMOS on-resistance Rdson is to continuously reduce the concentration of the drift region, and to completely deplete it by various RESURF theory, thereby obtaining low Rdson and maintaining a high off-BV.
  • this method has been able to make the relationship between Rdson and off-BV close to the theoretical limit.
  • the conventional method of shortening the channel length is to remove the photoresist after etching the polysilicon gate and the field plate, and then re-coating, exposing the implanted region of the body region, and performing the gate self-alignment process.
  • the P-type body region is implanted, and then the P-type body region is laterally expanded to form a channel region by a certain thermal process.
  • This method can maximize the concentration of the channel region near the source end, thereby obtaining a shorter channel length while obtaining a shorter channel length. Maintain a high punch-through voltage.
  • a semiconductor substrate 100 is provided in which a drift region is formed, on which a field oxide layer 101 is formed, at which the semiconductor substrate 100 and the field oxide layer 101 are formed.
  • the surface forms a polysilicon layer, and a mask layer 103 is formed on the polysilicon layer, and the mask layer 103 is a positive photoresist.
  • the mask layer 103 is patterned and etched using an etched lithography plate of a polysilicon layer to form a polysilicon gate and field plate 102.
  • the mask layer 103 over the polysilicon gate and field plate 102 is removed.
  • a photoresist layer 104 is coated over the semiconductor substrate 100, the field oxide layer 101, and the polysilicon gate and the field plate 102, and then the photoresist is patterned using a P-type body- implanted photolithographic plate.
  • the layer 104 forms a P-type implant region pattern, and then P-type body region implantation is performed by a gate self-alignment process, and then the P-type body region is laterally expanded to form a channel region by a certain thermal process to be in the semiconductor substrate 100.
  • a P-type body region is formed.
  • a photoresist layer having an opening on the semiconductor substrate and the patterned negative photoresist layer, the opening corresponding to a position where a body region is predetermined to be formed;
  • the body region is implanted with the gate and the negative photoresist layer above the gate as a self-aligned layer to form a channel region.
  • the formed LDMOS channel region is shorter, the overall size is smaller, and the total Rdson is lower, and the Rdson can be 10% to 30% lower than the conventional NLDMOS without affecting the breakdown.
  • the voltage off-BV which in turn improves the performance of the device.
  • 1A-1B are schematic cross-sectional views showing a device for fabricating a conventional NLDMOS device in sequence
  • 2A-2C are schematic cross-sectional views showing a method of sequentially performing the obtained NLDMOS device in accordance with an exemplary embodiment of the present invention
  • FIG. 3 is a flow chart of a method in which steps are sequentially performed in accordance with an exemplary embodiment of the present invention.
  • the present invention proposes a new method of fabricating an LDMOS device.
  • the LDMOS is an N-type LDMOS, and a method of fabricating the N-type LDMOS of the embodiment will be specifically described below with reference to FIGS. 2A-2C and FIG.
  • step 301 a semiconductor substrate is provided in which a drift region is formed.
  • a semiconductor substrate 200 is provided, wherein the semiconductor substrate 200 may be silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), and insulator. Upper silicon germanium (SiGeOI) and germanium on insulator (GeOI).
  • the semiconductor substrate 200 is a P-type substrate.
  • the semiconductor substrate 200 is doped with N-type ions to form an N-type drift region 201 in the substrate.
  • Doping is generally achieved by means of implantation.
  • the drift region has a low doping concentration, which is equivalent to forming a high resistance layer between the source and the drain, which can increase the breakdown voltage and reduce the parasitic capacitance between the source and the drain. Conducive to improve the frequency characteristics.
  • the implanted impurity is phosphorus
  • the implantation dose of the drift region 201 may be 1.0 ⁇ 10 12 - 1.0 ⁇ 10 13 cm -2 .
  • a field oxide layer 202 is formed over the drift region 201.
  • the field oxide layer 202 is formed using a local field oxide (Locos) process. Specifically, a thin pad oxide layer (not shown) is grown on the drift region and silicon nitride (not shown) is deposited, the field oxide layer 202 is thermally oxidized, active region lithography is performed, and the thin pad oxide layer is etched and Silicon nitride, the photoresist is removed, thermally grown to form a field oxide layer, and the thin pad oxide layer and silicon nitride are removed to obtain the final field oxide layer 202.
  • a local field oxide (Locos) process Specifically, a thin pad oxide layer (not shown) is grown on the drift region and silicon nitride (not shown) is deposited, the field oxide layer 202 is thermally oxidized, active region lithography is performed, and the thin pad oxide layer is etched and Silicon nitride, the photoresist is removed, thermally grown to form
  • step 302 a gate material layer is formed on the semiconductor substrate, and a negative photoresist layer is formed on the gate material layer.
  • step 303 the negative photoresist layer is patterned, and the gate material layer is etched by using the patterned negative photoresist layer as a mask to form a gate.
  • the patterned negative photoresist layer 204 is a mask, and the gate material layer is etched to form a gate and a field plate 203 covering a portion of the field oxide layer 202.
  • a gate oxide layer (not shown) may be formed by a thermal oxidation method.
  • a negative photoresist layer is formed over the polysilicon layer, and the negative photoresist layer is patterned by using a polysilicon etched photoresist.
  • the polysilicon layer is etched to form a gate and a field plate over a portion of the field oxide layer.
  • Negative photoresist is used here instead of the usual positive photoresist.
  • the photoresist applied in this step is negative because the P-type body exposure process is required after the polysilicon gate etch is completed, and the polysilicon gate must be ensured during the P-type body exposure process.
  • the photoresist layer on the field plate is not removed, and only the negative photoresist can remain during development after exposure. Therefore, the negative photoresist layer on the gate and the field plate is not removed at this step.
  • step 304 a photoresist layer having an opening corresponding to a position at which the body region is predetermined is formed on the semiconductor substrate and the patterned negative photoresist layer.
  • a photoresist layer 205 having an opening corresponding to a predetermined P-body region is formed on the surface of the semiconductor substrate 200, the field oxide layer 201, and the patterned negative photoresist layer 204. s position.
  • the step of forming the photoresist layer 205 having an opening includes: coating a photoresist layer on the surface of the semiconductor substrate 200, the field oxide layer 201, and the patterned negative photoresist layer 204, and then A photoresist layer 205 having an opening corresponding to a position at which a P-type body region is predetermined to be formed is formed by exposure. Since the photoresist layer over the gate is a negative photoresist layer, the negative photoresist can remain during development after exposure.
  • step 305 body region implantation is performed with the gate and the negative photoresist layer above the gate as a self-aligned layer.
  • a P-type body region implant is performed with the gate electrode 203 and the negative photoresist layer 204 thereon as a self-aligned layer.
  • the body region and the drift region have different conductivity types.
  • the conductivity type of the body region should be P-type. Since the gate electrode 203 and the negative photoresist layer 204 thereon are used as the self-aligned layer, the implantation energy of the P-type body region can be high at this step, and the channel region can be formed by oblique angle injection. The doping concentration of the body region is relatively high, and the implantation dose is correspondingly high.
  • the implantation dose of the body region may be 1 ⁇ 10 13 to 1 ⁇ 10 14 cm -2 .
  • the high implantation energy when forming the body region is from 100 KeV to 800 KeV.
  • P-type body region implantation can also be performed by oblique angle injection.
  • the push trap is generally a high temperature and long time thermal annealing process for increasing the diffusion rate of the implanted ions.
  • the thermal process of annealing the well is often performed after ion implantation to completely form the body region.
  • the present invention uses high implantation energy or oblique angle injection to perform the implantation of the body region, the P-type body region is completely formed by implantation to form a channel region, and does not need to undergo too much additional annealing to push the thermal process of the well, or even
  • the thermal process of annealing the immersion well may not be performed, so the polysilicon layer may serve as the gate of the low voltage portion at the same time.
  • the P-type impurity of the P-type body region is less laterally spread, the concentration of the N-type drift region 201 is not lowered, and the Rdson is smaller. .
  • the P-type body region uses the gate electrode 203 and the negative photoresist layer 204 as self-aligned implantation, the accuracy of the alignment, exposure, etc. of the P-type body region is low, and the negative polarity on the gate 203 is low.
  • the photoresist layer 204 can be removed together with the photoresist layer 205 having an opening when the P-type body region is implanted after the P-type body region is implanted.
  • an N-type dopant ion for example, phosphorus
  • an N-type drain electrode 208 is formed on a side away from the P-type body region 206.
  • the drain 208 is located outside the field oxide layer 202.
  • a P-type body extraction region 209 is formed in the P-type body region 206.
  • the doping is activated using rapid thermal annealing. It is also possible to continue the subsequent process to form a contact hole, and to fill the metal to form a metal interconnection, and to form the source 207, the drain 208, the P-type lead-out region 209, and the gate 203.
  • the fabrication of the NLDMOS has been basically completed. Although the above steps only show the NLDMOS with the field region, the method is equally applicable to the NLDMOS without field (or STI) and the corresponding PLDMOS.
  • the type of the photoresist before the etching of the polysilicon layer is adjusted to be a negative photoresist, so that it is not removed by exposure during the subsequent exposure process, and
  • the P-type body region photoresist layer is exposed and implanted in the subsequent process, so that the negative photoresist layer and the gate electrode serve as a self-aligned layer when the P-type body region is implanted.
  • the P-type body region can be implanted into a channel region by oblique implantation at a high energy angle. Therefore, the formed LDMOS channel region is shorter, the overall size is smaller, and the total Rdson is lower, compared with the conventional NLDMOS. Rdson can be 10% to 30% lower without affecting the breakdown voltage off-BV, which in turn improves the performance of LDMOS devices.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种LDMOS器件的制作方法，包括：提供半导体衬底（200），在该半导体衬底（200）内形成有漂移区（201），在该半导体衬底（200）上形成栅极材料层，在该栅极材料层上形成负性光刻胶层（204）；图案化该负性光刻胶层（204），以图案化的该负性光刻胶层（204）为掩膜蚀刻该栅极材料层，以形成栅极（203）；在半导体衬底（200）和图案化的该负性光刻胶层（204）上形成具有开口的光刻胶层，该开口对应预定形成体区（206）的位置；以该栅极（203）和位于该栅极（203）上方的该负性光刻胶层（204）作为自对准层，进行体区（206）注入，形成沟道区。

Description

LDMOS器件的制作方法
【技术领域】
本发明涉及半导体技术领域，具体而言涉及一种LDMOS(Laterally Diffused Metal Oxide Semiconductor)器件的制作方法。
【背景技术】
随着LDMOS在集成电路中的应用越来越广泛，对于击穿电压（off-BV）更高，导通电阻（Rdson）更小的LDMOS的需求越来越迫切。
通常来说，降低LDMOS导通电阻Rdson的方法，是在不断提高漂移区浓度的同时，通过各种RESURF理论，使其能够完全耗尽，从而获得低Rdson，并维持很高的off-BV。目前此方法已经能够使Rdson与off-BV之间的关系，接近了理论极限。
以NLDMOS为例，传统的缩短沟道长度的方法是在多晶硅栅极及场板刻蚀后，去除光刻胶，然后重新涂胶，曝光出体区注入区，利用栅极自对准工艺进行P型体区注入，然后通过一定的热过程，使P型体区横扩形成沟道区，此方法可以使靠近源端的沟道区浓度最高，从而在获得较短的沟道长度的同时，保持较高的穿通电压。
下面结合附图1A-1B对现有的NLDMOS的制作方法做简单描述。
参考图1A，首先，提供半导体衬底100，在所述半导体衬底100内形成有漂移区，在所述漂移区上形成有场氧化层101，在所述半导体衬底100和场氧化层101的表面形成多晶硅层，在所述多晶硅层上形成掩膜层103，所述掩膜层103为正性光刻胶。利用多晶硅层的刻蚀光刻版，图案化所述掩膜层103和并对所述多晶硅层进行刻蚀，形成多晶硅栅极及场板102。
参考图1B，去除位于多晶硅栅极及场板102上方的掩膜层103。在所述半导体衬底100、场氧化层101和多晶硅栅极及场板102的上方涂覆光刻胶层104，然后再使用P型体区注入的光刻版，图案化所述光刻胶层104形成P型注入区图案，再利用栅极自对准工艺进行P型体区注入，然后通过一定的热过程，使P型体区横扩形成沟道区，以在半导体衬底100内形成P型体区。
上述传统的做法中，在体区注入后需要经历较长的热过程，才能形成沟道区，因为受限于多晶硅栅极厚度，注入能量不可能太高，无法形成所需长度的沟道区。这就使得此层多晶硅只能作为LDMOS的栅极，因为低压器件的阈值电压Vt注入不易经历较长的热过程。此外，如果P型体区经历较长的热过程，其横扩后的P型杂质也会使漂移区的N型杂质浓度降低，导致Rdson升高。
【发明内容】
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
有鉴于此，有必要提供一种Rdson较低的LDMOS器件的制作方法，包括：
提供半导体衬底，在所述半导体衬底内形成有漂移区；
在所述半导体衬底上形成栅极材料层，在所述栅极材料层上形成负性光刻胶层；
图案化所述负性光刻胶层，以图案化的所述负性光刻胶层为掩膜刻蚀所述栅极材料层，以形成栅极；
在所述半导体衬底和图案化的所述负性光刻胶层上形成具有开口的光刻胶层，所述开口对应预定形成体区的位置；及
以所述栅极和位于所述栅极上方的所述负性光刻胶层作为自对准层，进行体区注入，形成沟道区。
根据本发明的制作方法，形成的LDMOS沟道区更短，总尺寸更小，使总的Rdson更低，与传统的NLDMOS相比，其Rdson可以低10%至30%，且不影响击穿电压off-BV，进而提高了器件的性能。
【附图说明】
本发明的下列附图在此作为本发明的一部分用于理解本发明。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。附图中：
图1A-1B为现有的NLDMOS器件的制作方法依次实施所获得器件的剖面示意图；
图2A-2C为根据本发明示例性实施例的方法依次实施所获得NLDMOS器件的剖面示意图；
图3为根据本发明示例性实施例的方法依次实施步骤的流程图。
【具体实施方式】
为了彻底理解本发明，将在下列的描述中提出详细的步骤，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
鉴于上述问题的存在，本发明提出了一种新的LDMOS器件的制作方法。
在该实施例中，LDMOS为N型LDMOS，以下结合图2A-2C及图3对该实施例的N型LDMOS的制作方法进行具体说明。
在步骤301中，提供半导体衬底，在所述半导体衬底内形成有漂移区。
首先，参考图2A，提供半导体衬底200，其中所述半导体衬底200可以硅、绝缘体上硅（SOI）、绝缘体上层叠硅（SSOI）、绝缘体上层叠锗化硅（S-SiGeOI）、绝缘体上锗化硅（SiGeOI）以及绝缘体上锗（GeOI）等。对于N型LDMOS，半导体衬底200为P型衬底。
对所述半导体衬底200进行N型离子掺杂，以在衬底内形成N型漂移区201。
掺杂一般是通过注入的方法实现。所需要的掺杂浓度越高，则注入过程中的注入剂量相应地也应该越高。一般来说，漂移区的掺杂浓度较低，相当于在源极和漏极之间形成一个高阻层，能够提高击穿电压，并减小了源极和漏极之间的寄生电容，有利于提高频率特性。例如，在根据本发明的一个实施例中，注入杂质为磷，漂移区201的注入剂量可以为1.0×1012~1.0×1013cm-2。
在所述漂移区201的上方形成场氧化层202。在一个示例中，利用局部场氧化（Locos）工艺形成场氧化层202。具体的，在漂移区上生长薄垫氧化层（未示出）并沉积氮化硅（未示出），热氧化生长场氧化层202，做有源区光刻，刻蚀薄垫氧化层和氮化硅，去除光刻胶，热生长形成场氧化层，去除薄垫氧化层和氮化硅，既得到最终的场氧化层202。
在步骤302中，在所述半导体衬底上形成栅极材料层，在所述栅极材料层上形成负性光刻胶层。
在步骤303中，图案化所述负性光刻胶层，以图案化的所述负性光刻胶层为掩膜刻蚀所述栅极材料层，以形成栅极。
在所述半导体衬底200和场氧化层202上方形成栅极材料层，在所述栅极材料层上形成负性光刻胶层204，图案化所述负性光刻胶层204，以所述图案化的负性光刻胶层204为掩膜，刻蚀所述栅极材料层，以形成栅极和覆盖部分所述场氧化层202的场板203。
进一步地，在形成所述栅极材料层之前，还包括在所述半导体衬底200表面形成栅氧化层的步骤。可采用热氧化方法形成栅氧化层（未示出）。
在一个示例中，当所述栅极材料层为多晶硅层时，在所述多晶硅层上方形成负性光刻胶层，利用多晶硅刻蚀的光刻板，图案化所述负性光刻胶层，刻蚀所述多晶硅层，形成栅极以及位于部分场氧化层上方的场板。在此使用负性光刻胶，而非常用的正性光刻胶。此步骤中所涂的光刻胶之所以是负胶，是因为在多晶硅栅极刻蚀完成后，需进行P型体区曝光过程，而在P型体区曝光过程中必须保证多晶硅栅极及场板上的光刻胶层不被去除，而只有负性光刻胶才可以在被曝光后的显影过程中保留下来。故在此步骤时并不去除位于栅极及场板上方的负性光刻胶层。
在步骤304中，在所述半导体衬底和图案化的所述负性光刻胶层上形成具有开口的光刻胶层，所述开口对应预定形成体区的位置。
参考图2B，在所述半导体衬底200、场氧化层201及图案化的负性光刻胶层204的表面上形成具有开口的光刻胶层205，所述开口对应预定形成P型体区的位置。
具体地，形成具有开口的光刻胶层205的步骤包括：在所述半导体衬底200、场氧化层201及图案化的负性光刻胶层204的表面上涂覆光刻胶层，然后通过曝光形成具有开口的光刻胶层205，所述开口对应预定形成P型体区的位置。由于栅极上方的光刻胶层为负性光刻胶层，负性光刻胶可以在被曝光后的显影过程中保留下来。
在步骤305中，以所述栅极和位于所述栅极上方的所述负性光刻胶层作为自对准层，进行体区注入。
继续参考图2B，以栅极203及其上的负性光刻胶层204作为自对准层，进行P型体区注入。体区与所述漂移区具有不同的导电类型，当为N型漂移区时，则体区的导电类型应为P型。由于以栅极203及其上的负性光刻胶层204作为自对准层，所以此步骤时P型体区的注入能量可以很高，完全可以通过斜角度注入方式形成沟道区。体区的掺杂浓度相对较高，注入剂量相应地也高。例如，在根据本发明的一个实施例中，体区的注入剂量可以为1×1013 ~1×1014cm-2。可选地，形成体区时的很高的注入能量为100KeV~800KeV。可选地，还可通过斜角度注入方式，进行P型体区注入。
推阱一般为高温长时间的热退火过程，用以提高注入离子的扩散速率，现有技术中往往会在离子注入后进行退火推阱的热过程以完全形成体区。而由于本发明采用高注入能量或斜角度注入方式进行所述体区的注入，因此上述P型体区完全通过注入形成沟道区，不需要经历太多额外的退火推阱的热过程，甚至可以不执行退火推阱的热过程，因此多晶硅层可以同时作为低压部分的栅极，此外，P型体区的P型杂质横扩较少，N型漂移区201浓度不会降低，Rdson更小。
由于P型体区使用栅极203及其上负性光刻胶层204作为自对准注入，所以对P型体区的对位、曝光等精度要求都很低，栅极203上的负性光刻胶层204可以在P型体区注入完成后，与P型体区注入时的具有开口的光刻胶层205一起去除。
之后，如图2C所示，在P型体区206的内部注入N型掺杂离子（例如，磷）形成N型源极207，在远离P型体区206的一侧形成N型漏极208，所述漏极208位于所述场氧化层202的外侧。接着，在P型体区206内形成P型体引出区209。之后，采用快速热退火对掺杂进行激活。还可继续后道工艺形成接触孔，以及填充金属，做金属互连线，形成源极207、漏极208、P型体引出区209和栅极203的引出。
经过上述步骤，已经基本完成对NLDMOS的制作，尽管上述步骤只示出了带有场区的NLDMOS，但是此方法同样适用于无场区（或STI）的NLDMOS，以及与此对应的PLDMOS。
综上所述，根据本发明的制作方法，通过调整多晶硅层刻蚀前光刻胶的类型为负性光刻胶，使其在后续曝光过程中，不会由于曝光而被去除，并将其一直保留至紧随其后的P型体区光刻胶层曝光及注入过程中，从而使该负性光刻胶层与栅极一起，作为P型体区注入时的自对准层，使P型体区可以通过高能斜角度注入形成沟道区。因此形成的LDMOS沟道区更短，总尺寸更小，使总的Rdson更低，与传统的NLDMOS相比，其 Rdson可以低10%至30%，且不影响击穿电压off-BV，进而提高了LDMOS器件的性能。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (9)

  1. 一种LDMOS器件的制作方法，包括：
    在半导体衬底内形成有漂移区；
    在所述半导体衬底上形成栅极材料层，在所述栅极材料层上形成负性光刻胶层；
    图案化所述负性光刻胶层，以图案化的所述负性光刻胶层为掩膜刻蚀所述栅极材料层，以形成栅极；
    在所述半导体衬底和图案化的所述负性光刻胶层上形成具有开口的光刻胶层，所述开口对应预定形成体区的位置；及
    以所述栅极和位于所述栅极上方的所述负性光刻胶层作为自对准层，进行体区注入，形成沟道区。
  2. 根据权利要求1所述的制作方法，其特征在于，在形成所述栅极材料之前，还包括在所述漂移区上方形成场氧化层的步骤。
  3. 根据权利要求2所述的制作方法，其特征在于，所述栅极延伸至部分所述场氧化层上方，形成场板。
  4. 根据权利要求1所述的制作方法，其特征在于，所述体区注入的注入能量为100KeV~800KeV。
  5. 根据权利要求1所述的制作方法，其特征在于，通过斜角度注入方式，进行所述体区注入。
  6. 根据权利要求1所述的制作方法，其特征在于，在所述体区注入步骤后，不执行退火推阱的热过程。
  7. 根据权利要求1所述的制作方法，其特征在于，在所述体区注入步骤完成后，还包括同时去除所述栅极上的所述负性光刻胶层和所述具有开口的光刻胶层的步骤。
  8. 根据权利要求1所述的制作方法，其特征在于，所述方法适用于带有场区的NLDMOS，无场区或无浅沟槽隔离结构的NLDMOS，以及PLDMOS。
  9. 根据权利要求1所述的制作方法，其特征在于，所述栅极的材料为多晶硅。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102359373B1 (ko) * 2018-06-11 2022-02-08 에스케이하이닉스 시스템아이씨 주식회사 고전압 반도체소자의 제조방법
CN111816705A (zh) * 2019-04-12 2020-10-23 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN112309863B (zh) * 2019-07-31 2024-02-23 上海积塔半导体有限公司 超低导通电阻ldmos及其制作方法
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KR102274813B1 (ko) 2020-02-27 2021-07-07 주식회사 키 파운드리 게이트 전극 통과 이온 주입을 이용한 반도체 소자 제조방법
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CN114823482B (zh) * 2022-06-20 2022-09-02 北京芯可鉴科技有限公司 横向扩散金属氧化物半导体的制备方法和器件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020072159A1 (en) * 2000-12-07 2002-06-13 Eiji Nishibe Semiconductor device and manufacturing method thereof
US20080073746A1 (en) * 2006-09-27 2008-03-27 Oki Electric Industry Co., Ltd. Semiconductor device
CN101241934A (zh) * 2007-02-08 2008-08-13 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN101431020A (zh) * 2007-11-09 2009-05-13 上海华虹Nec电子有限公司 T型多晶硅栅电极的制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0731504B1 (en) * 1995-03-09 2002-11-27 STMicroelectronics S.r.l. Process for the manufacturing of integrated circuits comprising lateral low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells
JP3575871B2 (ja) * 1995-06-19 2004-10-13 株式会社ルネサステクノロジ フォトマスクの製造方法およびそのフォトマスクを用いた半導体集積回路装置の製造方法
JP2007194308A (ja) * 2006-01-18 2007-08-02 Renesas Technology Corp 半導体装置およびその製造方法
CN102446733B (zh) * 2011-12-08 2014-03-12 上海先进半导体制造股份有限公司 高压射频横向扩散结构的功率器件及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020072159A1 (en) * 2000-12-07 2002-06-13 Eiji Nishibe Semiconductor device and manufacturing method thereof
US20080073746A1 (en) * 2006-09-27 2008-03-27 Oki Electric Industry Co., Ltd. Semiconductor device
CN101241934A (zh) * 2007-02-08 2008-08-13 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN101431020A (zh) * 2007-11-09 2009-05-13 上海华虹Nec电子有限公司 T型多晶硅栅电极的制备方法

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