WO2016141784A1 - 场效应晶体管的制作方法 - Google Patents

场效应晶体管的制作方法 Download PDF

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WO2016141784A1
WO2016141784A1 PCT/CN2016/072470 CN2016072470W WO2016141784A1 WO 2016141784 A1 WO2016141784 A1 WO 2016141784A1 CN 2016072470 W CN2016072470 W CN 2016072470W WO 2016141784 A1 WO2016141784 A1 WO 2016141784A1
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substrate
forming
gate oxide
polysilicon layer
field effect
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PCT/CN2016/072470
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French (fr)
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王蛟
黄枫
赵龙杰
林峰
韩广涛
孙贵鹏
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无锡华润上华半导体有限公司
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Publication of WO2016141784A1 publication Critical patent/WO2016141784A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure

Definitions

  • the present invention relates to the field of semiconductor device technologies, and in particular, to a method of fabricating a field effect transistor.
  • MOS Metal Oxide Semiconductor
  • BV Breakdown
  • Rdson on-resistance
  • MOS tube fabrication techniques typically use a photoresist barrier implant to form a channel region prior to formation of the gate oxide layer.
  • the channel formed by this technique must reach a certain length to compensate for the dimensional deviation and the alignment deviation caused by the fluctuation of the lithography process, so the channel length cannot be made small, thus limiting the size of the channel resistance, resulting in a larger Rdson. .
  • Impurity implantation is performed on the exposed regions at an implantation angle of 70 to 80 with respect to the surface of the substrate to form a source well region on the substrate.
  • the polysilicon layer is photolithographically and etched to form a source end region, and then the photoresist is left, and impurity implantation is performed at an implantation angle of 70 to 80 with respect to the surface of the substrate. Since the impurity implantation has a certain implantation angle, a portion of the polysilicon layer and the gate oxide layer at the edge of the source region is injected and penetrated by the impurity and injected into the substrate, thereby forming a stable and extremely small trench. Road. Thus, the channel length is greatly reduced without increasing the lithography plate and without lowering the BV, so that the Rdson of the present invention is greatly reduced compared to the Rdson of the conventional manufacturing technique.
  • FIG. 1 is a flow chart showing a method of fabricating a field effect transistor according to an embodiment
  • FIG. 2 is a schematic structural view of a device after forming a polysilicon layer according to an embodiment
  • FIG. 3 is a schematic structural view of a device after development according to an embodiment
  • FIG. 4 is a schematic view of impurity implantation of an exposed region according to an embodiment
  • FIG. 5 is a schematic structural diagram of a device of a field effect transistor according to an embodiment
  • Figure 6 is a BV-Rdson diagram of a conventional device and an embodiment fabrication device.
  • the vocabulary of the semiconductor field cited herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.
  • 1 is a flow chart of a method of fabricating a field effect transistor of an embodiment.
  • Step S110 providing the substrate 100.
  • the material of the substrate 100 is silicon, silicon carbide, gallium arsenide, indium phosphide or germanium silicon.
  • Substrate 100 can be a silicon or silicon-containing P-type substrate, such as a single layer silicon substrate including a silicon wafer, or a substrate including other multilayer structures and a silicon layer.
  • a drain well region 710 and a shallow trench isolation structure 800 are then formed over the substrate 100.
  • the drain well region 710 is an N well.
  • Shallow trench isolation structure (STI, shallow trench Isolation 800 is a field oxide layer which may comprise an oxide of silicon, such as silicon dioxide.
  • the shallow trench isolation structure 800 is mainly used to separate the source structure and the drain structure.
  • the shallow trench isolation structure is the mainstream isolation process below 0.18um.
  • drain well region 710 and the shallow trench isolation structure 800 are formed, the following steps are performed.
  • Step S120 forming a gate oxide layer 200 on the substrate 100.
  • the gate oxide layer 200 is a silicon dioxide layer.
  • the gate oxide layer 200 is formed followed by the following steps.
  • Step S130 forming a polysilicon layer 300 on the gate oxide layer 200.
  • a polysilicon layer 300 is formed on the gate oxide layer 200 by a deposition process.
  • 2 is a schematic view showing the structure of a device after forming a polysilicon layer according to an embodiment.
  • the polysilicon layer 300 is formed followed by the following steps.
  • Step S140 forming a photoresist 400 on the polysilicon layer 300.
  • a layer of photoresist 400 is applied over the polysilicon layer 300.
  • Step S150 exposing and developing the photoresist 400 to form an exposed region 310 to expose a portion of the polysilicon layer 300. This step mainly exposes and develops the area where the source structure needs to be formed.
  • Fig. 3 is a schematic view showing the structure of a device after development in an embodiment.
  • step S160 follows.
  • Step S160 removing a portion of the polysilicon layer located in the exposed region 310 and a gate oxide layer under the portion of the polysilicon layer.
  • the polysilicon layer and the gate oxide layer of the exposed region 310 are removed by an etching process, and then the source structure region (exposed region 310) where the substrate 100 is required to be implanted with the source is exposed.
  • Step S170 impurity implantation is performed on the exposed region 310 at an implantation angle ⁇ of 70° to 80° with respect to the surface of the substrate 100 to form a source terminal well region 610 (see FIG. 5) on the substrate 100, that is, a glue injection.
  • the source well region 610 is a P well.
  • the injection angle a is preferably 75°, allowing for a suitable deviation. Since the impurity implantation has a certain implantation angle, a portion of the polysilicon layer and the gate oxide layer at the edge of the source region is injected and implanted by the impurity and injected into the substrate 100, thereby forming a stable and extremely small. Channel (see the dotted line in Figure 4). Referring to Fig. 4, impurity implantation can be performed on both sides of the source region at an implantation angle ⁇ , so that a very small channel can be formed on both sides of the source region.
  • impurity implantation it may be an implantation angle of 70°-80° or a normal vertical injection.
  • FIG. 4 is a schematic view of impurity implantation of an exposed region according to an embodiment.
  • the source well region 610 For the fabrication of the field effect transistor, after the source well region 610 is formed, some subsequent steps should be included: removing the photoresist 400; etching the polysilicon layer and the gate oxide layer to form the gate structure 500; and performing the substrate 100 on the substrate 100 Impurity implantation forms the source structure 600 and the drain structure 700.
  • Fig. 5 is a block diagram showing the structure of a field effect transistor of an embodiment.
  • the polysilicon layer is photolithographically and etched to form a source end region, and then the photoresist is left, and an impurity implantation is performed at an implantation angle of 70°-80° with the surface of the substrate. Since the impurity implantation has a certain implantation angle, a portion of the polysilicon layer and the gate oxide layer at the edge of the source region is injected and penetrated by the impurity and injected into the substrate, thereby forming a stable and extremely small trench. Road (see the circular dotted line in Figure 5). Thereby, the channel length is greatly reduced without increasing the lithographic plate and without lowering the BV, so that the Rdson of the present invention is greatly reduced compared to the Rdson of the conventional manufacturing technique.
  • Figure 6 is a BV-Rdson diagram of a conventional device and an embodiment fabrication device.
  • the abscissa in Fig. 6 is the BV value, and the ordinate is the Rdson value.
  • the Rdson in the fabrication method of the present embodiment is greatly reduced compared to the Rdson of the conventional device.

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  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种场效应晶体管的制作方法，包括：（S110）提供衬底；（S120）在所述衬底上形成栅氧化层（200）；（S130）在所述栅氧化层（200）上形成多晶硅层（300）；（S140）在所述多晶硅层（300）上形成光刻胶（400）；（S150）对所述光刻胶（400）进行曝光和显影形成暴露区域（310），以暴露部分所述多晶硅层（300）；（S160）去除位于所述暴露区域（310）的部分多晶硅层（300）及位于所述部分多晶硅层下方的栅氧化层（200）；以及（S170）沿与所述衬底（100）表面呈70°-80°的注入角度对所述暴露区域（310）进行杂质注入，以在所述衬底（100）上形成源端阱区（610）。

Description

场效应晶体管的制作方法
【技术领域】
本发明涉及半导体器件技术领域，特别涉及一种场效应晶体管的制作方法。
【背景技术】
在半导体集成电路器件中，MOS(Metal Oxide Semiconductor)管的击穿电压（BV，Breakdown Voltage）和导通电阻（Rdson）往往是矛盾的。Rdson主要由漂移区电阻、沟道电阻、JEFT电阻以及源漏接触电阻组成，通常希望得到的是较大的BV和较低的Rdson。但当调整BV上升时，Rdson也会相应的升高；而降低Rdson时，BV也会随之降低。
而传统的MOS管制造技术，通常在栅氧化层形成前使用光刻胶阻挡注入形成沟道区域。这种技术形成的沟道必须达到一定长度来补偿光刻工艺波动造成的尺寸偏差和对位偏差，因此沟道长度不能做的很小，这样就限制了沟道电阻的大小，导致Rdson较大。
【发明内容】
有鉴于此，有必要提供一种场效应晶体管的制作方法，以在保证BV与传统制造技术一样的情况下Rdson较小。
一种场效应晶体管的制作方法，包括步骤：
提供衬底；
在所述衬底上形成栅氧化层；
在所述栅氧化层上形成多晶硅层；
在所述多晶硅层上形成光刻胶；
对所述光刻胶进行曝光和显影形成暴露区域，以暴露部分所述多晶硅层；
去除位于所述暴露区域的部分多晶硅层及位于所述部分多晶硅层下方的栅氧化层；
沿与所述衬底表面呈70°-80°的注入角度对所述暴露区域进行杂质注入，以在所述衬底上形成源端阱区。
上述场效应晶体管的制作方法，多晶硅层形成后，光刻和刻蚀多晶硅层以形成源端区域，然后保留光刻胶，沿与衬底表面呈70°-80°的注入角度进行杂质注入。因为杂质注入有一定的注入角度，源端区域边缘的多晶硅层和栅氧化层有一部份区域会被杂质注入射穿，并注入到衬底内部，由此可以形成一个稳定的、极小的沟道。从而，在不增加光刻版以及不降低BV的情况下，极大的减小沟道长度，使得本发明的Rdson比传统制造技术的Rdson大大降低。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一实施例的场效应晶体管的制作方法的流程图；
图2是一实施例的形成多晶硅层后的器件结构示意图；
图3是一实施例的显影后的器件结构示意图；
图4是一实施例的对暴露区域进行杂质注入的示意图；
图5是一实施例的场效应晶体管的器件结构示意图；
图6为传统器件和一实施例的制造器件的BV-Rdson图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
本文所引用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
下面结合附图，对本发明的具体实施方式进行详细描述，以N型场效应晶体管为例。
图1是一实施例的场效应晶体管的制作方法的流程图。
一种场效应晶体管的制作方法，包括步骤：
步骤S110：提供衬底100。衬底100的材料为硅、碳化硅、砷化镓、磷化铟或锗硅。衬底100可为硅或含硅的P型衬底，例如包括硅晶圆的单层硅衬底，或者包括其他多层结构和硅层的衬底。
然后在衬底100上形成漏端阱区710和浅沟槽隔离结构800。漏端阱区710为N阱。浅沟槽隔离结构（STI，shallow trench isolation）800即场氧化层，可以包含硅的氧化物，例如可以是二氧化硅。浅沟槽隔离结构800主要用于分隔源极结构和漏极结构。浅沟槽隔离结构为现今0.18um以下的主流隔离工艺。
漏端阱区710和浅沟槽隔离结构800形成完成后，接着以下步骤。
步骤S120：在衬底100上形成栅氧化层200。栅氧化层200为二氧化硅层。栅氧化层200形成后接着以下步骤。
步骤S130：在栅氧化层200上形成多晶硅层300。采用淀积工艺在栅氧化层200形成一层多晶硅层300。图2是一实施例的形成多晶硅层后的器件结构示意图。
多晶硅层300形成后接着以下步骤。
步骤S140：在多晶硅层300上形成光刻胶400。在多晶硅层300上涂覆一层光刻胶400。
步骤S150：对光刻胶400进行曝光和显影形成暴露区域310，以暴露部分多晶硅层300。此步骤主要对需要形成源极结构区域进行曝光和显影。图3是一实施例的显影后的器件结构示意图。
显影后，接着步骤S160。
步骤S160：去除位于所述暴露区域310的部分多晶硅层及位于所述部分多晶硅层下方的栅氧化层。采用刻蚀工艺去除暴露区域310的多晶硅层和栅氧化层，然后暴露出衬底100需要进行源端杂质注入的源极结构区域（暴露区域310）。
步骤S170：沿与衬底100表面呈70°-80°的注入角度α对暴露区域310进行杂质注入以在衬底100上形成源端阱区610(见图5)，即带胶注入。源端阱区610为P阱。注入角度α优选为75°，允许有合适的偏差。因为杂质注入有一定的注入角度，源端区域边缘的多晶硅层和栅氧化层有一部份区域会被杂质注入射穿，并注入到衬底100内部，由此可以形成一个稳定的、极小的沟道（见图4中圆形虚线部分）。见图4，可以对源端区域两侧都以注入角度α进行杂质注入，使得源端区域两侧都可以形成一个极小的沟道。
当然，对于杂质注入，既可以是呈70°-80°的注入角度，也可以伴随着正常的垂直注入。
图4是一实施例的对暴露区域进行杂质注入的示意图。
对于制造场效应晶体管而言，形成源端阱区610后，还应该包括一些后续步骤：去除光刻胶400；对多晶硅层和栅氧化层进行刻蚀形成栅极结构500；对衬底100进行杂质注入形成源极结构600和漏极结构700。
图5是一实施例的场效应晶体管的器件结构示意图。
上述场效应晶体管的制作方法，多晶硅层形成后，光刻和刻蚀多晶硅层以形成源端区域，然后保留光刻胶，与衬底表面呈70°-80°的注入角度进行杂质注入。因为杂质注入有一定的注入角度，源端区域边缘的多晶硅层和栅氧化层有一部份区域会被杂质注入射穿，并注入到衬底内部，由此可以形成一个稳定的、极小的沟道（见图5中圆形虚线部分）。从而，在不增加光刻版以及不降低BV的情况下，极大地减小沟道长度，使得本发明的Rdson比传统制造技术的Rdson大大降低。
图6为传统器件和一实施例的制造器件的BV-Rdson图。图6中的横坐标为BV值，纵坐标为Rdson值。从图6中可知，在相同的BV值的条件下，本实施例制作方法中的Rdson相对于传统器件的Rdson大为降低了。
可以理解，上述场效应晶体管的制作方法，仅描述一些主要步骤，并不代表制造场效应晶体管的所有步骤。图2-图5中的图示也是对场效应晶体管的一些主要结构的简单示例，并不代表场效应晶体管的全部结构。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (7)

  1. 一种场效应晶体管的制作方法，其特征在于，包括：
    提供衬底；
    在所述衬底上形成栅氧化层；
    在所述栅氧化层上形成多晶硅层；
    在所述多晶硅层上形成光刻胶；
    对所述光刻胶进行曝光和显影形成暴露区域，以暴露部分多晶硅层；
    去除位于所述暴露区域的部分多晶硅层及位于所述部分多晶硅层下方的栅氧化层；以及
    沿与所述衬底表面呈70°-80°的注入角度对所述暴露区域进行杂质注入，以在所述衬底上形成源端阱区。
  2. 根据权利要求1所述的方法，其特征在于，所述注入角度为75°。
  3. 根据权利要求1所述的方法，其特征在于，形成所述源端阱区后，所述方法还包括：
    去除所述光刻胶；
    对所述多晶硅层和栅氧化层进行刻蚀形成栅极结构；
    对所述衬底进行杂质注入形成源极结构和漏极结构。
  4. 根据权利要求1所述的方法，其特征在于，在所述衬底上形成栅氧化层之前，所述方法还包括：
    在所述衬底上形成漏端阱区；以及
    在所述衬底上形成浅沟槽隔离结构。
  5. 根据权利要求4所述的场效应晶体管的制作方法，其特征在于，所述漏端阱区为N阱，所述源端阱区为P阱。
  6. 根据权利要求4所述的场效应晶体管的制作方法，其特征在于，所述浅沟槽隔离结构包含硅的氧化物。
  7. 根据权利要求1方法，其特征在于，所述衬底的材料为硅、碳化硅、砷化镓、磷化铟或锗硅。
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