TW201431021A - 包含再分佈層及耦合至該再分佈層之金屬柱的半導體裝置 - Google Patents

包含再分佈層及耦合至該再分佈層之金屬柱的半導體裝置 Download PDF

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TW201431021A
TW201431021A TW102143349A TW102143349A TW201431021A TW 201431021 A TW201431021 A TW 201431021A TW 102143349 A TW102143349 A TW 102143349A TW 102143349 A TW102143349 A TW 102143349A TW 201431021 A TW201431021 A TW 201431021A
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layer
ldmos
metal
semiconductor device
gate
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TW102143349A
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TWI544591B (zh
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Ashraf W Lotfi
Jeffrey Demski
Anatoly Feygenson
Douglas Dean Lopata
Jay Norton
John D Weld
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Enpirion Inc
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Abstract

本發明揭示一種半導體裝置及其形成方法，在一實施例中，該半導體裝置包含使用複數個橫向擴散金氧半導體(「LDMOS」)單元形成之一半導體晶粒1905。該半導體裝置亦包含電耦合至該複數個LDMOS單元之一再分佈層1940及分佈在該再分佈層1940上方且電耦合至該再分佈層1940之複數個金屬柱1945。

Description

包含再分佈層及耦合至該再分佈層之金屬柱的半導體裝置
本發明大體上係針對半導體裝置，且更具體言之係針對一種金氧半導體裝置及其形成方法。
可以一客製化高速橫向擴散金氧半導體(「LDMOS」)程序在一矽晶圓上製造一橫向功率開關/電晶體。橫向功率開關係由經佈線進出一晶圓之頂側上容許之裝置終端機之極多個單元而形成。不同於傳統的垂直式樣及溝渠式樣裝置，通常不採用背面佈線。此外，使用深次微米微影術的情況下，一單元之節距(或半節距)下降至5微米(百萬分之一米(「μm」))以下，這使得源極及汲極電鍍金屬較為緊密使得沒有太多可用空間來耦合至上層金屬接觸件。上層金屬接觸件佈線至 位於一半導體封裝之一周邊處之一外部封裝接腳。此困難說明了兩個不利挑戰。
一第一挑戰係降低的金屬寬度，這導致開關及外部封裝接腳之大電流汲極端子與源極端子之間的電阻增加。一第二挑戰係開關汲極及源極金屬重疊量較大，這導致開關輸出電容(通常稱為「Coss」)增加。
在信號或數位應用中，大小減小並不妨礙佈線。然而，若該應用係一功率管理裝置，則開關之分段在理想狀況下應佈線至具有極低阻抗之外部接腳且亦具有量測自一共同參考點之相同阻抗。此狀況難以達成，這係因為該等單元內部比該等單元之周邊部分更固有地遠離該周邊，從而導致至外部封裝接腳之內部連接件之電壓及功率損失(如由上述該兩個挑戰所反映)。
當源極、汲極及閘極線係電遠離其等各自單點輸入信號產生器時會出現一分佈式傳輸線問題。在缺少補救措施的情況下，帶電長型連接件實際上變為延遲線，這導致一相當大的細節距開關之導通或關斷出現問題。此影響係一逐漸且緩慢的導通(或關斷)行為，其自輸入信號產生器傳播至自一傳輸線之一端至另一端之一有效電流槽從而導致當橫向功率開關之部分關斷時其他部分仍導通，或反之亦然。這導致一橫向功率開關產生被稱為「貫通」之一潛在相消狀況，這係因為該狀況導致一電源軌暫時短路至局部電路接地，從而產生一潛在相消電流。通常在電路設計中藉由延緩驅動器電路導通或關斷此等開關之速度來消除此一問題。雖然此解決方案可行，但是其亦使得利用具有深次微米細節距結構之高速LDMOS裝置之目的無法達成。因此，大的深次微米開關之一高速互連組態及用於形成此等開關之一對應程序將係有利的。
因此，此項技術需要的是包含諸開關(例如，一LDMOS裝置)之 一半導體裝置及其形成方法，其克服先前技術中之切換速度、佈局缺陷及開關裝置結構限制。此外，需要可高速切換且能夠用以建構一功率轉換器或其部分之一緊湊型LDMOS裝置。
藉由本發明之有利實施例(包含一半導體裝置及其形成方法)可大體上解決或避免此等及其他問題且大體上達成技術優點。在一實施例中，半導體裝置包含使用複數個橫向擴散金氧半導體(「LDMOS」)單元形成之一半導體晶粒。半導體裝置亦包含電耦合至該複數個LDMOS單元之一再分佈層及分佈在該再分佈層上方且電耦合至該再分佈層之複數個金屬柱。
前述已相當廣泛地概述本發明之特徵及技術優點使得可更好地理解本發明之下列詳細描述。在下文中將描述本發明之額外特徵及優點，其等形成本發明之申請專利範圍之標的。熟習此項技術者應明白，所揭示之概念及特定實施例可易於被用作用於修改或設計用於實行本發明之相同目的之其他結構或程序之基礎。熟習此項技術者亦應認識到，此等等效建構並未脫離如隨附申請專利範圍中陳述之本發明之精神及範疇。
110‧‧‧電力系統
120‧‧‧控制器
130‧‧‧驅動器
210‧‧‧導電基板/導線框
215‧‧‧導線框指狀物
216‧‧‧導線框指狀物
220‧‧‧表面安裝組件
225‧‧‧區域
230‧‧‧磁性材料之桿體
240‧‧‧半導體晶粒
250‧‧‧導電夾具
260‧‧‧區域
265‧‧‧第一導線接合
266‧‧‧第二導線接合
310‧‧‧淺溝渠隔離區域
315‧‧‧基板
316‧‧‧磊晶層
320‧‧‧N型埋層
325‧‧‧N型井
330‧‧‧P型井
335‧‧‧閘極介電質層
340‧‧‧閘極
345‧‧‧N型輕摻雜區域
350‧‧‧P型輕摻雜區域
355‧‧‧閘極側壁間隔件
360‧‧‧N型重摻雜區域
362‧‧‧N型重摻雜區域
365‧‧‧P型重摻雜區域
367‧‧‧P型重摻雜區域
370‧‧‧通道區域
372‧‧‧P型摻雜區域
375‧‧‧矽層
380‧‧‧介電質區域
385‧‧‧金屬接觸件
405‧‧‧功率半導體裝置
410‧‧‧倒置半導體晶粒/翻轉半導體晶粒
420‧‧‧導電圖案化導線框
421‧‧‧導電圖案化導線框
430‧‧‧印刷電路板
440‧‧‧去耦電容器/晶片電容器
441‧‧‧去耦電容器/晶片電容器
445‧‧‧去耦電容器/晶片電容器
450‧‧‧低電感區域
455‧‧‧區域
461‧‧‧通孔
462‧‧‧焊錫凸塊
463‧‧‧焊錫凸塊
470‧‧‧散熱器
480‧‧‧黏著劑
490‧‧‧金屬柱/銅柱
495‧‧‧塑膠
510‧‧‧N閘極驅動最終級
520‧‧‧P閘極驅動最終級
530‧‧‧N-橫向擴散金氧半導體裝置
531‧‧‧P-橫向擴散金氧半導體裝置
610‧‧‧小圓圈
620‧‧‧小圓圈
630‧‧‧小圓圈
640‧‧‧小圓圈
650‧‧‧小圓圈
800‧‧‧路徑
805‧‧‧路徑
810‧‧‧路徑
820‧‧‧路徑
830‧‧‧路徑
840‧‧‧路徑
910‧‧‧閘極多晶矽帶
1010‧‧‧第一反相器
1011‧‧‧P型金氧半導體裝置
1012‧‧‧N型金氧半導體裝置
1020‧‧‧第二反相器
1021‧‧‧P型金氧半導體裝置
1022‧‧‧N型金氧半導體裝置
1030‧‧‧第三反相器
1040‧‧‧第四反相器
1105‧‧‧輕摻雜P基板
1108‧‧‧P井
1111‧‧‧源極金屬帶
1112‧‧‧源極金屬帶
1113‧‧‧源極金屬帶
1114‧‧‧源極金屬帶
1121‧‧‧汲極金屬帶
1122‧‧‧汲極金屬帶
1123‧‧‧汲極金屬帶
1124‧‧‧汲極金屬帶
1130‧‧‧閘極金屬帶
1131‧‧‧閘極金屬帶
1140‧‧‧閘極氧化物帶
1150‧‧‧多晶矽閘極帶
1160‧‧‧源極金屬帶
1161‧‧‧汲極金屬帶
1162‧‧‧源極金屬帶
1163‧‧‧汲極金屬帶
1164‧‧‧源極金屬帶
1165‧‧‧汲極金屬帶
1170‧‧‧N-橫向擴散金氧半導體裝置
1171‧‧‧N-橫向擴散金氧半導體裝置/P-橫向擴散金氧半導體裝置汲極接觸件
1172‧‧‧P-橫向擴散金氧半導體裝置源極接觸件
1173‧‧‧邏輯電路元件接觸件
1174‧‧‧銅通孔
1175‧‧‧通孔
1176‧‧‧通孔
1177‧‧‧再分佈層
1178‧‧‧銅柱
1179‧‧‧導線框
1180‧‧‧通孔
1181‧‧‧通孔
1182‧‧‧通孔
1184‧‧‧P-橫向擴散金氧半導體裝置源極金屬帶
1185‧‧‧P-橫向擴散金氧半導體裝置汲極金屬帶
1186‧‧‧P-橫向擴散金氧半導體裝置源極金屬帶
1187‧‧‧P-橫向擴散金氧半導體裝置汲極金屬帶
1188‧‧‧P-橫向擴散金氧半導體裝置源極金屬帶
1189‧‧‧P-橫向擴散金氧半導體裝置汲極金屬帶
1191‧‧‧N閘極驅動器
1192‧‧‧P閘極驅動器
1193‧‧‧邏輯電路元件
1194‧‧‧N-橫向擴散金氧半導體裝置/P-橫向擴散金氧半導體裝置汲極接觸件
1195‧‧‧N-橫向擴散金氧半導體裝置源極接觸件
1196‧‧‧P-橫向擴散金氧半導體裝置源極接觸件
1197‧‧‧邏輯電路元件
1905‧‧‧輕摻雜基板/半導體晶粒
1910‧‧‧井
1915‧‧‧絕緣層/氮氧化矽層
1920‧‧‧通孔
1925‧‧‧通孔
1930‧‧‧銅通孔
1935‧‧‧第一聚醯亞胺層
1940‧‧‧銅再分佈層
1945‧‧‧銅柱
1950‧‧‧第二聚醯亞胺層
1955‧‧‧銅導線框
2001‧‧‧N-橫向擴散金氧半導體單元
2003‧‧‧通道區域
2005‧‧‧P摻雜半導體基板
2010‧‧‧P摻雜半導體基板
2115‧‧‧P型井
2120‧‧‧閘極氧化物層
2025‧‧‧閘極多晶矽層
2030‧‧‧上覆閘極氧化物層
2035‧‧‧氮化矽
2040‧‧‧側壁間隔件
2045‧‧‧光阻
2050‧‧‧閘極寬度
2055‧‧‧P型區域
2060‧‧‧重摻雜N型區域
2065‧‧‧光阻
2070‧‧‧輕摻雜N型區域
2075‧‧‧光阻
2080‧‧‧重摻雜N型區域
2085‧‧‧光阻
2090‧‧‧重摻雜P型區域
2095‧‧‧二氧化矽層
2100‧‧‧光阻
2105‧‧‧二氧化矽區域
2110‧‧‧非反應性耐熔金屬
2115‧‧‧矽化物層
2120‧‧‧非晶矽氮氧化物層/氮氧化矽層
2125‧‧‧光阻
2130‧‧‧蝕刻停止耐熔層
2135‧‧‧光阻層
2140‧‧‧氮氧化矽層
2145‧‧‧光阻層
2150‧‧‧蝕刻停止耐熔層
2155‧‧‧光阻層
2160‧‧‧氮氧化矽層
2165‧‧‧光阻層
2170‧‧‧氮氧化矽層
2175‧‧‧光阻層
2180‧‧‧聚醯亞胺塗層
2185‧‧‧光阻層
2190‧‧‧耐熔障壁層
2195‧‧‧銅晶種層
2200‧‧‧銅層
2205‧‧‧聚醯亞胺塗層
2210‧‧‧光阻層
2215‧‧‧銅晶種層
2220‧‧‧銅柱/金屬柱
2225‧‧‧囊封劑
2230‧‧‧圖案化導線框
8001‧‧‧P-橫向擴散金氧半導體單元單元
8003‧‧‧通道區域
8005‧‧‧P摻雜半導體基板
8010‧‧‧淺溝渠隔離區域
8015‧‧‧輕摻雜N型井
8017‧‧‧N型井
8120‧‧‧下伏閘極氧化物層
8025‧‧‧閘極多晶矽層
8030‧‧‧上覆閘極氧化物層
8040‧‧‧側壁間隔件
8055‧‧‧N型區域
8060‧‧‧重摻雜P型區域
8070‧‧‧輕摻雜P型區域
8080‧‧‧重摻雜P型區域
8090‧‧‧重摻雜N型區域
8105‧‧‧二氧化矽區域
8115‧‧‧矽化物層
8120‧‧‧非晶矽氮氧化物層/氮氧化矽層
8130‧‧‧蝕刻停止耐熔層
8140‧‧‧氮氧化矽層
8150‧‧‧蝕刻停止耐熔層
8160‧‧‧氮氧化矽層
8170‧‧‧氮氧化矽層
8180‧‧‧聚醯亞胺塗層
8190‧‧‧耐熔障壁層
8220‧‧‧銅層
8215‧‧‧銅晶種層
8220‧‧‧金屬柱/銅柱
8225‧‧‧囊封劑
8230‧‧‧圖案化導線框
為更完整地理解本發明，現結合隨附圖式參考下列描述，其中：圖1圖解說明包含一半導體裝置之一功率轉換器之一實施例之一方塊圖；圖2A及圖2B圖解說明囊封之前之一電子裝置/功率轉換器之一實施例之等角視圖；圖3圖解說明一半導體裝置之一部分之一實施例之一橫截面視圖； 圖4圖解說明展示藉由金屬柱耦合至複數個去耦裝置之一倒置半導體晶粒之一半導體裝置之一實施例之一正視圖；圖5圖解說明使用一圓周環分佈系統形成之一半導體裝置之一實施例之一平面圖；圖6圖解說明形成為一半導體晶粒上之一沈積物之一再分佈層之一實施例之一平面圖；圖7圖解說明圖6中所圖解說明之再分佈層之一平面圖，其具有展示一N-LDMOS裝置及一P-LDMOS裝置之一輪廓之一覆疊；圖8及圖9圖解說明圖6中圖解說明之再分佈層之放大平面圖；圖10圖解說明經組態以由一脈寬調變(「PWM」)信號產生圖1中圖解說明用於一N-LDMOS裝置之一大振幅閘極驅動信號之一N型金氧半導體(「NMOS」)反相器鏈之一實施例之一示意圖；圖11圖解說明一半導體裝置或其部分中具體實施之一部分建構N-LDMOS裝置之一部分之一實施例之一簡化三維視圖；圖12圖解說明在形成一實質上平坦第二金屬層之後該部分建構N-LDMOS裝置之一部分之一簡化三維視圖；圖13圖解說明在形成該第二金屬層之後該部分建構N-LDMOS裝置之一部分之一簡化平面圖；圖14圖解說明在形成一實質上平坦第三金屬層之後該部分建構N-LDMOS裝置之一部分之一簡化三維視圖；圖15圖解說明在形成該第三金屬層之後該部分建構N-LDMOS裝置之一部分之一簡化平面圖；圖16圖解說明包含N-LDMOS及P-LDMOS裝置之一部分建構半導體裝置之一實施例之一簡化三維視圖，其圖解說明該部分建構半導體裝置之一第二金屬層中之源極金屬帶及汲極金屬帶之一幾何形狀；圖17圖解說明包含N-LDMOS及P-LDMOS裝置之部分建構半導體 裝置之一簡化三維視圖，其圖解說明該第三金屬層中之源極及汲極接觸件之一幾何形狀；圖17A圖解說明包含N-LDMOS及P-LDMOS裝置之部分建構半導體裝置之一簡化三維視圖，其圖解說明一再分佈層之通孔之一幾何形狀；圖17B圖解說明包含N-LDMOS及P-LDMOS裝置之部分建構半導體裝置之一簡化三維視圖，其圖解說明一再分佈層之一幾何形狀；圖17C圖解說明包含N-LDMOS及P-LDMOS裝置之部分建構半導體裝置之一簡化三維視圖，其圖解說明該再分佈層之柱之一幾何形狀；圖17D圖解說明包含N-LDMOS及P-LDMOS裝置之部分建構半導體裝置之一簡化三維視圖，其圖解說明一導電圖案化導線框之一幾何形狀；圖18圖解說明包含N-LDMOS及P-LDMOS裝置之一裝填半導體裝置之一實施例之三維外部視圖；圖19圖解說明包含N-LDMOS及/或P-LDMOS裝置之一半導體裝置之一部分之一實施例之一正視圖；圖20圖解說明一半導體裝置或其部分中具體實施之一N-LDMOS裝置之一實施例之一橫截面視圖；圖21至圖87圖解說明形成一半導體裝置或其部分中具體實施之一N-LDMOS裝置之一實施例之橫截面視圖；圖88圖解說明一半導體裝置或其部分中具體實施之一P-LDMOS裝置之一實施例之一橫截面視圖；及圖89圖解說明一半導體裝置或其部分中具體實施之一P-LDMOS裝置之一實施例之一橫截面視圖。
除非另有指示，否則不同圖式中之對應數字及符號大體上係指 對應部分。該等圖式經繪製以清楚地圖解說明較佳實施例之相關態樣且不一定按比例繪製。
下文詳細論述當前較佳實施例之製作及使用。然而，應明白，該等實施例提供可在許多種特定背景下具體實施之許多可應用發明概念。所論述之特定實施例僅圖解說明製作並使用本發明之特定方式，且不限制本發明之範疇。
將在一特定背景下(即，一開關(例如，具體實施於一LDMOS裝置中)、併有LDMOS裝置之一半導體裝置及其形成方法)描述實施例。雖然本發明之原理將在採用一LDMOS裝置之一功率轉換器之環境下描述，但是可獲益於可在一半導體基板上高速切換之一裝置之任何應用或相關半導體技術完全在本發明之廣泛範疇內。
最初參考圖1，圖解說明包含一半導體裝置之一功率轉換器之一實施例之一方塊圖。功率轉換器包含一電力系統110、一控制器120及一驅動器130，且對諸如一微處理器之一系統供電。雖然在已圖解說明之實施例中電力系統110採用一降壓轉換器拓撲，但是熟習此項技術者應瞭解，諸如一順向轉換器拓撲之其他轉換器拓撲完全在本發明之廣泛範疇內。
功率轉換器之電力系統110在其之一輸入處自電源(由一電池表示)接收一輸入電壓Vin，且在功率轉換器之一輸出處提供一調節輸出電壓Vout以對(例如)一微處理器供電。為符合一降壓轉換器拓撲之原理，輸出電壓Vout大體上小於輸入電壓Vin使得功率轉換器之一切換操作可調節輸出電壓Vout。一主開關Qmn[例如，具體實施於一P型橫向擴散金氧半導體(「P-LDMOS」)裝置中之一P通道金氧半導體場效電晶體(「MOSFET」)]經啟用以在一主要時間間隔內(大體上與主開關Qmn之一主要工作循環「D」共存)導電且將輸入電壓Vin耦合至一輸出濾 波電感器Lout。在主要時間間隔期間，流過輸出濾波電感器Lout之一電感器電流ILout隨著電流自電力系統110之輸入流至電力系統110之輸出而增加。輸出濾波電容器Cout過濾電感器電流ILout之一ac分量。
在一互補時間間隔(大體上與主開關Qmn之一互補工作循環「1-D」共存)期間，主開關Qmn變換為一不導電狀態且一輔助開關Qaux[例如，具體實施於一N型橫向擴散金氧半導體(「N-LDMOS」)裝置中之一N通道MOSFET)]經啟用以導電。輔助開關Qaux提供維持電感器電流ILout持續流過輸出濾波電感器Lout之一路徑。在互補時間間隔期間，通過輸出濾波電感器Lout之電感器電流ILout降低。一般而言，主開關Qmn及輔助開關Qaux之各自工作循環可經調整以維持調節功率轉換器之輸出電壓Vout。然而，熟習此項技術者應瞭解，主開關Qmn及輔助開關Qaux之導電週期可分離一小段時間間隔以避免在該等導電週期之間產生跨導且有利地減小與功率轉換器相關聯之切換損耗。
功率轉換器之控制器120接收一所要功率轉換器特性，諸如來自可與微處理器相關聯之一內部或外部源的一所要系統電壓Vsystem，及功率轉換器之輸出電壓Vout。根據前述提及之特性，控制器120提供一信號(例如，一脈寬調變(「PWM」)信號SPWM)以控制電力系統110之主開關Qmn及輔助開關Qaux之一工作循環及一頻率以調節其輸出電壓Vout。經調適以控制功率轉換器之至少一開關之任何控制器完全在本發明之廣泛範疇內。
功率轉換器亦包含驅動器130，其經組態以基於由控制器120提供之PWM信號SPWM分別對主開關Qmn及輔助開關Qaux提供驅動信號SDRV1、SDRV2。實施一驅動器130存在許多種已知可行的替代技術，其等包含提供足夠大的信號延遲以防止當控制功率轉換器中之多個開關時產生交叉電流之技術。驅動器130通常包含併有經協作以對主開關Qmn及輔助開關Qaux提供驅動信號SDRV1、SDRV2之複數個驅動器開關之 切換電路。當然，能夠提供驅動信號SDRV1、SDRV2以控制一開關之任何驅動器130完全在本發明之廣泛範疇內。
在一實施例中，主開關Qmn及輔助開關Qaux係可併入最靠近執行功率轉換器之控制器120之控制功能之控制或信號處理裝置之一半導體裝置中之功率開關。控制及信號處理裝置通常係互補金氧半導體(「CMOS」)裝置，諸如P型金氧半導體(「PMOS」)裝置及N型金氧半導體(「NMOS」)裝置。PMOS及NMOS裝置亦可分別稱為P通道及N通道MOSFET。控制及信號處理裝置採用低電壓(例如，2.5伏特)(因此，亦稱為「低電壓裝置」)以防止在其細線結構之間產生跳火。電力系統110之主開關Qmn及輔助開關Qaux以及驅動器130之該複數個驅動器開關之一者可由處置較高電壓(例如，10伏特)之LDMOS裝置形成且因此稱為較高電壓裝置。將控制及信號處理裝置、功率開關及驅動器開關整合在一半導體基板上可大幅減小功率轉換器或採用相似裝置之其他設備之成本及大小。
因此，如圖1中圖解說明，控制器120之一輸入耦合至一功率轉換器之輸出電壓Vout或接收一功率轉換器之輸出電壓Vout以調節輸出電壓Vout。一控制器120可採用使用一反相輸入耦合至功率轉換器之輸出電壓Vout之一類比運算放大器建構之一誤差放大器。誤差放大器之一非反相輸入耦合至表示功率轉換器之一所要調節輸出電壓之一參考電壓。功率轉換器之一功率開關之一工作循環係由一時脈信號起始。為終止工作循環，由一類比比較器來比較誤差放大器之輸出與一傾斜電壓波形，該傾斜電壓波形通常係一週期斜坡電壓波形或具有一按比例疊加開關或電感器電流之一週期斜坡電壓波形。當誤差放大器之輸出超過傾斜電壓波形時，由類比比較器終止功率開關之工作循環。此控制器結構之結果係一回饋配置，其中類比比較器連續地作出在功率開關經啟用以導電之時間間隔期間終止功率開關工作循環之一決定。 此類比控制器架構能夠以不取決於數位邏輯之一時脈頻率或一計算速率之精細時間粒度來終止一功率開關工作循環。亦可採用數位電路來建構一控制器。
現在參考圖2A及圖2B，圖解說明囊封之前之一電子裝置/功率轉換器(例如，一功率模組)之一實施例之等角視圖。功率轉換器包含一磁性裝置(例如，一電感器)、一積體電路及表面安裝組件。功率轉換器可包含功率轉換電路，其包含磁性裝置、積體電路及表面安裝組件之至少一者或可具體實施於磁性裝置、積體電路及表面安裝組件之至少一者中。功率轉換電路可形成通常包含一切換調節器之一功率轉換器或諸如一降壓切換調節器之功率轉換器，該降壓切換調節器具有用於減小組件計數之一積體控制電路及用於高功率轉換效率之同步整流器。當然，一實施例不限於一功率模組、功率轉換器或類似物，且可適用於其他電子裝置。
圖案化並蝕刻一導電基板(或導線框)210以形成用於電感器之一繞線下部之一導電互連層以及在表面安裝組件、積體電路及電感器之間之電互連件。導線框210之一典型厚度係約8密耳(千分之一英寸)。雖然導線框210通常係由銅建構而成，但是其亦可使用替代性導電材料。導線框210對功率模組提供外部連接件，且對電感器提供一磁性材料之一支撐底座。外部連接件形成為導線框210之指狀物，參照為導線框指狀物(其等之兩者指定為215、216)。
導線框210大體上係使用包圍導電圖案之一體式金屬帶建構以在製造步驟期間提供機械支撐，該金屬帶隨後在製造製程中被丟棄。在建構電子裝置之後大體上剪斷周圍的金屬帶以(例如)提供未被連接的跡線。導線框210大體上係產生於諸如一16x16陣列之重複圖案(未展示)之一陣列中以(例如)形成256個實質上相同電子裝置。形成導線框210之一陣列係此項技術中已知用來減小生產電子裝置之一製造成本 之一程序。
焊錫膏經選擇性地以一薄層塗敷於導線框210而至用於遮蔽程序之區域(指定為225)以電且機械地附著表面安裝組件。諸如電容器(其等之一者指定為220)之表面安裝組件經放置使得其等導電端處於焊錫膏中。焊錫膏可由基於鉛及無鉛成分組成。具有表面安裝組件220之導線框210之陣列在一烤箱中回流以將表面安裝組件220機械且電附著至導線框210。
如上所述之步驟大體上無須在一無塵室之一高度受控制環境中執行。然而，下列步驟較佳地在諸如通常用於將積體電路組裝至如此項技術中大體上已知之一模製塑膠封裝中之一無塵室環境中執行。
將一黏著劑(例如，諸如由加利福尼亞州Ablestik of Rancho Dominguez生產之Abletherm 2600AT之一晶粒附著黏著劑)施配至導線框210上以固持一磁芯(例如，磁性材料之一桿體)230及呈一半導體晶粒240之形式的一積體電路。磁性材料之桿體230及半導體晶粒240定位於導線框210上的晶粒附著黏著劑上方。因此，磁性材料之桿體230之一下表面面向且較佳地黏附至導線框210。包含磁性材料之桿體230以增強電感器之磁性性質且可為約250微米(「μm」)厚、4密耳寬及7.5密耳長。黏著劑通常在一受控制熱製程中固化以將磁性材料之桿體230及半導體晶粒240固縛至導線框210。
焊錫膏塗敷至導線框210之區域(概括地指定為260)，其中該等區域中放置導電夾具250之端。此外，焊錫膏可由基於鉛及無鉛成分組成。導電夾具250(例如，約8密耳至12密耳厚)放置在導線框210上的磁性材料之桿體230上方且使得其等端處於焊錫膏中。導電夾具250經形成使得其等端繞磁性材料之桿體230之端朝向導線框210彎曲且不產生機械干擾。因此，磁性材料之桿體230之一上表面面向導電夾具250。因此較佳地在磁性材料之桿體230之上表面與導電夾具250之下 表面之間保留(例如)約一5密耳氣隙之一絕緣間隙，該間隙隨後可由一囊封劑填充。導電夾具250在磁性材料之各桿體230上方提供導電電感器繞線之一部分。導線框210在一回流烤箱中加熱以將導電夾具250機械且電接合至導線框210。
可由諸如金導線形成之導線接合(諸如一第一導線接合265)附著至各半導體晶粒240及導線框210以將半導體晶粒240上之襯墊電耦合至導線框210之接合區域，藉此在其等之間提供電路連接。諸如一第二導線接合266之導線接合亦可用以選擇性地電耦合導線框210之部分以提供不能容易地以單個平面佈局接線之電路互連，因此產生一雙層印刷電路板(亦稱為「印刷接線板」)或基板之導線框210之拓撲佈局功能性。
當以如上提及之一陣列形成電子裝置時，該陣列被置於一模具中且如此項技術中已知般在該陣列上方沈積諸如一模製材料之一囊封劑(較佳地，環氧樹脂)以提供環境及機械保護以及一導熱覆蓋物以在操作期間促進熱耗散。其他模製材料及程序以及經建構不具備一囊封劑之電子裝置完全在本發明之廣泛範疇內。
現在轉向圖3，圖解說明一半導體裝置之一部分之一實施例之一橫截面視圖。由於用以建構關於圖3圖解說明之半導體裝置之處理步驟類似於由以下專利描述之處理步驟：Lotfi等人於2004年1月29日申請之標題為「Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same」之美國專利7,230,302、Lotfi等人於2009年8月28日申請之標題為「Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same」之美國專利第8,212,315號、Lotfi等人於2007年8月20日申請之標題為「Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same」之美國專利申請公開案第2007/0284658 號、Lotfi等人於2012年8月15日申請之標題為「Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same」之美國專利申請公開案第2012/0306011號(該等案係以引用的方式併入本文)；此刻該程序中之步驟將不會加以詳細描述。然而，本文中將隨後描述用於建構一類似裝置之程序步驟。
圖3中圖解說明之橫截面視圖圖解說明P-LDMOS及N-LDMOS裝置之個別LDMOS單元，該等裝置係使用極多個此等個別單元而建構。在一實施例中，必要時使用鏡像重複圖3中圖解說明之個別單元之圖案以對一應用產生具有一合適額定電流之一P-LDMOS或N-LDMOS裝置。藉此使用(例如)複數個重摻雜源極區域及重摻雜汲極區域形成一基板。
半導體裝置在一基板315(例如，一P型基板)內形成於包含淺溝渠隔離區域310之一半導體晶粒中以在PMOS、NMOS、P-LDMOS及N-LDMOS裝置之間提供介電質分離。在基板315之一表面上生長一磊晶層316(例如，一P型磊晶層)，其較佳地經摻雜介於1．1014個原子/cm3與1．1016個原子/cm3之間。一埋層(例如，一N型埋層)320在容納P-LDMOS裝置及N-LDMOS裝置之區域中凹陷在基板315內。
半導體裝置亦包含形成於基板315中之容納PMOS裝置及P-LDMOS裝置之區域中及淺溝渠隔離區域310下方且在(P-LDMOS之)N型埋層320上之井(例如，N型井)325。形成N型井325以對PMOS裝置及P-LDMOS裝置提供電隔離且與N型埋層320(在P-LDMOS裝置的情況下)及淺溝渠隔離區域310協同操作以提供隔離。如圖解說明，N型埋層320上之N型井325並未覆蓋該基板315中介於其淺溝渠隔離區域310之間容納P-LDMOS裝置之整個區域。因而出於如本文中陳述之原因建構P-LDMOS之N型井325。
半導體裝置包含形成於基板315中介於淺溝渠隔離區域310之間 之額外井(例如，P型井)330，其實質上位於容納NMOS裝置與N-LDMOS裝置之區域中。雖然N型埋層320上之P型井330覆蓋該基板315中介於其淺溝渠隔離區域310之間容納N-LDMOS裝置之整個區域，但是將P型井330界定為覆蓋基板315中容納N-LDMOS裝置之區域之一部分亦完全在本發明之廣泛範疇內。半導體裝置亦包含PMOS、NMOS、P-LDMOS及N-LDMOS裝置之閘極340，其等位於一閘極介電質層335上方且包含繞該等裝置之閘極340之閘極側壁間隔件355。
N-LDMOS裝置包含用於其汲極之輕摻雜耐壓增強區域(例如，N型輕摻雜區域)345。P-LDMOS裝置亦包含用於其汲極之輕摻雜耐壓增強區域(例如，P型輕摻雜區域)350。在本實施例中且出於如上文陳述之類似原因，N型輕摻雜區域345及P型輕摻雜區域350分別對N-LDMOS及P-LDMOS裝置提供較高額定電壓。因此，N-LDMOS及P-LDMOS裝置不僅可處置來自其等汲極-源極之較高電壓，而且當源極之正電荷多於閘極340時該等裝置亦可處置來自其等之一源極-閘極之一較高電壓。應認識到，N型輕摻雜區域345及P型輕摻雜區域350之寬度可個別地改變以在不脫離本發明之範疇之情況下變更各自N-LDMOS及P-LDMOS裝置之崩潰電壓特性。此外，N型輕摻雜區域345及P型輕摻雜區域350可以類似於在先前上文引用之美國專利第7,230,302號中關於圖2至圖15圖解說明且描述之各自N-LDMOS及P-LDMOS裝置之一方式形成。
半導體裝置亦包含NMOS裝置之源極及汲極之重摻雜區域(例如，N型重摻雜區域)360，其等較佳地具有不同於N-LDMOS裝置之源極及汲極之重摻雜區域(例如，N型重摻雜區域)362之一摻雜濃度分佈。NMOS裝置之N型重摻雜區域360形成於NMOS裝置之P型井330內，且正如前文所述形成NMOS裝置之源極及汲極。此外，N-LDMOS裝置之N型重摻雜區域362形成於N-LDMOS裝置之P型井330 內。又，N-LDMOS裝置之汲極之N型重摻雜區域362與N-LDMOS裝置之N型輕摻雜區域345相鄰。
半導體裝置亦包含PMOS裝置之源極及汲極之重摻雜區域(例如，P型重摻雜區域)365，其等較佳地具有不同於P-LDMOS裝置之源極及汲極之重摻雜區域(例如，P型重摻雜區域)367之一摻雜濃度分佈。PMOS裝置之P型重摻雜區域365形成於PMOS裝置之N型井325內，且正如前文所述形成PMOS裝置之源極及汲極。此外，P-LDMOS裝置之P型重摻雜區域367形成於N型井325內或與P-LDMOS裝置之N型井325相鄰之區域中，且形成P-LDMOS裝置之源極及汲極之一部分。又，P-LDMOS裝置之汲極之P型重摻雜區域367與P-LDMOS裝置之P型輕摻雜區域350相鄰。
在已圖解說明之實施例中，N型埋層320上之N型井325並未覆蓋該基板315中介於P-LDMOS裝置之淺溝渠隔離區域310之間容納P-LDMOS裝置之整個區域。特定言之，N型井325位於一通道區域370下方且位於通道區域370內，且與P型輕摻雜區域350及重摻雜區域367相比，相反地摻雜N型井325及N型埋層320。因此，與輕摻雜區域350相同之一摻雜類型之摻雜區域(例如，P型摻雜區域)372在P-LDMOS裝置之汲極之P型重摻雜區域367與N型井325之間延伸，且具有小於P型重摻雜區域367之一摻雜濃度分佈之一摻雜濃度分佈。雖然P型重摻雜區域367較佳地具有相同摻雜濃度分佈，但是源極之P型重摻雜區域367具有不同於汲極之對應部分之一摻雜濃度分佈亦完全在本發明之廣泛範疇內。相同原理適用於半導體裝置之其他相似裝置區域。與輕摻雜區域350相同之摻雜類型之摻雜區域372一起使汲極之重摻雜區域367與形成於相反摻雜N型井325中之通道區域370分離。
P型摻雜區域372可恰好具體實施於基板315中，基板315具有介於1．1014個原子/cm3與1．1016個原子/cm3之間之一摻雜濃度分佈。採用 基板315作為P型摻雜區域372可提供在製造半導體裝置時省略一遮罩及一處理步驟之一機會。在又另一替代性實施例中，P型摻雜區域372可在植入P-LDMOS裝置之源極及汲極之P型重摻雜區域367之前由一離子植入程序形成。當然，P型摻雜區域372可經形成具有小於P型重摻雜區域367之任何摻雜濃度分佈。
將P型摻雜區域372併入P-LDMOS裝置中可進一步增加P-LDMOS裝置之P型重摻雜區域367與N型井325之間之一崩潰電壓。因此，P-LDMOS裝置歸因於其較高崩潰電壓而展現出一較高汲極-源極電壓處置能力且當源極的正電荷多於閘極340時亦提供一較高源極-閘極電壓處置能力。應瞭解，雖然已關於P-LDMOS裝置描述摻雜區域，但是原理同樣可適用於N-LDMOS裝置，且就此而言可適用於類似建構之其他電晶體。
關於圖3圖解說明且描述之P-LDMOS及N-LDMOS裝置稱為不對稱裝置。換言之，圖3之半導體裝置之源極及汲極之不對稱本質提供一不對稱裝置。當然，熟習此項技術者應瞭解，源極及汲極(包含其等之輕摻雜區域及重摻雜區域)之尺寸可改變且仍屬於本發明之廣泛範疇內。半導體裝置亦包含由形成於PMOS、NMOS、P-LDMOS及N-LDMOS裝置之閘極、源極及汲極之矽層(其等之一者指定為375)上方之介電質區域380界定之金屬接觸件385。
如本文中介紹，一半導體裝置(亦稱為一「功率半導體裝置」)包含放置在包含較佳地以一分佈式方式具體實施於一LDMOS裝置(亦稱為一「功率MOSFET」或「增強型MOSFET」)中之一MOSFET之一半導體晶粒下方之一或多個去耦電容器，以減小用於驅動器之一電壓源之一阻抗。驅動器可分佈在半導體晶粒之周邊上以實質上等化耦合至MOS裝置之個別MOS單元及LDMOS裝置之LDMOS單元之驅動信號之時序。大體上應瞭解，一LDMOS裝置係藉由將極多個小LDMOS單元 (例如，100,000或更多個單元)之源極及汲極並聯耦合在一共同晶粒中且驅動來自一共同電路節點之並聯LDMOS單元之個別閘極而形成。一設計挑戰係匹配耦合至該等個別閘極之信號之時序使得實質上同時導通或關斷LDMOS單元。不能維持信號與個別閘極之同步可導致半導體裝置故障。在習知設計中，抑制閘極信號之高頻特性使得所得低頻信號實質上同時到達。
現在描述有效地路由信號使其等進出形成於一半導體晶粒內之一LDMOS裝置之一結構之一實施例。在一實施例中，在半導體晶粒內形成複數個LDMOS單元。使用可經形成具有一縱橫比(例如，等於或大於1比1)之金屬柱(例如，長形銅柱)進行分佈式三維去耦在半導體晶粒內形成分佈式圓周信號路徑，以提取自LDMOS裝置之汲極或源極接觸件(或射極或集極接觸件)至分佈式去耦裝置之電流。此結構不依賴於至具有單個去耦點之一電路板之一中間習知封裝接腳及焊錫接頭。汲極接觸件與源極接觸件接觸，但是無須透過如習知積體電路裝置中使用之傳統頂層晶片電鍍金屬而佈線。實情係，使用接觸一導電圖案化導線框(諸如形成於具有複數個小的去耦裝置(例如，去耦電容器)之多個位置中之一印刷電路板之一上表面上之一導電圖案化導線框)之金屬柱之一柵格。去耦裝置分佈且放置在印刷電路板下方之一第三維中。去耦裝置放置在印刷電路板之一下表面上半導體晶粒下方之一導電圖案化導線框上。印刷電路板之上表面上之導電圖案化導線框由複數個通孔耦合至印刷電路板之下表面上之導電圖案化導線框。帶電長型傳輸線之影響因此藉由使用經由金屬柱之柵格下方之導線框及通孔放置在第三維中之多個分佈式去耦裝置而消除。替代地，一導電圖案化導線框可使用半導體晶粒封裝且接著放置在一印刷電路板上。
具有一凸塊底層電鍍金屬方案之一替代性凸狀結構將使凸塊放 置在各位置中。一凸塊通常係使用沈積方法(諸如焊錫材料之氣相沈積)或藉由使用導線接合設備進行球體衝撞而形成。如Simon Tam於2008年3月14日申請之標題為「Transistor Circuit Formation Substrate」之美國專利第7,989,963號中描述，此一製造製程之製造含義可能太昂貴而不能被視為實用。如以下專利中描述之一封裝中之柱及其等至一導線框之連接件的使用係可達成分佈式佈線問題之一實用解決方案之經廣泛確立且具成本效益的製造製程：Tung於2002年6月12日申請之標題為「Pillar Connections for Semiconductor Chips and Method of Manufacture」之美國專利第6,681,982號、Hwee於2001年5月18日申請之標題為「Method for Forming a Flip Chip Semiconductor Package」之美國專利第6,510,976號、Chew於2001年8月21日申請之標題為「Method for Forming a Flip Chip on Leadframe Semiconductor Package」之美國專利第6,550,666號、Tung於2000年4月27日申請之標題為「Pillar Connections for Semiconductor Chips and Method of Manufacture」之美國專利第6,578,754號及Tung於2001年4月26日申請之標題為「Pillar Connections for Semiconductor Chips and Method of Manufacture」之美國專利第6,592,019號。此等專利之各者係以引用的方式併入本文。
現在描述一功率半導體裝置之一實施例。在一態樣中，複數個驅動器(例如，閘極驅動器)位於功率半導體晶粒之周邊上以等化閘極時序且對一驅動器提供低閘極驅動阻抗。在金屬帶及半導體晶粒上產生實體結構以改良一再分佈層(「RDL」)及開關輸出電容Coss。形成且定位諸如鋁帶之金屬帶以將閘極信號路由至個別LDMOS單元以減小閘極電阻並改良閘極驅動信號之時序等化。一閘極驅動偏壓電壓「VDDG」匯流排及接地(「GND」或「PGND」)軌條呈凸狀以減小閘極驅動供應阻抗。
此結構使閘極驅動信號能夠實際上同時到達LDMOS單元之各自閘極處。閘極驅動偏壓電壓匯流排之去耦裝置以一分佈式方式放置在位於半導體晶粒正下方之路徑中。結果係，沿形成為金屬帶之閘極驅動傳輸線傳導之信號呈現低阻抗。
在一實施例中，閘極驅動信號之金屬帶在半導體晶粒上自連接件之周邊延伸至其之一中心區域中之LDMOS單元。金屬帶用於自晶粒周邊至LDMOS單元之閘極驅動連接件。金屬柱形成為電鍍金屬(例如，銅)柱以將位於半導體晶粒下方之一外部去耦裝置耦合至該半導體晶粒上之一點。在一實施例中，至少一去耦裝置位於半導體晶粒正下方。一柱及一去耦裝置耦合至閘極驅動信號之金屬帶之一者之一端。在一實施例中，在上方形成裝填(potting)以對金屬柱提供結構支撐及保護。
現在轉向圖4，圖解說明一半導體裝置405之一實施例之一正視圖，其展示藉由金屬柱(諸如一長形銅柱或柱490)耦合至複數個去耦裝置(例如，去耦或晶片電容器440、441)之一倒置半導體晶粒410。藉由在需要去耦之位置處(諸如半導體晶粒410之周邊位置處)使用金屬柱490及去耦電容器440、441以達成局部去耦。可實質上在一對應柱490下方、半導體晶粒410正上方或正下方放置一或多個去耦電容器440、441以減小電路路徑電感。在實質上位於半導體晶粒410下方之一低電感區域450外部(例如，半導體晶粒區域外部之一區域455中)放置一去耦裝置(例如，去耦或晶片電容器445)會產生可減小去耦電容器445之效能之一較高電感。在低電感區域450中，去耦電容器440、441完全位於半導體裝置405之半導體晶粒區域下方。金屬柱490亦可用以耦合至位於半導體晶粒410之一更中央區域中之一LDMOS裝置之LDMOS單元之大電流源極及汲極端子。
在圖4中，一光阻(例如，一半密耳(~12μm)光阻)經自旋塗佈至 半導體晶粒410之一頂面上，且經蝕刻以形成其中形成金屬柱490之孔。接著移除光阻使得保留懸臂式導電柱。在半導體晶粒410上，首先沈積鋁，接著是一錫-銅或閃爍層/晶種層銅沈積及電鍍。為提供機械穩定性，使用塑膠495(例如，諸如環氧樹脂或聚醯亞胺之一囊封劑)包圍金屬柱490，使得各金屬柱490之一端曝露於塑膠495之一表面上。金屬柱490可形成於聚醯亞胺層中且可自聚醯亞胺層延伸。金屬柱490接觸按原圖界定於一印刷電路板430之一上表面上之一導電圖案化導線框420的島狀物。金屬柱490經回流焊接至導電圖案化導線框420。在印刷電路板430中建構通孔(例如，其等之一者指定為461)以使金屬柱490耦合至印刷電路板430之一下表面上之一導電圖案化導線框421，且耦合至去耦電容器440、441、445之端子。去耦電容器440、441、445使用焊錫凸塊(例如，其等之一者指定為463)之一陣列回流焊接至印刷電路板430之下表面上之導電圖案化導線框421的島狀物。島狀物係小的幾何形狀結構，諸如圖案化導線框中有益於一回流焊接操作以附著一組件之圓形區域。焊錫凸塊(例如，其等之一者指定為462)之一陣列位於印刷電路板430之上表面上之導電圖案化導線框420的島狀物上。因此，去耦電容器440、441、445放置在島狀物上與半導體晶粒410之周邊上的節點相距一段短的垂直距離，以對此等節點之局部電路接地產生低阻抗。金屬柱490係由焊錫凸塊462耦合至導電圖案化導線框420。
半導體晶粒410在附著至印刷電路板430之前如圖4中圖解說明般翻轉，且因此半導體晶粒410下方之金屬柱490與其等「頂」側電接觸。因為該裝置係一高功率裝置，所以(經由一黏著劑480)在半導體晶粒410之一「下」表面上安裝一散熱器470(其經圖解說明位於圖4之頂部中之半導體晶粒410上方)，使得去耦電容器440、441、445可安裝在印刷電路板430上，且在翻轉半導體晶粒410之頂側下。散熱器 470因此接觸半導體晶粒410之下表面。因此，金屬柱490使去耦電容器440、441、445能夠放置在印刷電路板430上緊靠半導體晶粒410之頂側，且形成穿過印刷電路板430之通孔461，以將半導體晶粒410耦合至印刷電路板430下方之去耦電容器440、441、445的陣列。以此方式，對功率半導體裝置405提供一分佈式去耦功能。在一實施例中，相同或一不同導線框可用以耦合至焊錫凸塊或柱之柵格或其他電路元件。一例示性導線框係6毫米(「mm」)x 6mm。圖4中圖解說明之結構可經(例如，以環氧樹脂)裝填/囊封，且所得總成可使用(例如)如由以下專利中描述之一夾具電感器耦合至一導線框：Lotfi等人於2005年10月5日申請之標題為「Magnetic Device Having a Conductive Clip」之美國專利第7,688,172號，該案係以引用的方式併入本文中。
因此，一倒置半導體(例如，矽)晶粒藉由長形金屬柱耦合至一印刷接線或電路板之一上表面，且去耦裝置耦合至印刷電路板在半導體晶粒下方之一下表面。在一實施例中，複數個去耦裝置之至少一者耦合至印刷電路板在半導體晶粒正下方之一下表面。運用此結構，由半導體晶粒與至少一去耦裝置之間之一金屬路徑產生減小的電路阻抗。倒置半導體晶粒、印刷電路板及至少一去耦晶片裝置可易於以一具成本效益的回流焊接程序組裝。此結構避免需要在半導體晶粒結構之一曝露表面上產生複數個交替之小佔據面積的金屬源極及汲極襯墊，否則將需要對附著半導體晶粒之一印刷電路板提供一低電感連接件，藉此促進印刷電路板之佈局。替代地如下文圖解說明且描述，導電圖案化導線框420可與半導體晶粒410及金屬柱490封裝在一封裝半導體裝置內，且接著放置在一印刷電路板430上，使得去耦電容器440、441、445之陣列位於該導線框420下方(參見(例如)圖18，封裝半導體裝置)。
現在轉向圖5，圖解說明使用一圓周環分佈系統形成之一半導體 裝置之一實施例之一平面圖。一N-LDMOS裝置530及一P-LDMOS裝置531表示形成(例如)一降壓或升壓dc-dc功率轉換器之一功率級之一對LDMOS裝置。如上文先前陳述，各LDMOS裝置係由極多個個別LDMOS單元形成。圖5展示N-LDMOS裝置530及P-LDMOS裝置531及驅動最終級，諸如位於(功率半導體裝置之)半導體晶粒之周邊上之N閘極驅動最終級510及P閘極驅動最終級520。一習知設計採用位於半導體晶粒之一端上之N閘極驅動最終級510之僅一結構及P閘極驅動最終級520之僅一結構。在N-LDMOS裝置530及P-LDMOS裝置531之各者之半導體晶粒之一周邊周圍分佈複數個驅動最終級實質上改良耦合至個別LDMOS單元之驅動信號之時序。在各驅動最終級內，有P-MOS單元與N-MOS單元串聯耦合之由一級聯緩衝器驅動之一圖騰柱(totem-pole)配置。驅動最終級並聯電耦合。
在組成各LDMOS裝置之極多個(例如，上千個)LDMOS單元中，控制或閘極端子上之閘極驅動信號應實質上同時且以實質上相同振幅到達。使用一電容器衰減閘極驅動信號之高頻特性以改良相對同時性會折損高頻操作之效率。該設計中包含複數個去耦裝置以對閘極驅動器之閘極驅動偏壓電壓VDDG匯流排提供低阻抗，但不會減緩閘極驅動器。去耦裝置減小供應至分佈式驅動器之閘極驅動偏壓電壓VDDG匯流排之阻抗。閘極驅動信號仍保留一定的傳播延遲變動，但是該變動之最大部分由分佈式閘極驅動結構而消除。
現在轉向圖6，圖解說明形成為一半導體晶粒上之一沈積物之一再分佈層之一實施例之一平面圖。再分佈層(例如，一銅再分佈層)跨半導體晶粒之表面分佈功率及接地節點且分佈耦合至LDMOS單元之其他電路節點。再分佈層亦用以將控制及監控信號分佈至閘極驅動器。
小圓圈(標記為「SW」、「PGND」、「PVIN」等等)係將LDMOS單 元及其他電路節點耦合至上文先前參考圖4描述之一導電(例如，銅)圖案化導線框420或下文參考圖17D描述之一導線框1179之長形金屬(例如，銅)柱之位置。標記為「SW」之小圓圈(其等之一者指定為610)形成將P-LDMOS單元之汲極及N-LDMOS單元之汲極耦合在一起且將該等汲極耦合至諸如圖1中圖解說明之輸出電感器Lout之一外部輸出電感器之一電路節點。標記為「PVIN」之小圓圈(其等之一者指定為620)對形成高側P-LDMOS裝置之LDMOS單元之源極提供一正偏壓電壓，且標記為「PGND」之小圓圈(其等之一者指定為630)對形成低側N-LDMOS裝置之LDMOS單元之源極提供局部電路接地。在再分佈層之周邊處，標記為「VDDG」之小圓圈(其等之一者指定為640)對驅動LDMOS單元之閘極之閘極驅動反相器(亦稱為「閘極驅動器」或「驅動器」)供應正偏壓電壓，且標記為「PGND」之小圓圈(其等之一者指定為650)對閘極驅動反相器供應局部電路接地。
現在轉向圖7，圖解說明圖6中所圖解說明之再分佈層之一平面圖，其具有展示N-LDMOS裝置530及P-LDMOS裝置531(參見圖5)之一輪廓之一覆疊。此外，展示N閘極驅動最終級510及P閘極驅動最終級520之位置之輪廓亦加以展示。在一實施例中，使用220,000個帶形成N-LDMOS裝置530，各帶表示約20微米寬且約2微米至3微米通道長度之一N-LDMOS單元。在一實施例中，使用約相同大小之120,000個帶形成P-LDMOS裝置531。
現在轉向圖8及圖9，圖解說明圖6中圖解說明之再分佈層之放大平面圖。在周邊周圍的是驅動N-LDMOS單元及P-LDMOS單元之閘極之閘極驅動反相器的三個路徑。一路徑800對閘極驅動反相器提供正閘極驅動偏壓電壓VDDG匯流排，且一路徑805對反相器提供局部電路接地。一路徑N_Drv 810係由閘極驅動反相器產生之閘極驅動信號。一路徑N_Drv 830在另一銅/金屬層上且與路徑N_Drv 810電互 通。路徑N_Drv 830耦合至N-LDMOS單元之閘極。路徑820係再分佈層下方之進一步電鍍金屬(例如，20μm電鍍金屬)，且路徑840表示耦合至N-LDMOS單元之閘極多晶矽層或帶(大體上稱為「閘極」)之20μm電鍍金屬。圖9圖解說明N-LDMOS單元之閘極多晶矽帶910。應瞭解，閘極可由諸如一導電金屬材料之其他材料形成。
現在轉向圖10，圖解說明一NMOS反相器鏈之一實施例之一示意圖，該NMOS反相器鏈經組態以由一PWM信號SPWM產生圖1中圖解說明用於一N-LDMOS裝置之一大振幅閘極驅動信號SDRV2。如圖10中圖解說明之偶數個(例如，四個)反相器序列由低振幅工作循環信號SPWM產生具有一相同指向之大振幅閘極驅動信號SDRV2。NMOS反相器鏈在圖5及圖7上被標記為「N閘極驅動最終級」，且分佈在該裝置之周邊周圍。
反相器鏈之輸出級係使用第一反相器1010及第二反相器1020之一並聯驅動配置而形成。第一反相器1010係使用PMOS裝置1011及NMOS裝置1012形成。第二反相器1020係使用PMOS裝置1021及NMOS裝置1022形成。第一反相器1010係由使用較小MOS裝置(通常約為第一反相器1010中之MOS裝置之大小的三分之一)形成之一第三反相器1030驅動。類似地，第三反相器1030係由使用MOS裝置(約為第三反相器1030中之MOS裝置之大小的三分之一)形成之一第四反相器1040驅動。以此方式，圖1中圖解說明之低位準輸入信號(PWM信號SPWM)在使用連續增大之MOS裝置形成之級中連續被放大以產生圖1中圖解說明之具有足夠大振幅之閘極驅動信號SDRV2以驅動圖1中圖解說明之輔助開關Qaux。
對應於圖10中圖解說明之NMOS反相器鏈之一PMOS反相器鏈可使用偶數個反相器級建構以對一P-LDMOS裝置由低振幅輸入信號SPWM產生一大振幅相同指向閘極驅動信號。PMOS反相器鏈將因此在 與NMOS反相器鏈互補之一時間週期中操作，且時間間隔足夠大以避免在圖1中圖解說明之一主開關Qmn及輔助開關Qaux之串聯電路配置中產生貫通電流。雖然已描述採用NMOS及PMOS裝置之NMOS及PMOS反相器鏈，但是應瞭解N-LDMOS及P-LDMOS裝置亦可加以使用而獲益。
因此，如上文參考隨附圖式圖解說明且描述，已介紹一種半導體裝置及其形成方法。在一實施例中，半導體裝置包含使用複數個LDMOS單元形成之一半導體晶粒、電耦合至該複數個LDMOS單元之一再分佈層、分佈在該再分佈層上方且電耦合至該再分佈層之複數個金屬柱(例如，形成為電鍍柱之銅柱)及藉由該複數個金屬柱電耦合至該再分佈層之一導電圖案化導線框。半導體裝置進一步包含電耦合至該再分佈層且透過該再分佈層電耦合至該複數個LDMOS單元之閘極之一閘極驅動器。半導體裝置係使用一囊封劑裝填，使得導電圖案化導線框之部分經曝露以用作半導體裝置之外部接觸件。外部接觸件之數者耦合至一印刷電路板且外部接觸件之數者(例如，透過印刷電路板之一相對表面上之通孔)耦合至複數個去耦裝置。該複數個去耦裝置之至少一者位於半導體晶粒下方。外部接觸件之數者耦合至閘極驅動器，其等電耦合至再分佈層且透過再分佈層電耦合至該複數個LDMOS單元之閘極，且外部接觸件之數者透過再分佈層耦合至該複數個LDMOS單元之汲極或源極。
現在轉向圖11，圖解說明一半導體裝置或其部分中具體實施之一部分建構N-LDMOS裝置之一部分之一實施例之一簡化三維視圖。根據半導體產業中之標準慣例，此等圖式及後續圖式中之各種特徵並未按比例繪製。為使本文中之論述清晰，可能任意增大或減小各種特徵之尺寸，且構成半導體裝置之不同裝置之類似特徵可採用相似參考數字。
N-LDMOS裝置係形成於包含一輕摻雜P基板1105及植入於輕摻雜P基板1105中之一P井1108之一半導體晶粒中。P井1108包含呈交替圖案之一序列之摻雜源極區域「s」及汲極區域「d」，其等佈局為平行帶於P井1108中或當未植入選用P井1108時直接位於輕摻雜P基板1105上方。源極金屬(例如，鋁)帶(其等之一者指定為1111、1112)形成於一實質上平坦第一金屬(例如，鋁)層M1中且位於摻雜源極區域「s」上方且電接觸摻雜源極區域「s」但並未彼此接觸。對應地，汲極金屬(例如，鋁)帶(其等之一者指定為1121、1122)亦形成於第一金屬層M1中且位於摻雜汲極區域「d」上方且電接觸摻雜汲極區域「d」但並未彼此接觸。因此，在第一金屬層M1中於輕摻雜P基板1105上形成複數個交替源極及汲極金屬帶，且其等平行於複數個源極及汲極區域之各自者並(例如，透過矽化物層)與複數個源極及汲極區域之各自者形成一電接觸。閘極氧化物帶(其等之一者指定為1140)使多晶矽閘極帶(其等之一者指定為1150)與下伏P井1108隔離或當未植入選用P井1108時與輕摻雜P基板1105隔離。因此，在輕摻雜P基板1105上方於複數個源極及汲極區域之一者之間且平行於複數個源極及汲極區域之一者形成複數個閘極多晶矽帶1150，且該複數個閘極多晶矽帶1150經定向平行於該複數個交替源極及汲極金屬帶。圖11中未展示形成於P井1108中或輕摻雜P基板1105中之位於摻雜源極區域「s」與摻雜汲極區域「d」之間並使其等分離之額外及不同摻雜帶。第一金屬層M1中之一閘極金屬(例如，鋁)帶1130位於閘極多晶矽帶1150上方、垂直於閘極多晶矽帶1150對準且電耦合至閘極多晶矽帶1150。
現在轉向圖12，圖解說明在形成一實質上平坦第二金屬(例如，鋁)層M2之後該部分建構N-LDMOS裝置之一部分之一簡化三維視圖。 第二金屬層M2係形成於位於形成於第一金屬層M1中之各自源極金屬帶1111、1112及汲極金屬帶1121、1122上方之帶中(諸如源極金屬(例 如，鋁)帶(其等之一者指定為1160)及汲極金屬(例如，鋁)帶(其等之一者指定為1161))。氮氧化矽之一隔離或絕緣層(參見(例如)圖19)使第一金屬層與第二金屬層分離且電隔離。第二金屬層M2層中位於第一金屬層M1中之源極金屬帶1111、1112上方之源極金屬帶1160由導電通孔耦合至源極金屬帶1111、1112。類似地，第二金屬層M2層中位於第一金屬層M1中之汲極金屬帶1121、1122上方之汲極金屬帶1161由導電通孔耦合至汲極金屬帶1121、1122。因此，在第二金屬層M2中於第一金屬層M1上形成第二複數個交替源極及汲極金屬帶，其等上覆且平行於該第一複數個交替源極及汲極金屬帶之一者。該第一複數個源極及汲極金屬帶由通孔電耦合至各自第二複數個交替源極及汲極金屬帶。第二金屬層M2中之源極金屬帶1160及汲極金屬帶1161並未耦合至第一金屬層M1中之閘極金屬帶1130，閘極金屬帶1130與閘極多晶矽帶1150相交並電耦合至閘極多晶矽帶1150。
現在轉向圖13，圖解說明在形成該第二金屬層M2之後該部分建構N-LDMOS裝置之一部分之一簡化平面圖。圖13圖解說明將第一金屬層M1中之源極金屬帶1111、1112、1113、1114電耦合至第二金屬層M2中之源極金屬帶1160、1162之通孔(其等之一者指定為1175)。類似地，通孔(其等之一者指定為1176)將第一金屬層M1中之汲極金屬帶1121、1122、1123、1124電耦合至第二金屬層M2中之汲極金屬帶1161、1163。通孔1175、1176穿透一隔離或絕緣層(參見(例如)圖19中之絕緣層1915)，該隔離或絕緣層使第一金屬層M1與第二金屬層M2分離並電隔離(絕緣)。應注意，在一實施例中，通孔並未將第一金屬層M1中之閘極金屬帶1130電耦合至第二金屬層M2中之源極金屬帶1160、1162或汲極金屬帶1161、1163。
現在轉向圖14，圖解說明在形成一實質上平坦第三金屬(例如，鋁)層M3之後該部分建構N-LDMOS裝置之一部分之一簡化三維視圖。 第三金屬層M3上覆第二金屬層M2。圖14圖解說明形成於第三金屬層M3中之N-LDMOS裝置源極接觸件1170及亦形成於第三金屬層M3中之N-LDMOS裝置汲極接觸件1171。氮氧化矽之一隔離或絕緣層(參見(例如)圖19)使第二金屬層與第三金屬層分離且電隔離。N-LDMOS裝置汲極接觸件1171係共用於形成於相同晶粒上之一P-LDMOS裝置汲極接觸件(亦稱為一「N-LDMOS/P-LDMOS裝置汲極接觸件」1171)。N-LDMOS裝置源極接觸件1170由通孔(例如，圖14中未展示之鋁通孔)電耦合至第二金屬層M2中之源極金屬帶(其等之一者指定為1160)。N-LDMOS/P-LDMOS裝置汲極接觸件1171由通孔(例如，圖14中未展示之鋁通孔)電耦合至第二金屬層M2中之汲極金屬帶(其等之一者指定為1161)。因此，形成於第三金屬層M3中之源極及汲極接觸件由通孔電耦合至第二金屬層M2中之該第二複數個交替源極及汲極金屬帶之一者且實質上覆蓋該複數個源極及汲極區域。
現在轉向圖15，圖解說明在形成該第三金屬層M3之後該部分建構N-LDMOS裝置之一部分之一簡化平面圖。圖15圖解說明將形成於第三金屬層M3中之N-LDMOS裝置源極接觸件1170電耦合至第二金屬層M2中之源極金屬帶1160、1162、1164之通孔(其等之一者指定為1180)。圖15中亦圖解說明將形成於第三金屬層M3中之N-LDMOS/P-LDMOS裝置汲極接觸件1171電耦合至第二金屬層M2中之汲極金屬帶1161、1163、1165之通孔(其等之一者指定為1181)。亦展示將形成於第三金屬層M3中之N-LDMOS/P-LDMOS裝置汲極接觸件1171電耦合至一P-LDMOS裝置之第二金屬層M2中之P-LDMOS裝置汲極金屬帶1185、1187、1189之通孔(其等之一者指定為1182)。P-LDMOS裝置之第二金屬層M2中之P-LDMOS源極金屬帶1184、1186、1188係由通孔電耦合至第三金屬層M3中之一P-LDMOS裝置源極接觸件(圖15中未展示)。通孔1180、1181、1182穿透一隔離或絕緣層(參見(例如)圖19中 之絕緣層1915)，該隔離或絕緣層使第二金屬層M2與第三金屬層M3分離並電隔離(絕緣)。圖15中亦圖解說明第一金屬層M1中與閘極多晶矽帶1150(參見圖14)相交並電耦合至閘極多晶矽帶1150(參見圖14)之閘極金屬帶1130。
現在轉向圖16，圖解說明包含N-LDMOS及P-LDMOS裝置之一部分建構半導體裝置之一實施例之一簡化三維視圖，其圖解說明該部分建構半導體裝置之第二金屬層M2中之源極金屬帶及汲極金屬帶之一幾何形狀。圖16圖解說明半導體晶粒之周邊處耦合至N-LDMOS及P-LDMOS裝置之閘極驅動器，諸如一N閘極驅動器1191及P閘極驅動器1192。因此，在半導體晶粒之周邊周圍，N-LDMOS裝置具有複數個N閘極驅動器(諸如N閘極驅動器1191)且P-LDMOS裝置具有複數個P閘極驅動器(諸如P閘極驅動器1192)。圖16中亦圖解說明位於半導體晶粒之周邊處之邏輯電路元件，諸如邏輯電路元件1193。第二金屬層M2上之電鍍金屬藉由如先前上文描述之通孔上覆且電耦合至第一金屬層M1上之各自電鍍金屬。為簡化圖解說明，圖16中未圖解說明第一金屬層M1下伏第二金屬層M2之部分。圖16中亦展示第一金屬層M1中與N-LDMOS及P-LDMOS裝置之閘極多晶矽帶(未展示)相交且電耦合至該等閘極多晶矽帶之閘極金屬帶1130、1131。為符合先前圖式之目的，圖16中指定N-LDMOS裝置之第二金屬層M2中之源極金屬帶1160及汲極金屬帶1161及P-LDMOS裝置之第二金屬層M2中之源極金屬帶1184及汲極金屬帶1185。
現在轉向圖17，圖解說明包含N-LDMOS及P-LDMOS裝置之部分建構半導體裝置之一簡化三維視圖，其圖解說明第三金屬層M3中之源極及汲極接觸件(即，導電區域)之一幾何形狀。圖17中圖解說明輕P摻雜基板1105，但是未展示位於其之一上部中之選用P井。N-LDMOS/P-LDMOS裝置汲極接觸件1171位於第三金屬層M3中之N- LDMOS裝置源極接觸件1170與一P-LDMOS裝置源極接觸件1172之間。圖17亦圖解說明位於第三金屬層M3中之半導體裝置之周邊處之閘極驅動器及邏輯電路元件接觸件(其等之一者指定為1173)。
現在轉向圖17A，圖解說明包含N-LDMOS及P-LDMOS裝置之部分建構半導體裝置之一簡化三維視圖，其圖解說明一再分佈層(例如，一銅再分佈層)之通孔(例如，銅通孔，其等之一者指定為1174)之一幾何形狀。銅通孔1174在第三金屬層M3與再分佈層之間提供電接觸。銅通孔1174穿透一隔離或絕緣層(參見(例如)圖19中之第一聚醯亞胺層1935)，其使第三金屬層M3與再分佈層分離且電隔離(絕緣)。
現在轉向圖17B，圖解說明包含N-LDMOS及P-LDMOS裝置之部分建構半導體裝置之一簡化三維視圖，其圖解說明一再分佈層(例如，一銅再分佈層)1177之一幾何形狀。再分佈層1177展示為圖案化於第三金屬層M3上之各自電鍍金屬上方且藉由銅通孔1174(參見圖17A)電耦合至第三金屬層M3上之電鍍金屬。此外，再分佈層1177藉由一隔離層或絕緣層(參見圖19)與第三金屬層M3分離。
現在轉向圖17C，圖解說明包含N-LDMOS及P-LDMOS裝置之部分建構半導體裝置之一簡化三維視圖，其圖解說明再分佈層1177之柱(例如，銅柱，其等之一者指定為1178)之一幾何形狀。銅柱1178在再分佈層1177與一導電圖案化導線框之間提供電接觸。
現在轉向圖17D，圖解說明包含N-LDMOS及P-LDMOS裝置之部分建構半導體裝置之一簡化三維視圖，其圖解說明一導電圖案化導線框1179之一幾何形狀。導線框1179展示為圖案化於再分佈層1177上方且藉由銅柱1178(參見圖17C)電耦合至再分佈層1177。
現在轉向圖18，圖解說明包含N-LDMOS及P-LDMOS裝置之一裝填半導體裝置(裝填有諸如環氧樹脂之一囊封劑)之一實施例之三維外部視圖。導線框1179(參見圖17D)之部分經曝露以用作半導體裝置之 外部接觸件。一外部N-LDMOS/P-LDMOS裝置汲極接觸件1194位於一外部N-LDMOS裝置源極接觸件1195與一外部P-LDMOS裝置源極接觸件1196之間，且外部閘極驅動器及邏輯電路元件接觸件(其等之一者指定為1197)位於半導體裝置之一周邊周圍。在一實施例中一可用裝填材料係諸如環氧樹脂之一囊封劑，但是包含具有增強熱特性之裝填材料之其它裝填材料預期在本發明之廣泛範疇內。半導體裝置之外部電接觸表面可塗佈有一銅閃爍層/晶種層且接著電鍍銅以形成一可容易焊接金屬表面。外表面亦可鍍敷一薄金層或其它惰性金屬或合金層以提供用於焊接或其他附著程序之一進一步鈍化層級。如關於圖4圖解說明且描述，圖18之裝填或封裝半導體裝置可置於最靠近一去耦裝置之一印刷電路板上以提供如上文陳述之優點。
現在轉向圖19，圖解說明包含N-LDMOS及/或P-LDMOS裝置之一半導體裝置之一部分之一實施例之一正視圖。N-LDMOS及/或P-LDMOS裝置形成於一半導體晶粒中，該半導體晶粒包含位於一輕摻雜基板1905上方之一井1910，且摻雜源極區域「s」及汲極區域「d」位於其中。第一金屬層M1、第二金屬層M2及第三金屬層M3藉由氮氧化矽層(概括地指定為1915)彼此分離且絕緣，且位於摻雜源極區域「s」及摻雜汲極區域「d」上方並與其等電接觸。通孔(其等之一者指定為1920)在第一金屬層M1及第二金屬層M2上之電鍍金屬之間提供電接觸。通孔(其等之一者指定為1925)在第二金屬層M2及第三金屬層M3上之電鍍金屬之間提供電接觸。銅通孔(其等之一者指定為1930)形成於一第一聚醯亞胺層1935中以在第三金屬層M3與形成於第一聚醯亞胺層1935上之一銅再分佈層1940之間提供電接觸。銅柱(其等之一者指定為1945)形成於一第二聚醯亞胺層1950中以在銅再分佈層1940與形成於第二聚醯亞胺層1950上之一銅導線框1955之間提供電接觸。應瞭解，各自層之特定材料僅係實例且具有類似性質之其他材料可加 以使用而獲益。
因此，如上文參考隨附圖式圖解說明且描述，已介紹一種半導體裝置及其形成方法。在一實施例中，半導體裝置包含使用複數個LDMOS單元形成之一半導體晶粒、電耦合至該複數個LDMOS單元之一金屬層(例如，形成一再分佈層之複數個銅層)及沿半導體晶粒之一周邊定位且透過金屬層電耦合至該複數個LDMOS單元之閘極之閘極驅動器(例如，包含形成為MOS裝置之驅動器開關之閘極驅動器之一者)。金屬層用以將閘極驅動器之一者耦合至一閘極驅動偏壓電壓且耦合至控制及監控信號。半導體裝置亦包含分佈在金屬層上方且電耦合至金屬層之複數個金屬柱；及電耦合至該複數個金屬柱之一導電圖案化導線框。半導體裝置係使用一囊封劑裝填，使得導電圖案化導線框之部分經曝露以用作半導體裝置之外部接觸件。外部接觸件之一者透過一印刷電路板之一相對表面上之通孔耦合至複數個去耦裝置。外部接觸件之一者透過金屬層耦合至閘極驅動器，且外部接觸件之一者透過金屬層耦合至該複數個LDMOS單元之汲極或源極。
現在轉向圖20，圖解說明一半導體裝置或其部分中具體實施之一N-LDMOS裝置之一實施例之一橫截面視圖。雖然將關於圖20介紹N-LDMOS裝置之一些層，但是亦將關於圖21及其他圖式描述建構該等層之程序之一更詳細解釋。在包含一P摻雜半導體基板(亦稱為一「基板」)2005之一半導體晶粒中形成N-LDMOS裝置，且可在該基板之一表面上生長一選用磊晶層(例如，一輕摻雜P型磊晶層，未展示)。雖然在已圖解說明之實施例中基板2005係一P型基板，但是熟習此項技術者應瞭解，在不脫離本發明之範疇之情況下，基板2005可為一N型基板。
N-LDMOS裝置係由複數個N-LDMOS單元(諸如圖20中圖解說明之N-LDMOS單元2001)形成。N-LDMOS裝置包含P型井2015及形成於 P型井2015上方之重摻雜P型區域2090。在重摻雜P型區域2090之任一側上或其上形成重摻雜N型區域2060、2080。重摻雜N型區域2060經形成尤其在遠離重摻雜N型區域2080之一橫向方向上具有低於重摻雜N型區域2080之一摻雜密度。重摻雜N型區域2060、2080透過形成於其等上方之矽化物層2115提供一歐姆接面。矽化物層2115在重摻雜N型區域2060、2080與一第一金屬(例如，鋁)層M1之間提供一強導電接面以最終對N-LDMOS裝置提供源極接觸件(指定為「接合源極(接觸件)」)。位於重摻雜P型區域2090上方之重摻雜N型區域2080較薄(例如，約10Å至100Å)使得藉此形成於摻雜N型區域2080與重摻雜P型區域2090之間之所得P-N接面將為實質上係在兩個方向上皆強導電之一歐姆接面。因此，形成於其等之間之P-N接面將不能用作二極體。類似地，矽化物層2115在重摻雜N型區域2080與第一金屬層M1之間提供一強導電接面以最終對N-LDMOS裝置提供汲極接觸件(指定為「接合汲極(接觸件)」)。源極及汲極之第一金屬層M1係藉由諸如非晶矽氮氧化物(「SixOyNz」)層2120之一絕緣層分離。
在P型井2015內於重摻雜N型區域2060及重摻雜P型區域2090附近形成P型區域2055。在重摻雜N型區域2060與輕摻雜N型區域2070之間的閘極下方形成通道區域2003。P型區域2055係藉由在將形成於通道區域2003上之閘極下方以偏離垂直面之一角度進行離子注入而形成於P型井2015中，且P型區域2055係用以控制N-LDMOS裝置之一臨限電壓。
該等閘極係形成具有閘極多晶矽層2025，閘極多晶矽層2025在周圍具有下伏閘極氧化物層2020及上覆閘極氧化物層2030以及側壁間隔件(其等之一者指定為2040)。通道區域2003上之閘極多晶矽層2025控制其中的導電率位準。下伏閘極氧化物層2020在閘極多晶矽層2025及P型井2015及P型區域2055之間形成一隔離層。移除上覆閘極氧化物 層2030在閘極多晶矽層2025上方之一部分且在該部分上方形成矽化物層2115以減小閘極電阻。
因此，閘極多晶矽層2025(連同矽化物層2115)跨N-LDMOS裝置之許多N-LDMOS單元形成閘極多晶矽帶1150且耦合至第一金屬層M1中之閘極金屬帶1130(參見(例如)圖11)。閘極金屬帶1130佈線至位於半導體裝置之周邊處之複數個閘極驅動器(參見(例如)圖16)。藉由將第一金屬層M1中之閘極金屬帶1130(其等具有實質上大於閘極多晶矽帶1150之導電率)耦合至該複數個閘極驅動器而藉此對該N-LDMOS單元之閘極啟用一實質上時間對準切換信號。
鑑於閘極及源極以及汲極之間產生之大量有效電容，將一時間對準切換信號提供給個別N-LDMOS單元之該複數個閘極係一項重要的設計考慮，該電容需要大量閘極驅動電流以達成一快速切換轉變。不能對個別N-LDMOS單元之閘極產生一時間對準閘極驅動信號可使得能夠在導通一些N-LDMOS單元之前導通其他N-LDMOS單元，這迫使早期切換的單元在時間上錯位切換轉變期間傳導大電流脈衝。時間上錯位大電流脈衝將N-LDMOS單元曝露於裝置故障。
已圖解說明之結構亦使得能夠使用一共同半導體晶粒中之實質上相同結構形成N-LDMOS及P-LDMOS裝置，且使得能夠使用一低電感大電流路徑將各LDMOS類型耦合至一外部電路。各LDMOS經形成具有單個大的源極接觸件及單個大的且共用的汲極接觸件(參見(例如)圖17)，這可簡化一外部電路之電路板佈局及附著問題。大的源極及汲極接觸件容易覆疊具有實質上與大的源極及汲極接觸件(參見(例如)圖17B)相同之佔據面積之一銅再分佈層，且最終覆疊一導線框(參見(例如)圖17D)，這進一步改良導電率並將一封裝半導體裝置(參見(例如)圖18)耦合至一外部電路。源極接觸件及共用汲極接觸件上覆N-LDMOS及P-LDMOS裝置之實質上整個作用區域，使得未上覆作用切 換區域之大電流接觸件浪費的晶粒區域較少。
關於N-LDMOS單元2001，源極(或源極區域)係具體實施於至少該重摻雜N型區域2060中，且汲極(或汲極區域)係具體實施於該輕摻雜N型區域2070(例如，一輕摻雜汲極(「LDD」)區域)及與通道區域2003相對之一相鄰重摻雜N型區域2080中。閘極駐留在具有如本文中介紹之層之通道區域2003上。LDD區域對N-LDMOS裝置提供高於習知設計之一崩潰電壓。按「重摻雜源極區域」、「閘極」、「輕摻雜汲極區域」及「重摻雜汲極區域」的順序形成此等區域。P-LDMOS裝置中採用類似於關於圖88及其他圖式描述之結構之一結構。
現在轉向圖21至圖87，圖解說明形成一半導體裝置或其部分中具體實施之一N-LDMOS裝置之一實施例之橫截面視圖。開始於圖21，在包含一P摻雜半導體基板(亦稱為一「基板」)2005之一半導體晶粒中形成N-LDMOS裝置，且可在該基板之一表面上生長一選用磊晶層(例如，一輕摻雜P型磊晶層，未展示)。基板2005較佳地輕P摻雜(例如，硼)介於1．1014個原子/cm3與1．1016個原子/cm3之間。尤其當基板2005係一輕摻雜P型基板時，不一定需要在基板2005上生長選用磊晶層。雖然在已圖解說明之實施例中基板2005係一P型基板，但是熟習此項技術者應瞭解，在不脫離本發明之範疇之情況下，基板2005可為一N型基板。
基板2005係形成有隔離區域(例如，淺溝渠隔離區域2010)。淺溝渠隔離區域2010亦可形成於一基板內或生長在該基板上之一磊晶層內以在實施於該基板上或磊晶層上之裝置之間提供介電質隔離。淺溝渠隔離區域2010係藉由使用一光阻塗佈、圖案化及蝕刻基板2005以界定其中的各自區域而形成。一例示性光阻係一AZ電子材料光阻。接著蝕刻並使用諸如二氧化矽、氮化矽、其等之一組合或任何其他合適的介電質材料之一介電質回填淺溝渠隔離區域2010。接著，藉由諸如一 化學機械平坦化(「CMP」)磨薄程序之一磨薄程序平坦化基板2005之磊晶層及淺溝渠隔離區域2010以平坦化該裝置並同時限制對晶粒的表面破壞。遮罩、蝕刻、回填介電質及磨薄之步驟在此項技術中廣為人知且將不會在下文中予以進一步詳細描述。
P型基板2005藉由淺溝渠隔離區域2010分成介電質分離區域以在已圖解說明之實施例中容納複數個N-LDMOS及P-LDMOS裝置以及閘極驅動器及嵌入位於P型基板2005上之控制電路中用作低電壓裝置之其他PMOS及NMOS裝置。低電壓裝置可在(例如)一功率轉換器之一控制器內(例如，可形成於半導體裝置之一表面上之控制及信號處理裝置內)操作。此外，P型基板2005可容納用作(例如)一電力系統以及一功率轉換器(即，功率開關及驅動器開關)之一驅動器內之較高電壓裝置之N-LDMOS及P-LDMOS裝置。
現在轉向圖22，藉由塗佈且圖案化一光阻遮罩(未展示)接著蝕刻光阻遮罩以界定被P型井2015佔據之區域來形成P型井2015。(例如，在約100千電子伏特(「keV」)至300keV之一控制能量下)藉由諸如硼之一適當P型摻雜劑物種之一離子植入程序形成P型井2015，且導致較佳地在約1．1017個原子/cm3至2．1019個原子/cm3之一範圍中之一摻雜濃度分佈。
現在轉向圖23，在符合閘極之所期待操作電壓之一厚度之半導體裝置之表面上方形成一閘極氧化物層2020(一絕緣層)。閘極氧化物層2020通常係(例如)藉由以下操作形成之二氧化矽：在一烤箱中放置其上面形成矽裝置之晶圓；及對採用約0.25微米(「μm」)特徵大小且在低閘極電壓下(例如，2.5伏特)操作之裝置使晶圓之曝露表面與氧氣或具有約30埃(「Å」)至50Å之一厚度之其他合適的材料在500℃至900℃下發生反應持續10分鐘至100分鐘(諸如以產生一高κ(介電常數)堆疊)。假定N-LDMOS及P-LDMOS裝置之閘極-源極電壓限制限於(例 如，約2.5伏特之)一電壓，則可使用如上文陳述之一閘極介電質層厚度形成閘極氧化物層2020。較佳地，閘極氧化物層2020經建構具有一均勻厚度以對該等裝置提供使該裝置之順向導電性質完全或幾乎完全飽和之大約2.5伏特之一閘極-源極額定電壓。當然，該等裝置之前述提及之閘極電壓範圍係僅為了闡釋性目的而提供，且預期其他電壓範圍在本發明之廣泛範疇內。
現在轉向圖24，在閘極氧化物層2020之一表面上方沈積一閘極多晶矽層2025且在一後續處理步驟中使用諸如具有約1．1019至5．1020之一範圍中之一摻雜密度之一適當摻雜物種(諸如砷)對閘極多晶矽層2025進行N型(或P型)摻雜以獲得一合適位準的導電率。在一烤箱中在一高溫下退火閘極多晶矽層2025(例如，在攝氏800度(「℃」)至攝氏1000℃之一溫度下持續2分鐘至60分鐘)以適當地擴散並活化摻雜劑。閘極多晶矽層2025可具有可自約100奈米至約500奈米之一厚度範圍，但是取決於一應用可具有更小或更大的厚度範圍。
現在轉向圖25，藉由以下操作在閘極多晶矽層2025之一上表面上方形成一上覆閘極氧化物層2030(一絕緣層)：在一烤箱中放置其上面形成矽裝置之晶圓；及使閘極多晶矽層2025之曝露表面與氧氣在一高溫下發生反應(例如，在500℃至900℃之一溫度下持續1分鐘至60分鐘)。上覆閘極氧化物層2030可經形成具有約50Å至500Å之一厚度。
現在轉向圖26，圖案化並蝕刻閘極氧化物層2020、閘極多晶矽層2025及上覆閘極氧化物層2030以界定並形成其等之水平尺寸。搭配一蝕刻採用一光阻遮罩以界定閘極多晶矽層2025、閘極氧化物層2020及上覆閘極氧化物層2030之橫向尺寸。在下列圖式中僅使用參考數字指定閘極多晶矽層2025及閘極氧化物層2020、2030之閘極之一者。一例示性光阻係AZ電子材料光阻。圖案化並蝕刻以界定並形成閘極多晶矽層2025及閘極氧化物層2020、2030之水平尺寸之步驟在此項技術 中廣為人知且將不會在下文予以進一步詳細描述。在一替代性實施例中，閘極多晶矽層2025可包含或以其他方式經形成具有多種材料，包含各種金屬、其他摻雜半導體或其他導電材料。應注意，可在相同處理步驟中遮罩並蝕刻閘極多晶矽層2025及閘極氧化物層2020、2030之水平尺寸以及形成於相同矽上之一N-LDMOS及P-LDMOS裝置二者之多種其他結構。
現在轉向圖27，已在半導體裝置上方沈積氮化矽(「Si3N4」)2035之一上覆層(一絕緣層)。在半導體裝置上方沈積氮化矽2035之上覆層係此項技術中之一習知程序且將不會在本文進一步描述。
現在轉向圖28，幾乎到處(惟氮化矽層2035與由閘極多晶矽層2025及下伏氧化物層2020及上覆氧化物層2030形成之側壁相鄰之垂直厚的部分以外)回蝕氮化矽2035之上覆層。以此方式，在一自對準程序中且無須遮罩及蝕刻一光阻而由與閘極多晶矽層2025及下伏氧化物層2020及上覆氧化物層2030相鄰之氮化矽層2035形成側壁間隔件(其等之一者指定為2040)。
現在轉向圖29，在一後續處理步驟中塗佈、圖案化且蝕刻一光阻2045以界定N-LDMOS裝置之源極區域以使諸如硼離子之P型離子能夠植入至半導體裝置之選定區域中。蝕刻光阻以曝露一閘極寬度的一半，其係約0.2μm(指定為2050)以適應圖案化及蝕刻光阻時之容限問題。因此，P型離子植入之橫向位置受控於使用此項技術中已知的技術之一光阻遮罩。塗佈、圖案化並蝕刻一光阻之步驟在此項技術中廣為人知且將不會在本文進一步詳細描述。
現在轉向圖30，植入P型離子(例如，在約20keV至100keV之一控制能量下約5．1017個原子/cm3至1．1019個原子/cm3)以形成P型區域2055。P型區域2055係經一合適的原子物種(諸如硼)進行離子植入以使已形成之N-LDMOS裝置達成一可用閘極臨限電壓。
現在轉向圖31，植入N型離子(例如，砷)以形成重摻雜N型區域2060。重摻雜N型區域2060經植入(例如，在約5keV至50keV之一控制能量下)具有較佳地在5．1018個原子/cm3至1．1020個原子/cm3之一範圍中之一摻雜濃度分佈以使已形成之N-LDMOS裝置達成一低源極電阻。在如圖32中圖解說明般剝除光阻2045之後，(例如，在一烤箱中在700℃至1000℃之一溫度下持續1分鐘至60分鐘)退火半導體裝置以將P型區域2055及重摻雜N型區域2060轉換為作用基板部位。
現在轉向圖33，塗佈、圖案化且蝕刻一光阻2065使得在一後續處理步驟處可在由閘極多晶矽層2025及下伏氧化物層2020及上覆氧化物層2030形成之閘極之間之區域中選擇性地植入N型離子。如圖34中圖解說明，在閘極之間植入N型離子(例如，砷離子)以形成輕摻雜N型區域2070。在一實施例中，輕摻雜N型區域2070之植入密度較佳地在1．1017個原子/cm3至1．1019個原子/cm3之範圍中且係在10keV至200keV之一控制能量下植入。
在如圖35中圖解說明般剝除光阻2065之後，在一烤箱中退火半導體裝置以將輕摻雜N型區域2070轉換為作用基板部位(例如，在700℃至1000℃之一溫度下持續1分鐘至60分鐘)。現在轉向圖36，塗佈、圖案化且蝕刻一光阻2075以用於在由閘極多晶矽層2025及下伏氧化物層2020及上覆氧化物層2030形成之閘極之間之區域中後續選擇性植入離子。
現在轉向圖37，對半導體裝置植入重摻雜N型區域2080。在一實施例中，使用(例如)砷將重摻雜N型區域2080摻雜至約1．1019個原子/cm-3至5．1020個原子/cm-3之一範圍中之一密度，且在10keV至100keV之一控制能量下進行植入。同時，類似地使用具有約1．1019至5．1020之一範圍中之一摻雜密度之砷對閘極多晶矽層2025進行N型摻雜，以獲得一合適位準的閘極導電率。在如圖38中圖解說明般剝除光阻2075之 後，於一烤箱中退火半導體裝置(例如，在700℃至1000℃之一溫度下持續1分鐘至60分鐘)以將重摻雜N型區域2080轉換為作用基板部位。
現在轉向圖39，在一後續步驟中塗佈、圖案化且蝕刻一光阻2085，以用於在N-LDMOS裝置之源極區域與汲極區域之間之選定區域中進行後續選擇性植入P型離子。如圖40中圖解說明，使用(例如)硼之離子植入形成重摻雜P型區域2090。在一實施例中，將重摻雜P型區域2090摻雜至約1．1019個原子/cm-3至5．1020個原子/cm-3之一密度，且在5keV至50keV之一控制能量下進行植入。在如圖41中圖解說明般剝除光阻2085之後，於一烤箱中退火半導體裝置(例如，在700℃至1000℃之一溫度下持續1分鐘至60分鐘)，以將重摻雜P型區域2090轉換為作用基板部位。重摻雜P型區域2090上之重摻雜N型區域2080相對較薄(例如，約10Å至100Å)。
現在轉向圖42，在(例如)具有氧氣及矽源氣體之一腔室中，於550℃至900℃下持續30分鐘至90分鐘，在半導體裝置之表面上形成一低溫二氧化矽(「SiO2」)層2095(一絕緣層)。為避免在表面上矽化N型區域，沈積低溫二氧化矽層2095且接著塗佈並處理光阻，以使用一自對準區塊(「SAB」，一自對準矽化物/自對準矽化物區塊)界定其中將形成矽化物的區域。矽化物僅形成於曝露矽上。在其中矽被一層SiO2覆蓋之區域中，將不會形成矽化物層。
現在轉向圖43，圖案化並蝕刻一光阻2100以使能夠在半導體裝置之選定區域上方形成矽化物區域(圖解說明用於後續處理之一閘極寬度2050的一半)。在如圖44中圖解說明般蝕刻低溫二氧化矽層2095之後，保留二氧化矽區域2105。亦如圖44中圖解說明般部分移除上覆閘極氧化物層2030。如圖45中圖解說明，在半導體裝置之表面上方塗佈一非反應性耐熔金屬2110。例示性耐熔金屬包含鎢、鈦及鈷。使用一低溫烘焙(例如，在400℃至550℃之一溫度下持續1分鐘至20分 鐘)，接著使用一高溫退火(例如，在600℃至800℃之一溫度下持續1分鐘至20分鐘)，在曝露矽及多晶矽表面上方形成矽化物(例如，具有較佳地在100埃(「Å」)至800Å之範圍中之一厚度)以減小矽化物薄片電阻。
現在轉向圖46，使用一濕式蝕刻來蝕刻非反應性耐熔金屬2110，保留矽化物層2115。矽化物層2115中形成於矽及多晶矽之曝露區域上方之部分實質上對濕式蝕刻不具有反應且不會被濕式蝕刻移除。一例示性濕式蝕刻係王水(氮酸與鹽酸之一混合物)。在一實施例中，上覆閘極多晶矽層2025之矽化物層2115電耦合至形成於一第一金屬層M1中之閘極金屬帶1130(如關於圖11及其他圖式論述)。
現在轉向圖47，採用一電漿沈積程序在半導體裝置之表面上方沈積一非晶矽氮氧化物(「SixOyNz」)層2120(一絕緣層)。採用一電漿沈積程序形成一非晶矽氮氧化物層2120在此項技術中廣為人知且將不會在本文進一步描述。如圖48中圖解說明，在氮氧化矽層2120上方沈積一光阻層2125。在一後續處理步驟中圖案化並蝕刻光阻層2125以曝露矽化物層2115之部分。
現在轉向圖49，使用諸如一反應性離子蝕刻(「RIE」)之一合適的蝕刻來蝕刻氮氧化矽層2120以曝露矽化物層2115之部分。如圖50中圖解說明，剝除光阻層2125之剩餘部分。接著如圖51中圖解說明般在半導體裝置之表面上方真空沈積一第一金屬(例如，鋁)層M1。
現在轉向圖52，在第一金屬層M1上方沈積一蝕刻停止耐熔層2130。在一實施例中，蝕刻停止耐熔層2130係氮化鈦、氮化鈷或氮化鎢。用於在一鋁層上方沈積一蝕刻停止耐熔層之一程序在此項技術中廣為人知且將不會在本文進一步描述。如圖53中圖解說明，在半導體裝置上方沈積一光阻層2135，接著圖案化並蝕刻光阻層2135以覆蓋第一金屬層M1中將被留存之區域。此後，如圖54中圖解說明般使用諸 如一RIE之一合適的蝕刻移除蝕刻停止耐熔層2130之曝露區域及第一金屬層M1之曝露區域。此外，剝除光阻層2135之剩餘部分，藉此如圖55中圖解說明般曝露蝕刻停止耐熔層2130及氮氧化矽層2120之剩餘部分。
現在轉向圖56，在半導體裝置上方沈積另一氮氧化矽層2140(一絕緣層)且藉由化學機械平坦化平坦化之。如圖57中圖解說明，在氮氧化矽層2140上方沈積且圖案化一光阻層2145以使能夠在一系列處理步驟中形成N-LDMOS之低電阻金屬源極及汲極接觸件。此後，如圖58中圖解說明般蝕刻氮氧化矽層2140下至蝕刻停止耐熔層2130。一例示性氮氧化矽蝕刻劑設備採用一感應耦合電漿蝕刻設備中之六氟乙烷(「C2F6」)氣體。
現在轉向圖59，剝除光阻層2145。此後，接著如圖60中圖解說明般在半導體裝置之表面上方真空沈積一第二金屬(例如，鋁)層M2。如圖61中圖解說明般在第二金屬層M2上方沈積一蝕刻停止耐熔層2150。在一實施例中，蝕刻停止耐熔層2150係氮化鈦、氮化鈷或氮化鎢。如圖62中圖解說明，在蝕刻停止耐熔層2150上方沈積並圖案化一光阻層2155以覆蓋第二金屬層M2中將被留存之區域。此後，如圖63中圖解說明般使用諸如一RIE之一合適的蝕刻移除蝕刻停止耐熔層2150之曝露區域及第二金屬層M2之曝露區域。此外，剝除光阻層2155之剩餘部分，藉此如圖64中圖解說明般曝露蝕刻停止耐熔層2150及氮氧化矽層2140之剩餘部分。
現在轉向圖65，在半導體裝置上方沈積另一氮氧化矽層2160(一絕緣層)且藉由化學機械平坦化平坦化之。如圖66中圖解說明，在氮氧化矽層2160上方沈積且圖案化一光阻層2165以覆蓋氮氧化矽層2160中待被留存之區域。圖67圖解說明在蝕刻氮氧化矽層2160下至蝕刻停止耐熔層2150之後的部分完成半導體裝置。此後，如圖68中圖解說明 般剝除光阻層2165。
現在轉向圖69，接著在半導體裝置之表面上方真空沈積一第三金屬(例如，鋁)層M3。如圖70中圖解說明，沈積並圖案化一光阻層2165以覆蓋第三金屬層M3中將被留存之區域。此後，如圖71中圖解說明般使用諸如一RIE之一合適的蝕刻移除第二金屬層M3之曝露區域。此外，剝除光阻層2165之剩餘部分，藉此如圖72中圖解說明般曝露第三金屬層M3及氮氧化矽層2160之剩餘部分。
現在轉向圖73，在半導體裝置上方沈積一最終氮氧化矽層2170(一絕緣層)且藉由化學機械平坦化來平坦化之。如圖74中圖解說明，在氮氧化矽層2170上方沈積且圖案化一光阻層2175以覆蓋將被留存之區域。此後，使用諸如一RIE之一合適的蝕刻移除氮氧化矽層2170之曝露區域，藉此如圖75中圖解說明般曝露第三金屬層M3之剩餘部分。此外，剝除光阻層2175之剩餘部分，藉此如圖76中圖解說明般曝露氮氧化矽層2170之剩餘部分。
現在轉向圖77，在半導體裝置上方沈積聚醯亞胺塗層2180(一絕緣層)。如圖78中圖解說明，在聚醯亞胺塗層2180上方沈積並圖案化一光阻層2185以覆蓋第三金屬層M3在N-LDMOS裝置之汲極上方之區域。此後，使用一合適的蝕刻移除聚醯亞胺塗層2180之曝露區域，藉此如圖79中圖解說明般曝露第三金屬層M3在N-LDMOS裝置之源極上之剩餘部分。此外，剝除光阻層2185之剩餘部分，藉此曝露聚醯亞胺塗層2180之剩餘部分。
現在轉向圖80，在半導體裝置上方沈積一耐熔障壁層2190(例如，氮化鈦、氮化鉭或氮化鈷)。接著如圖81中圖解說明般在耐熔障壁層2190上方沈積一薄金屬(例如，銅)晶種層2195。接著如圖82中圖解說明般電鍍銅晶種層2195以形成一電鍍銅層2200。此後，如圖83中圖解說明般在銅層2200上方沈積另一聚醯亞胺塗層2205(一絕緣層)。
現在轉向圖84，接著在聚醯亞胺塗層2205上方沈積並圖案化一光阻層2210。蝕刻光阻層2210且蝕刻下伏聚醯亞胺塗層2205以曝露N-LDMOS裝置之源極上方之下伏銅層2200。此後，在半導體裝置上方沈積另一薄金屬(例如，銅)晶種層2215。沈積銅晶種層2215係用以產生一全新表面以用於金屬(例如，銅)柱之後續電沈積之一選用步驟。此後，如圖86中圖解說明般自半導體裝置剝離光阻層2210(其中銅晶種層2215之部分上覆光阻層2210)。
現在轉向圖87，藉由採用一酸性溶液之一電鍍程序形成金屬(例如，銅)柱2220。如上文參考圖4圖解說明且描述，銅柱2200用作至一導電圖案化導線框之低電阻源極接觸件、完成半導體裝置之端子可焊接附著之跡線。可結合上文描述用於建構源極接觸件以形成N-LDMOS裝置之低電阻汲極接觸件之步驟採用對應步驟。此外，可選擇性地在銅柱2200與放置在銅柱2200上方之一圖案化導線框2230之間沈積一囊封劑(例如，一環氧樹脂)2225以產生用於一封裝半導體裝置之外部接觸件(例如(參見)圖18)。
現在轉向圖88，圖解說明一半導體裝置或其部分中具體實施之一P-LDMOS裝置之一實施例之一橫截面視圖。雖然將關於圖88介紹P-LDMOS裝置之一些層，但是亦將關於圖89描述該等層之一更詳細解釋。此外，因為建造包含P-LDMOS裝置之半導體裝置之許多處理步驟類似於建造包含上文陳述之N-LDMOS裝置之半導體裝置之處理步驟，所以下列論述將限於形成P-LDMOS裝置之層。
在包含一P摻雜半導體基板(亦稱為一「基板」)8005之一半導體晶粒中形成P-LDMOS裝置，且可在該基板之一表面上生長一選用磊晶層(例如，一輕摻雜P型磊晶層，未展示)。雖然在已圖解說明之實施例中基板8005係一P型基板，但是熟習此項技術者應瞭解，在不脫離本發明之範疇之情況下，基板8005可為一N型基板。
P-LDMOS裝置係由複數個P-LDMOS單元(諸如圖88中圖解說明之P-LDMOS單元8001)形成。P-LDMOS裝置包含上方形成有N型井8017之輕摻雜N型井8015。N型井8017內具有形成於其中之重摻雜N型區域8090。在重摻雜N型區域8090之任一側上或其上方形成重摻雜P型區域8060、8080。重摻雜P型區域8060經形成為尤其在遠離重摻雜P型區域8080之一橫向方向上具有低於重摻雜P型區域8080之一摻雜密度。重摻雜P型區域8060、8080透過形成於其等上方之矽化物層8115提供一歐姆接面。矽化物層8115在重摻雜P型區域8060、8080與一第一金屬(例如，鋁)層M1之間提供一強導電接面以最終對P-LDMOS裝置提供源極接觸件(指定為「接合源極(接觸件)」)。位於重摻雜N型區域8090上方之重摻雜P型區域8080較薄(例如，約10Å至100Å)使得藉此形成於重摻雜P型區域8080與重摻雜N型區域8090之間之所得P-N接面將實質上係在兩個方向上皆強導電之一歐姆接面。因此，形成於其等之間之P-N接面將不能用作二極體。類似地，矽化物層8115在重摻雜P型區域8080與第一金屬層M1之間提供一強導電接面以最終對P-LDMOS裝置提供汲極接觸件(指定為「接合汲極(接觸件)」)。源極及汲極之第一金屬層M1係藉由諸如非晶矽氮氧化物(「SixOyNz」)層8120之絕緣層分離。
在N型井8017內於重摻雜P型區域2060及重摻雜N型區域8090附近形成N型區域8055。在重摻雜P型區域8060與輕摻雜P型區域8070之間的閘極下方形成通道區域8003。N型區域8055係藉由在將形成於通道區域8003上之閘極下方以偏離垂直面之一角度進行離子注入而形成於N型井8017中，且用以控制P-LDMOS裝置之一臨限電壓。
該等閘極係經形成有閘極多晶矽層8025，閘極多晶矽層8025在周圍具有下伏閘極氧化物層8020及上覆閘極氧化物層8030以及側壁間隔件(其等之一者指定為8040)。通道區域8003上方之閘極多晶矽層 8025控制其中的導電率位準。下伏閘極氧化物層8020在閘極多晶矽層8025及N型井8017及N型區域8055之間形成一隔離層。移除上覆閘極氧化物層8030在閘極多晶矽層8025上方之一部分且在該部分上方形成矽化物層8115以減小閘極電阻。
因此，閘極多晶矽層8025(連同矽化物層8115)跨P-LDMOS裝置之許多P-LDMOS單元形成閘極多晶矽帶且耦合至第一金屬層M1中之閘極金屬帶1131(參見(例如)圖16)。閘極金屬帶1131佈線至位於半導體裝置之周邊處之複數個閘極驅動器(參見(例如)圖16)。藉由將第一金屬層M1中之閘極金屬帶1131(其等具有實質上大於閘極多晶矽帶之導電率)耦合至該複數個閘極驅動器而對該P-LDMOS單元之閘極啟用一實質上時間對準切換信號。
鑑於閘極及源極以及汲極之間產生之大量有效電容，將一時間對準切換信號提供給個別P-LDMOS單元之該複數個閘極係一項重要的設計考慮，該電容需要大量閘極驅動電流以達成一快速切換轉變。不能對個別P-LDMOS單元之閘極產生一時間對準閘極驅動信號會使得能夠在導通一些P-LDMOS單元之前導通其他P-LDMOS單元，這迫使早期切換的單元在時間上錯位切換轉變期間傳導大電流脈衝。時間上錯位大電流脈衝將P-LDMOS單元曝露於裝置故障。
已圖解說明之結構亦使得能夠使用一共同半導體晶粒中之實質上相同結構形成N-LDMOS及P-LDMOS裝置，且使能夠使用一低電感大電流路徑將各LDMOS類型耦合至一外部電路。各LDMOS經形成具有單個大的源極接觸件及單個大的且共用的汲極接觸件(參見(例如)圖17)，這可簡化一外部電路之電路板佈局及附著問題。大的源極及汲極接觸件容易覆疊具有實質上與大的源極及汲極接觸件(參見(例如)圖17B)相同之佔據面積之一銅再分佈層且最終覆疊一導線框(參見(例如)圖17D)，這進一步改良導電率並將一封裝半導體裝置(參見(例如)圖 18)耦合至一外部電路。源極接觸件及共用汲極接觸件上覆N-LDMOS及P-LDMOS裝置之實質上整個作用區域，使得未上覆作用切換區域之大電流接觸件浪費的晶粒區域較少。
關於P-LDMOS單元8001，源極(或源極區域)係具體實施於至少該重摻雜P型區域8060中，且汲極(或汲極區域)係具體實施於該輕摻雜P型區域8070(例如，一輕摻雜汲極(「LDD」)區域)及與通道區域8003相對之一相鄰重摻雜P型區域8080中。閘極駐留在具有如本文中介紹之層之通道區域8003上方。LDD區域對P-LDMOS裝置提供高於習知設計之一崩潰電壓。按「重摻雜源極區域」、「閘極」、「輕摻雜汲極區域」及「重摻雜汲極區域」的順序形成此等區域。
現在轉向圖89，圖解說明一半導體裝置或其部分中具體實施之一P-LDMOS裝置之一實施例之一橫截面視圖。在包含一P摻雜半導體基板(亦稱為一「基板」)8005之一半導體晶粒中形成P-LDMOS裝置，且可在該基板之一表面上生長一選用磊晶層(例如，一輕摻雜P型磊晶層，未展示)。基板8005較佳地輕P摻雜(例如，硼)介於1．1014個原子/cm3與1．1016個原子/cm3之間。尤其當基板8005係一輕摻雜P型基板時，不一定需要在基板8005上生長選用磊晶層。雖然在已圖解說明之實施例中基板8005係一P型基板，但是熟習此項技術者應瞭解，在不脫離本發明之範疇之情況下，基板8005可為一N型基板。
基板8005係形成具有隔離區域(例如，淺溝渠隔離區域8010)。淺溝渠隔離區域8010亦可形成於一基板內或生長在該基板上之一磊晶層內以在實施於該基板上或磊晶層上之裝置之間提供介電質隔離。淺溝渠隔離區域8010係藉由使用一光阻塗佈、圖案化及蝕刻基板8005以界定其中的各自區域而形成。一例示性光阻係一AZ電子材料光阻。接著蝕刻並使用諸如二氧化矽、氮化矽、其等之一組合或任何其他合適的介電質材料之一介電質回填淺溝渠隔離區域8010。接著，藉由諸如 一化學機械平坦化(「CMP」)磨薄程序之一磨薄程序平坦化基板8005之磊晶層及淺溝渠隔離區域8010以平坦化該裝置並同時限制對晶粒的表面破壞。遮罩、蝕刻、回填介電質及磨薄之步驟在此項技術中廣為人知且將不會在下文中予以進一步詳細描述。
P型基板8005藉由淺溝渠隔離區域8010分成介電質分離區域以在已圖解說明之實施例中容納複數個N-LDMOS及P-LDMOS裝置以及閘極驅動器及嵌入位於P型基板8005上之控制電路中用作低電壓裝置之其他PMOS及NMOS裝置。低電壓裝置可在(例如)一功率轉換器之一控制器內(例如，可形成於半導體裝置之一表面上之控制及信號處理裝置內)操作。此外，P型基板8005可容納用作(例如)一電力系統以及一功率轉換器(即，功率開關及驅動器開關)之一驅動器內之較高電壓裝置之N-LDMOS及P-LDMOS裝置。
藉由塗佈且圖案化一光阻遮罩(未展示)接著蝕刻光阻遮罩以界定待由輕摻雜N型井8015佔據之區域來形成輕摻雜N型井8015。一例示性光阻係AZ電子材料光阻。圖案化並蝕刻以界定輕摻雜N型井8015之水平尺寸之步驟在此項技術中廣為人知且將不會在下文予以進一步詳細描述。(例如，在約100keV至300keV之一控制能量下)藉由諸如砷之一適當N型摻雜劑物種之一離子植入程序形成輕摻雜N型井8015，且導致較佳地在約1．1014個原子/cm3至1．1016個原子/cm3之一範圍中之一輕摻雜濃度分佈。
藉由塗佈且圖案化一光阻遮罩(未展示)接著蝕刻遮罩以界定待由N型井8017佔據之區域來在輕摻雜N型井8015中形成N型井8017。(例如，在約100keV至300keV之一控制能量下)藉由諸如磷之一適當N型摻雜劑物種之一離子植入程序形成N型井8017，且導致較佳地在約1．1017個原子/cm3至2．1019個原子/cm3之一範圍中之一摻雜濃度分佈。
在符合閘極之所期待操作電壓之一厚度之半導體裝置之表面上 方形成一閘極氧化物層8020(一絕緣層)，在閘極氧化物層8020(一絕緣層)上形成閘極。閘極氧化物層8020通常係(例如)藉由以下操作形成之二氧化矽：在一烤箱中放置其上面形成矽裝置之晶圓；及對採用約0.25微米(「μm」)特徵大小且在低閘極電壓下(例如，2.5伏特)操作之裝置使晶圓之曝露表面與氧氣或具有約30埃(「Å」)至50Å之一厚度之其他合適的材料在500℃至900℃下發生反應持續10分鐘至100分鐘(諸如以產生一高κ(介電常數)堆疊)。假定N-LDMOS及P-LDMOS裝置之閘極-源極電壓限制限於(例如，約2.5伏特之)一電壓，則可使用如上文陳述之一閘極介電質層厚度形成閘極氧化物層8020。較佳地，閘極氧化物層8020經建構具有一均勻厚度以對該等裝置提供使該裝置之順向導電性質完全或幾乎完全飽和之大約2.5伏特之一閘極-源極額定電壓。當然，該等裝置之前述提及之閘極電壓範圍係僅為闡釋性目的而提供，且預期其他電壓範圍在本發明之廣泛範疇內。
該等閘極包含沈積在閘極氧化物層8020之一表面上方之一閘極多晶矽層8025且在一後續處理步驟中使用諸如具有約1．1019至5．1020之一範圍中之一摻雜密度之一適當摻雜物種(諸如砷)對閘極多晶矽層8025進行N型(或P型)摻雜以獲得一合適位準的導電率。在一烤箱中在一高溫下退火閘極多晶矽層8025(例如，在攝氏800度(「℃」)至攝氏1000℃之一溫度下持續2分鐘至60分鐘)以適當地擴散並活化摻雜劑。閘極多晶矽層8025可具有可自約100奈米至約500奈米之一厚度範圍，但是取決於一應用可具有更小或更大的厚度範圍。
閘極經形成具有一上覆閘極氧化物層8030(一絕緣層)，上覆閘極氧化物層8030係藉由以下操作在閘極多晶矽層8025之一上表面上方而形成：在一烤箱中放置其上面形成矽裝置之晶圓；及使閘極多晶矽層8025之曝露表面與氧氣在一高溫下發生反應(例如，在500℃至900℃之一溫度下持續1分鐘至60分鐘)。上覆閘極氧化物層8030可經形成具 有約50Å至500Å之一厚度。
圖案化並蝕刻閘極氧化物層8020、閘極多晶矽層8025及上覆閘極氧化物層8030以界定並形成其等之水平尺寸。搭配一蝕刻採用一光阻遮罩以界定閘極多晶矽層8025、閘極氧化物層8020及上覆閘極氧化物層8030之橫向尺寸。在圖89中僅使用參考數字指定閘極多晶矽層8025及閘極氧化物層8020、8030之閘極之一者。一例示性光阻係AZ電子材料光阻。圖案化並蝕刻以界定並形成閘極多晶矽層8025及閘極氧化物層8020、8030之水平尺寸之步驟在此項技術中廣為人知且將不會在下文予以進一步詳細描述。在一替代性實施例中，閘極多晶矽層8025可包含或以其他方式經形成具有多種材料，包含各種金屬、其他摻雜半導體或其他導電材料。應注意，可在相同處理步驟中遮罩並蝕刻閘極多晶矽層8025及閘極氧化物層8020、8030之水平尺寸以及形成於相同矽上之一N-LDMOS及P-LDMOS裝置二者之多種其他結構。此外，在一自對準程序中且無須遮罩及蝕刻一光阻而由與閘極多晶矽層8025及下伏氧化物層8020及上覆氧化物層8030相鄰之一絕緣層(諸如氮化矽)形成側壁間隔件(其等之一者指定為8040)。應注意，移除上覆閘極氧化物層8030在閘極多晶矽層8025上方之一部分(約一閘極寬度的一半，約為0.2μm)。
在N型井8017內離子植入(例如)砷而形成重摻雜N型區域8090。在一實施例中，將重摻雜N型區域8090摻雜至約1．1019個原子/cm-3至5．1020個原子/cm-3之一密度，且在5keV至50keV之一控制能量下進行植入。在重摻雜N型區域8090周圍的是經離子植入諸如磷之一合適的原子物種之N型區域8055以使已形成之P-LDMOS裝置達成一可用閘極臨限電壓。N型區域8055具有約5．1017個原子/cm3至1．1019個原子/cm3之範圍中之一摻雜濃度分佈且係在約20keV至100keV之一控制能量下進行植入。在N型區域8055上方的係具有P型離子(例如，硼)之重摻 雜P型區域8060。重摻雜P型區域8060經植入(例如，在約5keV至50keV之一控制能量下)具有較佳地在5．1018個原子/cm3至1．1020個原子/cm3之一範圍中之一摻雜濃度分佈以使已形成之P-LDMOS裝置達成一低源極電阻。
在重摻雜N型區域8090上方(及輕摻雜N型井8015內之其他位置內)的是使用(例如)硼摻雜至約1．1019個原子/cm-3至5．1020個原子/cm-3之一範圍密度且在10keV至100keV之一控制能量下經植入之重摻雜P型區域8080。重摻雜N型區域8090上方之重摻雜P型區域8080相對較薄(例如，約10Å至100Å)。又，類似地使用具有約1．1019至5．1020之一範圍中之一摻雜密度之硼對閘極多晶矽層8025進行P摻雜以獲得一合適的位準的閘極導電率。在重摻雜P型區域8080(位於輕摻雜N型井8015內)周圍的是使用(例如)硼摻雜至1．1017個原子/cm3至1．1019個原子/cm3且在10keV至200keV之一控制能量下經植入之輕摻雜P型區域8070。
在閘極及輕摻雜P型區域8070之部分上方的係二氧化矽區域8105(一絕緣區域)。矽化物僅形成於曝露矽上。在其中矽被二氧化矽區域8105覆蓋之區域中，將不會形成矽化物層。接著在矽之曝露區域上方形成矽化物層8115，且多晶矽實質上對濕式蝕刻不具有反應且不會被濕式蝕刻移除。一例示性濕式蝕刻係王水(氮酸與鹽酸之一混合物)。在一實施例中，上覆閘極多晶矽層8025之矽化物層8115電耦合至形成於一第一金屬層M1中之閘極金屬帶1131(參見(例如)圖16)。可使用諸如具有較佳地在100Å至800Å之範圍中之一厚度之耐熔金屬(諸如鎢、鈦及鈷)形成矽化物層8115。
在閘極及二氧化矽區域8105上方沈積並圖案化一非晶矽氮氧化物(「SixOyNz」)層8120(一絕緣層)。一第一金屬(例如，鋁)層M1(例如，經由一真空沈積)位於氮氧化矽區域8120之間下至矽化物層8115 在源極及汲極接觸件之一區域中之部分。在第一金屬層M1上方沈積一蝕刻停止耐熔層8130。在一實施例中，蝕刻停止耐熔層8130係氮化鈦、氮化鈷或氮化鎢。在氮氧化矽層8120上方沈積並圖案化另一氮氧化矽層8140(一絕緣層)。氮氧化矽層8120、8140使能夠在一系列處理步驟中形成P-LDMOS之低電阻金屬源極及汲極接觸件。一第二金屬(例如，鋁)層M2(例如，經由一真空沈積)位於氮氧化矽區域8140之間下至源極及汲極接觸件之一區域中之一第一金屬層M1上方之蝕刻停止耐熔層8130。在第二金屬層M2上方沈積一蝕刻停止耐熔層8150。在一實施例中，蝕刻停止耐熔層8150係氮化鈦、氮化鈷或氮化鎢。
在氮氧化矽層8140上方沈積並圖案化另一氮氧化矽層8160(一絕緣層)。氮氧化矽層8120、8140、8160使能夠在一系列處理步驟中形成P-LDMOS之低電阻金屬源極及汲極接觸件。一第三金屬(例如，鋁)層M3(例如，經由一真空沈積)位於氮氧化矽區域8160之間下至源極及汲極接觸件之一區域中之一第二金屬層M2上方之蝕刻停止耐熔層8150。在氮氧化矽層8160上方沈積並圖案化一最終氮氧化矽層8170(一絕緣層)。氮氧化矽層8120、8140、8160、8170使能夠在一系列處理步驟中形成P-LDMOS之低電阻金屬源極及汲極接觸件。在氮氧化矽層8170及第三金屬層M3上方沈積及圖案化一聚醯亞胺塗層8180(一絕緣層)。在半導體裝置上方沈積一耐熔障壁層8190(例如，氮化鈦、氮化鉭或氮化鈷)。
接著在耐熔障壁層8190上方沈積一薄金屬(例如，銅)晶種層，該晶種層接著被電鍍以形成一電鍍銅層8200。在由聚醯亞胺塗層8180界定之區域中之銅層8200上方沈積並圖案化另一聚醯亞胺塗層8205(一絕緣層)。在P-LDMOS裝置之源極之區域中之該另一聚醯亞胺塗層8205之間之電鍍銅層8200上方沈積並圖案化另一薄金屬(例如，銅)晶種層8215。沈積銅晶種層8215係用以產生一全新表面以用於金屬(例 如，銅)柱之後續電沈積之一選用步驟。
金屬(例如，銅)柱8220係藉由採用一酸性溶液之一電鍍程序形成且位於銅晶種層8215上方。如上文參考圖4圖解說明且描述，銅柱8220用作至一導電圖案化導線框之低電阻源極接觸件、完成半導體裝置之端子可焊接附著之跡線。可結合上文描述用於建構源極接觸件以形成P-LDMOS裝置之低電阻汲極接觸件之步驟採用對應步驟。此外，可選擇性地在銅柱8200與放置在銅柱8200上方之一圖案化導線框8230之間沈積一囊封劑(例如，一環氧樹脂)8225以產生用於一封裝半導體裝置之外部接觸件(例如(參見)圖18)。
下文在表格1中列出之步驟圖解說明可用以在一共同晶粒中形成N-LDMOS及P-LDMOS裝置之一系列程序步驟。在本發明之廣泛範疇內預期可修改程序步驟之特定順序以在一共同晶粒中產生N-LDMOS及P-LDMOS裝置。
在最左邊欄中對步驟進行編號。在向右的下一欄中，識別應用於N-LDMOS及P-LDMOS裝置二者之程序步驟。在第三欄及第四欄中，分別識別僅應用於LDMOS及P-LDMOS裝置之程序步驟。
熟習此項技術者應瞭解，一半導體開關及一功率轉換器及建構半導體開關及功率轉換器之相關方法之先前描述之實施例僅係為闡釋性目的而提出。此外，能夠採用其他開關模式功率轉換器拓撲生產一 半導體開關及一功率轉換器之其他實施例完全在本發明之廣泛範疇內。雖然已在包含用以控制一輸出特性以對一負載供電之一控制器之一功率轉換器之環境下描述半導體開關及功率轉換器之建構，但是半導體開關及功率轉換器之建構亦可應用於其他系統，諸如一功率放大器、一馬達控制器及根據一步進馬達或其他機電裝置控制一致動器之一系統。
為更加理解積體電路、半導體裝置及其製造方法，參見R.F.Pierret、Addison-Wesley(1996年)發表的「Semiconductor Device Fundamentals」及K.Wasa及S.Hayakawa發表在Noyes Publications(1992年)的「Handbook of Sputter Deposition Technology」。為加理解功率轉換器，參見美國紐約Van Nostrand Reinhold公司的Rudolph P.Severns及Gordon Bloom(1985年)發表的「Modern DC-to-DC Switchmode Power Converter Circuits」及J.G.Kassakian、M.F.Schlecht及G.C.Verghese、Addison-Wesley(1991年)發表的「Principles of Power Electronics」。前述提及之參考係以引用的方式全部併入本文。
又，雖然已詳細描述本發明及其優點，但是應瞭解可在不脫離如關於實施例之申請專利範圍定義之本發明之精神及範疇之情況下在本文中作出各種改變、替代及變更。例如，上文論述之許多程序可以不同方法論實施且由其他程序或其等之一組合取代。
此外，本申請案之範疇不旨在限於說明書中描述之程序、加工、製造、物質成分、方式、方法及步驟之特定實施例。根據本發明之揭示內容，一般技術者將容易明白可根據本發明利用當前存在或隨後發展之執行與本文中描述之對應實施例實質上相同功能或達成實質上相同結果之程序、加工、製造、物質成分、方式、方法及步驟。因此，對實施例之申請專利範圍旨在使此等程序、加工、製造、物質成 分、方式、方法及步驟包含在該等申請專利範圍之範疇內。
1905‧‧‧輕摻雜基板
1910‧‧‧井
1915‧‧‧絕緣層/氮氧化矽層
1920‧‧‧通孔
1925‧‧‧通孔
1930‧‧‧銅通孔
1935‧‧‧第一聚醯亞胺層
1940‧‧‧銅再分佈層
1945‧‧‧銅柱
1950‧‧‧第二聚醯亞胺層
1955‧‧‧銅導線框

Claims (15)

  1. 一種半導體裝置，其包括：一半導體晶粒，其係使用形成一橫向擴散金氧半導體(LDMOS)裝置之複數個LDMOS單元而形成；一再分佈層，其電耦合至該複數個LDMOS單元；及複數個金屬柱，其等分佈在該再分佈層上方且電耦合至該再分佈層。
  2. 如請求項1之半導體裝置，其進一步包括複數個閘極驅動器，該複數個閘極驅動器電耦合至該再分佈層且電耦合至該複數個LDMOS單元之閘極。
  3. 如請求項1之半導體裝置，其進一步包括一導電圖案化導線框，該導電圖案化導線框藉由該複數個金屬柱電耦合至該再分佈層。
  4. 如請求項3之半導體裝置，其中該半導體裝置裝填有一囊封劑。
  5. 如請求項4之半導體裝置，其中該導電圖案化導線框之部分經曝露以用作該半導體裝置之外部接觸件。
  6. 如請求項5之半導體裝置，其中該等外部接觸件之數者經組態以耦合至一印刷電路板。
  7. 如請求項6之半導體裝置，其中該等外部接觸件之數者經組態以耦合至該印刷電路板上之複數個去耦裝置。
  8. 如請求項6之半導體裝置，其中該等外部接觸件之數者經組態以透過該印刷電路板上之一相對表面上的通孔耦合至複數個去耦裝置。
  9. 如請求項5之半導體裝置，其中該等外部接觸件之數者經耦合至複數個閘極驅動器，該複數個閘極驅動器電耦合至該再分佈層 且電耦合至該複數個LDMOS單元之閘極，且該等外部接觸件之數者透過該再分佈層耦合至該複數個LDMOS單元之汲極或源極。
  10. 如請求項1之半導體裝置，其進一步包括形成於該再分佈層下方之一金屬層，該金屬層包含形成於該半導體晶粒之一基板上且平行於該LDMOS裝置之複數個源極及汲極區域之各自者並與該等各自者形成一電接觸件的複數個交替源極及汲極金屬帶。
  11. 一種形成一半導體裝置之方法，其包括：在一半導體晶粒中形成一橫向擴散金氧半導體(LDMOS)裝置之複數個LDMOS單元；將一再分佈層耦合至該複數個LDMOS單元；及在該再分佈層上方分佈複數個金屬柱，並將該複數個金屬柱耦合至該再分佈層。
  12. 如請求項11之方法，其進一步包括將複數個閘極驅動器耦合至該再分佈層且耦合至該複數個LDMOS單元之閘極。
  13. 如請求項11之方法，其進一步包括：藉由該複數個金屬柱將一導電圖案化導線框耦合至該再分佈層；及使用一囊封劑裝填該半導體裝置，其中該導電圖案化導線框之部分經曝露以用作該半導體裝置之外部接觸件。
  14. 如請求項13之方法，其中該等外部接觸件之數者耦合至複數個閘極驅動器，該複數個閘極驅動器耦合至該再分佈層且耦合至該複數個LDMOS單元之閘極，且該等外部接觸件之數者透過該再分佈層耦合至該複數個LDMOS單元之汲極或源極。
  15. 如請求項11之方法，其進一步包括在該再分佈層下方形成一金屬層，該金屬層包含形成於該半導體晶粒之一基板上且平行於該 LDMOS裝置之複數個源極及汲極區域之各自者並與該等各自者形成一電接觸件的複數個交替源極及汲極金屬帶。
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