CN102290351A - 半导体器件制造方法 - Google Patents
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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Abstract
本发明公开了一种半导体器件制造方法,包括:通过化学气相沉积,在半导体衬底上形成包含硅、氧及碳的绝缘膜;在形成所述绝缘膜后,对在350℃或低于350℃的温度下正在进行加热的所述绝缘膜进行UV固化;以及在所述UV固化后,对所述绝缘膜进行氦等离子体处理。本发明提供的方法,可以使得层间绝缘膜具有高硬度,而不会引起膜应力的大幅提高。
Description
技术领域
本发明所讨论的实施例涉及一种半导体器件制造方法。
背景技术
近来,半导体器件的信号频率变得越来越高,这使得使用低介电常数(low-k)材料作为层间绝缘膜的材料变得尤为重要。
例如,用SiOC膜作为具有低介电常数的绝缘膜。在SiOC膜中形成许多孔隙(void),这些孔隙实现了相对低的相对介电常数。
例如,通过CVD(化学气相沉积)形成SiOC膜。
简单地通过CVD形成的SiOC膜没有足够的强度,而且也没有足够低的相对介电常数。为了提高强度和减小相对介电常数,对SiOC层间绝缘膜进行UV固化。
相关参考如下:
日本特许专利公开号2005-175085。
发明内容
为了克服现有技术中存在的问题,根据本实施例的一个方案,本发明提供了一种半导体器件制造方法,包括:通过化学气相沉积,在半导体衬底上形成包含硅、氧及碳的绝缘膜;在形成所述绝缘膜后,对在350℃或低于350℃的温度下正在进行加热的所述绝缘膜进行UV固化;以及在所述UV固化后,对所述绝缘膜进行氦等离子体处理。
本发明提供的半导体器件制造方法,可以使得层间绝缘膜具有高硬度,而不会引起膜应力的大幅提高。
实施例的目的和优点将通过在权利要求中具体给出的元件和组合来实现和得到。
应当理解,前面的大致描述和下面的具体描述均是示例性和说明性的,而不是用来限定权利要求所要求保护的实施方案。
附图说明
图1A到图11是根据一实施例的半导体器件制造方法步骤中的半导体器件剖视图,用以说明该方法;
图12A是示出在400℃的衬底温度下进行UV固化时相对介电常数的图;
图12B是示出在400℃的衬底温度下进行UV固化时杨氏模量的图;
图12C是示出在400℃的衬底温度下进行UV固化时膜应力的图;
图13A是示出相对介电常数的比较结果的图;
图13B是示出杨氏模量的比较结果的图;
图13C是示出膜应力的比较结果的图;
图14A是示出UV固化中相对介电常数与衬底温度之间关系的图;
图14B是示出UV固化中杨氏模量与衬底温度之间关系的图;
图14C是示出UV固化中膜应力与衬底温度之间关系的图。
具体实施方式
当简单地进行UV固化时,层间绝缘膜的膜应力增大很多,膜很容易脱落。不能总是制造出足够高可靠性的半导体器件。
例如,对SiOC层间绝缘膜进行UV固化,并在400℃下加热该层间绝缘膜,从而可以充分地提高该层间绝缘膜的强度,而且也可以充分地减小该层间绝缘膜的相对介电常数。也就是说,在400℃下的UV固化充分地加强了在该层间绝缘膜中的结合(bond),而且使该层间绝缘膜可以具有足够的强度。在400℃下的UV固化从层间绝缘膜向层间绝缘膜的外部释放出诸如硅羟基(Si-OH)(silanol groups)等多余的物质,层间绝缘膜可以具有足够低的相对介电常数。
然而,当进行UV固化并在400℃下加热层间绝缘膜时,该层间绝缘膜的膜应力变得很大。产生如此大的应力是由于层间绝缘膜中的结合在400℃下被加强后,层间绝缘膜被冷却,并且层间绝缘膜和其他构成元件的热膨胀系数不同。
当UV固化的加热温度降低时,层间绝缘膜的膜应力相应地降低。然而,UV固化的加热温度降低,诸如硅羟基等多余的物质不能容易地从层间绝缘膜中移除,相对介电常数就不能充分地降低。
本申请的发明人进行了认真的研究,得到了如后面所描述的观点:在UV固化后进行He(氦)等离子体处理,这样,即使当UV固化的加热温度设置得相对低时,层间绝缘膜的相对介电常数也可以充分降低。
参考附图,对本发明的优选实施例进行说明。
【a】一实施例
参考图1A到图14描述根据一实施例的半导体器件。图1A到图11是根据本实施例的半导体器件制造方法步骤中的半导体器件剖视图,用以说明该方法。
首先,在半导体衬底10上形成器件隔离区12,例如,通过STI(浅沟槽隔离)(参见图1A)。半导体器件10例如是N型或P型硅衬底。例如,用二氧化硅膜作为隔离区12的材料。该半导体衬底10可以是SOI(绝缘体上的半导体)衬底。可以通过LOCOS(区域性硅片氧化)形成器件隔离区12。这样,通过器件隔离区12界定出了器件区14。
接着,在整个表面上形成光致抗蚀剂膜(未示出),例如,通过旋转涂覆方法。
接着,通过光刻,形成用于露出NMOS晶体管待形成区2的开口(未示出)。
接着,例如,通过离子注入,以光致抗蚀剂膜作为掩模,将P型掺杂杂质注入半导体衬底10中,从而形成P型阱16。该P型掺杂杂质例如是B(硼)。
接着,移除光致抗蚀剂膜,例如,通过灰化。
在未示出的PMOS晶体管待形成区中形成N型阱(未示出),在该N型阱中,在后续的步骤中形成PMOS晶体管(未示出)。在本实施例中,将主要描述NMOS晶体管待形成区2,关于PMOS晶体管待形成区的描述将省略。
接着,在半导体衬底10的表面上形成膜厚例如是1.5nm的二氧化硅膜的栅绝缘膜18,例如,通过干热氧化。
接下来,在整个表面上形成膜厚例如是100nm的多晶硅膜,例如,通过CVD(化学气相沉积)。
接着,在整个表面上形成光致抗蚀剂膜(未示出),例如,通过旋转涂覆。
接下来,通过光刻,在光致抗蚀剂膜中形成用于露出NMOS晶体管待形成区2的开口(未示出)。
接下来,例如,通过离子注入,以光致抗蚀剂膜作为掩模,将N型掺杂杂质注入多晶硅膜中。该N型掺杂杂质例如是磷。这样,NMOS晶体管待形成区2中的多晶硅膜变成N型类型。
此后,移除光致抗蚀剂膜,例如,通过灰化。
接下来,执行用于活化掺杂杂质的热处理,例如,通过RTA(快速热退火)。
接着,通过光刻,使多晶硅膜图案化,从而形成多晶硅栅极20(参见图1B)。栅长度例如是约32nm。
接下来,在整个表面上形成光致抗蚀剂膜(未示出),例如,通过旋转涂覆。
接着,通过光刻,在光致抗蚀剂膜中形成用于露出NMOS晶体管待形成区2的开口。
接下来,例如,通过离子注入,以光致抗蚀剂膜和栅极20作为掩模,将N型掺杂杂质注入,从而在半导体衬底10中栅极20的两侧形成N型扩展区22(参见图1C)。该N型掺杂杂质例如是磷或砷。加速能量例如是约7keV。剂量例如是约7.0×1014cm-2。
此后,移除光致抗蚀剂膜,例如,通过灰化。
接下来,在整个表面上形成膜厚例如是8nm的二氧化硅膜,例如,通过CVD。
接着,各向异性地(anisotropically)蚀刻二氧化硅膜以在栅极20的侧壁上形成二氧化硅膜的侧壁绝缘膜24(参见图1D)。
接下来,在整个表面上形成光致抗蚀剂膜(未示出),例如,通过旋转涂覆。
接着,通过光刻,形成用于露出NMOS晶体管待形成区2的开口(未示出)。
接下来,以形成有侧壁绝缘膜24的栅极20和光致抗蚀剂膜作为掩摸,将N型掺杂杂质注入半导体衬底10中。该N型掺杂杂质例如是砷(As)。加速能量例如是约12keV。剂量例如是约2.0×1015cm-2。这样,用于形成扩展源/漏极结构的深区的N型杂质区26就形成了(参见图2A)。
此后,移除光致抗蚀剂膜,例如,通过灰化。
接着,执行用于活化掺杂杂质的热处理,例如,通过RTA(快速热退火)。这样,扩展区22和杂质区26就形成了扩展源/漏极结构的源/漏极扩散层28(参见图2A)。
接下来,在整个表面上形成膜厚例如是约20nm的高熔点(refractory)金属膜,例如,通过溅射。该高熔点金属膜例如是镍膜。
接着,通过热处理,栅极20表面的硅和高熔点金属膜内的镍互相反应的同时,半导体衬底10表面的硅和高熔点金属膜内的镍互相反应。
接下来,蚀刻掉那些未反应的高熔点金属膜。这样,在源/漏极区扩散层28上和栅极20上分别形成硅化镍的硅化物膜30(参见图2B)。在源/漏极扩散层28上的硅化物膜30起到了源/漏极的作用。
这样,形成了包括栅极20和源/漏极扩散层28的晶体管(NMOS晶体管)32。
接下来,在整个表面上形成膜厚例如是600nm的PSG(磷硅玻璃)膜的层间绝缘膜34,例如,通过CVD(参见图2C)。
接着,将层间绝缘膜34的表面平坦化,例如,通过CMP(化学机械研磨)。
接下来,通过光刻,在层间绝缘膜34内形成向下直到源/漏极30的接触孔36。
接着,在整个表面上顺序形成膜厚例如是7nm的Ti膜及膜厚例如是2nm的TiN膜,例如,通过溅射。这样,就形成了Ti膜和TiN膜的基底金属膜(粘附膜,阻挡金属膜)38。
接着,在整个表面上形成例如是钨的导电膜40,例如,通过CVD。该导电膜40的膜厚设置为使得导电膜40充分地填充接触孔36。
接着,例如,通过CMP,抛光钨膜40及基底金属膜38直到暴露出层间绝缘膜34的表面。这样,例如是钨的导体塞40被埋入了接触孔36内(参见图2C)。
接下来,在整个表面上形成膜厚例如是50到200nm的层间绝缘膜42,例如,通过等离子体CVD(参见图3A)。该层间绝缘膜42是由低介电常数(low-k)材料形成的。具体地说,形成包括硅、氧及碳的膜作为层间绝缘膜42。更具体地说,形成SiOC膜作为层间绝缘膜42。下面举例说明层间绝缘膜42的形成。提供到膜形成室内的气体例如是TMSA(Trimethylsilylacetylene,三甲基硅乙炔)气体、O2气及CO2气体。TMSA气体的流量设置在例如约3sccm。O2气的流量设置例如约200sccm。CO2气体的流量设置在例如约5000sccm。膜形成室内的压强设置在例如约10mTorr。衬底温度设置在例如约400℃。这样,就形成了层间绝缘膜42。
接着,将UV(紫外线)应用到正在进行加热的层间绝缘膜42从而进行UV固化(紫外线固化,紫外线处理)(参见图3B)。对于UV固化而言,可以使用UV退火系统或其他系统。例如,通过将半导体衬底10装入UV退火系统的反应室,用UV灯或其他设备,将UV应用到正在进行加热的半导体衬底10,来进行UV固化。UV灯的波长范围设置在例如约200到500nm。UV灯的输出设置在例如约1800W。反应室内的压强设置在例如约50Torr。提供到反应室内的气体设置为例如是He气。He气的流量设置在例如约7500sccm。在应用UV中的加热温度(即衬底温度)设置在350℃或低于350℃。衬底温度优选为230-350℃的范围。这里的衬底温度例如是230℃。UV辐射时间设置在例如约5分钟。在相对低的温度进行UV固化可以提高层间绝缘膜42a的杨氏模量而不会引起膜应力的大幅提高。也就是说,可以固化层间绝缘膜42a而不引起膜应力的大幅提高。通过这种UV固化,层间绝缘膜42a的相对介电常数不能被充分地降低,因为UV固化是在相对高的温度进行的。在UV固化已经完成的阶段,层间绝缘膜42a的相对介电常数是相对高的。
在UV固化已经完成的阶段层间绝缘膜42a的相对介电常数相对高的原因如下。即,在SiOC层间绝缘膜42a中,包含诸如硅羟基等多余的物质。硅羟基离开层间绝缘膜42a的解吸附(desorption)温度将约为400℃或高于400℃。因此,当在350℃或低于350℃的温度下进行UV固化时,硅羟基保留在层间绝缘膜42a中。这样,当在低于350℃的温度下完成UV固化时,层间绝缘膜42a的相对介电常数将会是相对高的。
衬底温度设置在350℃或低于350℃的原因如下。即,当在相对高的温度进行UV固化时,在层间绝缘膜42中产生大的应力。为了固化该层间绝缘膜42而不产生大的膜应力,优选地,在相对低的温度进行UV固化。在350℃或低于350℃的温度下进行UV固化,可以固化层间绝缘膜42同时防止大的膜应力产生。因此,在本实施例中,衬底温度设置在350℃或低于350℃。
另一方面,当在相对低的温度进行UV固化时,层间绝缘膜42不能被充分地固化。因此,优选地,用于UV固化的衬底温度不能太低。在230℃或高于230℃的温度下进行UV固化,可以充分地固化层间绝缘膜42。因此,优选地,UV固化中的衬底温度设置在230℃或高于230℃。
即使当用于UV固化的衬底温度设置在230℃或低于230℃时,层间绝缘膜42在一定程度上也可以被固化。因此,用于UV固化的衬底温度实质上可以不设置在230℃或高于230℃。就获得足够的强度而言,优选地,用于UV固化的衬底温度不能过低。
接下来,将氦(He)等离子体应用到正在进行加热的层间绝缘膜42a。这样,进行He等离子体处理(He等离子体固化)(参见图4A)。例如,对于He等离子体处理,可以使用等离子体处理系统(诸如等离子体CVD系统或其他设备)。例如,可以通过将半导体衬底10装入等离子体处理系统的反应室内,并将He等离子体应用到正在进行加热的半导体衬底10,来进行He等离子体处理。提供到反应室内的He气的流量设置在例如约9000sccm。反应室内的压强设置在例如约8Torr。等离子体的输出设置在例如约200W。He等离子体处理中的加热温度(即衬底温度)设置在100℃-350℃的范围。这里的衬底温度设置在例如是350℃。He等离子体应用时间设置在例如约15秒。
使用He的等离子体处理产生硅羟基等离开层间绝缘膜42a的解吸附效果,其中,He是惰性(inactive)小原子。此外,通过He等离子体处理,即使在约350℃的相对低的温度,硅羟基也可以从层间绝缘膜42a脱离出来。
这样,He等离子体处理可以充分地减小层间绝缘膜42b的相对介电常数。在相对低的温度进行的He等离子体处理,不会大幅提高层间绝缘膜42b的膜应力。也就是说,这样进行He等离子体处理,可以充分地降低层间绝缘膜42b的相对介电常数,而不会引起膜应力的大幅提高。He等离子体处理不会实质上改变层间绝缘膜42b的杨氏模量。
衬底温度设置在100-350℃范围的原因如下。即,当在相对高的温度进行He等离子体处理时,在层间绝缘膜42a中产生大的膜应力。为了固化该层间绝缘膜42a而不产生大的膜应力,优选地,在相对低的温度进行He等离子体处理。在350℃或低于350℃的温度下进行He等离子体处理,可以固化层间绝缘膜同时防止在层间绝缘膜中产生大的膜应力。因此,在本实施例中,衬底温度设置在350℃或低于350℃。另一方面,在相对低的温度进行He等离子体处理,不能充分地降低层间绝缘膜42a的相对介电常数。因此,优选地,在He等离子体处理中的衬底温度不能太低。在100℃或高于100℃的温度下进行He等离子体处理,可以充分地减小层间绝缘膜42a的相对介电常数。这样,在本实施例中,在He等离子体处理中的衬底温度设置在100-350℃的范围。
即使当用于He等离子体处理的衬底温度设置在100℃或低于100℃时,层间绝缘膜42的相对介电常数在一定程度上也可以被降低。因此,在He等离子体处理中的衬底温度实质上可以不是100℃或高于100℃。就获得足够低的相对介电常数而言,优选地,在He等离子体处理中的衬底温度不能过低。
如上所述,根据本实施例,在相对低的温度下对层间绝缘膜42进行UV固化,从而可以获得高硬度的层间绝缘膜42a,而不会引起膜应力的大幅提高。因为在UV固化中的温度是相对低的,在当UV固化完成的阶段,层间绝缘膜42的相对介电常数不能变得足够低。因此,在本实施例中,进行He等离子体处理,从而充分地降低层间绝缘膜42a的相对介电常数。即使是相对低的温度的UV固化也可以充分地提高层间绝缘膜的硬度。即使是相对低的温度的He等离子体处理也可以充分地降低层间绝缘膜的相对介电常数。这样,根据本实施例,在没有大幅提高膜应力的情况下可以形成高硬度并具有足够低相对介电常数的层间绝缘膜42b。
这样进行UV固化和He等离子体处理,可以使层间绝缘膜42b具有例如是55Mpa或低于55Mpa的膜应力,例如是2.7或低于2.7的相对介电常数以及例如是8GPa或高于8GPa的杨氏模量。
接着,在整个表面上形成膜厚例如是15到60nm的覆盖膜(cap film)44,例如,通过等离子体CVD(参见图4B)。例如,可以使用碳化硅(SiC)膜、硅碳氮(SiCN)膜、BN膜或其他膜作为覆盖膜44。
接下来,在整个表面上形成光致抗蚀剂膜46,例如,通过旋转涂覆。
接下来,通过光刻,在光致抗蚀剂膜46中形成开口48。该开口48用于形成沟槽50,该沟槽50用于将互连线54埋入层间绝缘膜42和覆盖膜44内。
接着,例如,通过等离子体蚀刻,以光致抗蚀剂膜46作为掩模,各向异性地蚀刻覆盖膜44和层间绝缘膜42。例如,使用含氟气体(fluorine contentgas)作为蚀刻气体。这样,在层间绝缘膜42和覆盖膜44内形成用于将互连线54埋入的沟槽50。在该沟槽50的底部,暴露出了导体塞40的顶部。
此后,移除光致抗蚀剂膜46,例如,通过灰化(参见图5A)。例如,使用氧气作为用于灰化的反应气体。
接下来,在整个表面上形成膜厚例如是15nm的阻挡金属膜52,例如,通过溅射。例如,使用钽膜作为该阻挡金属膜52。阻挡金属膜52用于阻止互连线54(参见图6A)内的Cu(铜)扩散到层间绝缘膜42中等。
接下来,在整个表面上形成膜厚例如是30nm的籽晶层(未示出),例如,通过溅射。例如,使用Cu作为该籽晶层的材料。
接下来,形成Cu层54,例如,通过电镀(参见图5B)。该Cu层54的厚度设置为使得Cu层54充分地填充沟槽50。
接下来,例如,通过CMP,抛光Cu层54和阻挡金属膜52,直到暴露出覆盖膜44的表面。这样,Cu互连线54被埋入沟槽50内(参见图6A)。
例如,这里使用Cu作为互连线54的材料,但不仅限于Cu。例如,也可以使用Cu合金或其他材料作为互连线54的材料。
接下来,在整个表面上形成膜厚例如是15到60nm的蚀刻停止膜56,例如,通过等离子体增强CVD。例如,可以使用SiC膜、SiCN膜、BN膜或其他膜作为蚀刻停止膜56。
接着,在整个表面上形成膜厚例如是150到250nm的层间绝缘膜58,例如,通过CVD(参见图6B)。形成具有低介电常数材料的层间绝缘膜作为层间绝缘膜58。具体地说,例如,形成包含硅、氧及碳的膜作为层间绝缘膜58。更具体地说,形成SiOC膜作为层间绝缘膜58。可以用与如上参考图3A描述的用于形成层间绝缘膜42的处理同样的方法,形成层间绝缘膜58。也就是说,提供到膜形成室内的气体例如是TMSA气体、O2气及CO2气体。TMSA气体的流量设置在例如约3sccm。O2气的流量设置在例如约200sccm。CO2气体的流量设置在例如约5000sccm。膜形成室内的压强设置在例如是约10mTorr。衬底温度设置在例如是400℃。
接着,将UV应用到正在进行加热的层间绝缘膜58,从而进行UV固化(参见图7A)。可以用与如上参考图3B描述的在层间绝缘膜42上进行UV固化同样的方法,对层间绝缘膜58进行UV固化。然而,由于层间绝缘膜58比层间绝缘膜42厚,可以将UV固化时间设置得更长,将UV灯的功率设置得更高,以便可以对层间绝缘膜58充分地进行UV固化。可以像层间绝缘膜42那样,使用例如UV退火系统进行用于层间绝缘膜58的UV固化。UV灯的主波长范围设置在例如约200到500nm。UV灯的输出设置在例如约1800W。反应室内的压强设置在例如约50Torr。提供到反应室内的气体设置为例如He气体。He气的流量设置在例如约7500sccm。在UV应用中的加热温度(即衬底温度)设置在350℃或低于350℃。优选地,衬底温度设置在230-350℃的范围。这里的衬底温度设置在例如230℃。UV应用时间设置在例如约180秒。相对低的温度的UV固化可以提高层间绝缘膜58a的杨氏模量而不会引起膜应力的大幅提高。也就是说,在不引起膜应力的大幅提高的情况下也可以固化层间绝缘膜58a。在UV固化已经完成的阶段,层间绝缘膜58a的相对介电常数是相对高的。
接着,将He等离子体应用到正在进行加热的层间绝缘膜58a,从而进行He等离子体处理(He等离子体固化)(参见图7B)。可以用与如上所述在层间绝缘膜42a上进行的He等离子体处理同样的方法,对层间绝缘膜58进行He等离子体处理。然而,由于层间绝缘膜58a比层间绝缘膜42a厚,可以将处理时间设置得更长,将等离子体的输出设置得更高,以便可以对层间绝缘膜58a充分地进行He等离子体处理。可以使用像用于层间绝缘膜42a的He等离子体处理一样的等离子体处理系统(例如等离子体CVD系统或其他系统),对层间绝缘膜58a进行He等离子体处理。提供到反应室内的He气的流量设置在例如约9000sccm。反应室内的压强设置在例如约8Torr。等离子体的输出设置在例如约200W。He等离子体处理中的加热温度(即衬底温度)设置在100-350℃的范围。这里的衬底温度设置在例如350℃。He等离子体应用时间设置在例如约30秒。He等离子体处理可以充分地降低层间绝缘膜58b的相对介电常数。在相对低的温度进行的He等离子体处理不会引起层间绝缘膜58b的膜应力的大幅提高。也就是说,这样进行的He等离子体处理,可以充分地降低层间绝缘膜58b的相对介电常数,而不会引起膜应力的大幅提高。He等离子体处理不会实质上改变层间绝缘膜58b的杨氏模量。
如上所述,根据本实施例,以相对低的温度对层间绝缘膜58进行UV固化,可使层间绝缘膜58a具有高硬度,而不会引起膜应力的大幅提高。因为用于UV固化的温度相对低,层间绝缘膜58a的相对介电常数在UV固化已经完成的阶段还没有变得足够低。接下来,对层间绝缘膜58a进行He等离子体处理,从而可以充分地降低层间绝缘膜58b的相对介电常数。UV固化和He等离子体处理都是在相对低的温度进行的,从而使层间绝缘膜58b可以具有高硬度和足够低的相对介电常数,而不会引起膜应力的大幅提高。
这样进行的UV固化和He等离子体处理,可以形成膜应力例如是55MPa或低于55MPa、相对介电常数例如是2.7或低于2.7、以及杨氏模量例如是8GPa或高于8GPa的层间绝缘膜58b。
接着,在整个表面上形成膜厚例如是15到60nm的覆盖膜60,例如,通过等离子体增强CVD(参见图8A)。例如,可以使用SiC膜、SiCN膜、BN膜或其他膜作为覆盖膜60。
接下来,在整个表面上形成光致抗蚀剂膜62,例如,通过旋转涂覆。
接下来,通过光刻,在光致抗蚀剂膜62中形成开口64。该开口64用于在层间绝缘膜58中形成接触孔66等(参见图8B)。
接着,例如,通过等离子体蚀刻,以光致抗蚀剂膜62作为掩模,蚀刻覆盖膜60和层间绝缘膜58,从而形成接触孔66。例如,使用包含CF4的气体作为蚀刻气体。
此后,移除光致抗蚀剂膜62,例如,通过氧等离子体。
这样,在覆盖膜60和层间绝缘膜58中形成了接触孔66(参见图8B)。
接下来,例如,通过旋转涂覆,将热固性树脂应用在整个表面上,从而形成树脂膜68(参见图9A)。这样,在接触孔66中和覆盖膜60上形成了树脂膜68。
接下来,进行热处理以固化树脂膜68。热处理温度设置在例如约250℃。热处理时间设置在例如约60秒。
接下来,在整个表面上形成光致抗蚀剂膜70,例如,通过旋转涂覆。
接下来,通过光刻,在光致抗蚀剂膜70中形成开口72。该开口72用于在层间绝缘膜58中形成沟槽74等。
接下来,例如,通过等离子体蚀刻,以光致抗蚀剂膜70作为掩模,蚀刻覆盖膜60和层间绝缘膜58,从而在层间绝缘膜58和覆盖膜60中形成沟槽74。沟槽74的深度设置在例如约100nm。例如,使用氟类气体(fluorine-based gas)作为蚀刻气体。在这个阶段,由树脂膜68保护的蚀刻停止膜56不被蚀刻。
接下来,移除光致抗蚀剂膜70和树脂膜68,例如,通过氧等离子体(参见图9B)。
接下来,通过等离子体蚀刻,蚀刻在接触孔66中暴露出的光致抗蚀剂膜56(参见图10A)。例如,使用包含CH2F2气体和O2气的混合气体作为蚀刻气体。这样,接触孔66到达互连线54的上表面。通过这次蚀刻,覆盖膜60的顶部被蚀刻,并且沟槽74变得更深。
接着,在整个表面上形成膜厚例如是15nm的阻挡金属膜76,例如,通过溅射(参见图10B)。例如,使用钽膜作为阻挡金属膜76。阻挡金属膜76用于阻止Cu层78内的Cu扩散到层间绝缘膜58中等。
接下来,在整个表面上形成膜厚例如是30nm的籽晶层(未示出),例如,通过溅射。例如,使用Cu作为籽晶层的材料。
接下来,形成Cu层78,例如,通过电镀。该Cu层78的厚度设置为使得Cu层78充分地填充接触孔66和沟槽74。
接着,例如,通过CMP,抛光Cu层78和阻挡金属膜76,直到暴露出覆盖膜60的表面。这样,Cu膜78被填充在沟槽74和接触孔66中。Cu层78埋入接触孔66中的部分变成导体塞78a。Cu层78埋入沟槽74中的部分变成互连线78b。这样,通过双镶嵌(dual damascening),导体塞78a和互连线78b形成为整体(参见图11)。
这里的互连线78b和导体塞78a的材料是Cu,但实质上不仅限于Cu。例如,可以使用Cu合金或其他材料作为互连线78b和导体塞78a的材料。
这样,就制造出了本实施例的半导体器件。
【评测结果】
接下来,参考图12A到图14C,介绍根据本实施例的半导体器件制造方法的评测结果。
图12A到图12C示出比较例1的评测结果,也就是说,给出了在400℃下对SiOC层间绝缘膜进行UV固化时的相对介电常数、杨氏模量及膜应力的图。图12A是层间绝缘膜的UV应用时间和相对介电常数之间的关系图。图12B是层间绝缘膜的UV应用时间和杨氏模量之间的关系图。图12C是层间绝缘膜的UV应用时间和膜应力之间的关系图。
用于形成SiOC层间绝缘膜的膜形成条件如下。即,使用诺发系统有限公司(Novellus System,Inc.)的VECTOR(R)作为用于形成层间绝缘膜的CVD系统。使用硅衬底作为衬底。使用TMSA气体、O2气及CO2气体作为提供到反应室内的气体。TMSA气体的流量设置在2sccm。O2气的流量设置在300sccm。CO2气体的流量设置在4000sccm。反应室内的压强设置在5.5Torr。应用的高频功率设置在1900W。应用的低频功率设置在300W。
用于SiOC层间绝缘膜的UV固化的条件如下。即,用在UV固化中的系统是诺发系统有限公司的SOLA(R)。使用主波长区域是200-500nm的UV灯作为UV灯。UV灯的输出设置在1800W。反应室内的压强设置在50Torr。使用He气体作为提供入反应室内的气体。He气的流量设置在7500sccm。衬底温度设置在如上所述的400℃。
如图12A所示,随着UV固化时间变长,层间绝缘膜的相对介电常数提高。
如图12B所示,随着UV固化时间变长,层间绝缘膜的杨氏模量提高。
如图12A和图12B所示,当进行约5分钟的UV固化时,将会获得相对小的相对介电常数,并将会获得相对高的杨氏模量。
然而,如图12C所示,约5分钟的UV固化使得膜应力相对大。
基于此,在比较例1中可以看出,即,当在400℃的衬底温度下进行UV固化时,膜应力变得相对大。
图13A到图13C是相对介电常数、杨氏模量及膜应力的比较结果的图。图13A是层间绝缘膜的收缩系数及其相对介电常数之间的关系图。图13B是层间绝缘膜的收缩系数及其杨氏模量之间的关系图。图13C是层间绝缘膜的收缩系数及其膜应力之间的关系图。带◆标记的图表明比较例2的结果,即,在400℃的衬底温度下进行UV固化的情况。带■标记的图表明比较例3的结果,即在230℃的衬底温度下进行UV固化的情况。带△标记的图表明实例1的结果,即在230℃的衬底温度下进行UV固化然后接着进行He等离子体处理的情况。
在所有情况中,可以用图12中所示的与比较例1中相同的方法形成SiOC层间绝缘膜。
在所有情况中,可以用图12所示的与比较例1中相同的方法对SiOC层间绝缘膜进行UV固化。然而,在比较例2中,UV固化中的衬底温度设置在400℃。在比较例3和实例1中,用于UV固化的衬底温度设置在250℃。
在实例1中,进行的He等离子体处理如下。即,He气的流量设置在9000sccm。反应室内的压强设置在8Torr。等离子体的输出设置在200W。衬底温度设置在350℃。He等离子体应用时间设置在15秒。
随着UV固化中衬底温度改变,发生在层间绝缘膜中的反应速率大大改变,因此不容易比较图表中的层间绝缘膜的特性与呈现在水平轴上的UV应用时间的特性。接着,在图13中,层间绝缘膜的收缩系数呈现在水平轴上。
如图13B所示,在实例1中,可以像比较例2那样获得相对高的杨氏模量。基于此,即使当UV固化中的衬底温度是相对低的温度230℃,基本上和比较例2(UV固化中的衬底温度是400℃)中一样,也可以充分地固化层间绝缘膜。
如图13C所示,在实例1中,膜应力与比较例2中的膜应力相比是足够低的。基于此,可以通过在UV固化中设置相对低的衬底温度来减小层间绝缘膜的膜应力。
如图13A所示,在实例1中,相对介电常数与比较例3中的相对介电常数相比是足够低的。基于此,可以看出通过进行He等离子体处理,即使当UV固化中的衬底温度设置得相对低时,也可以降低层间绝缘膜的相对介电常数。
基于这些结果,可以看出在相对低的衬底温度下进行UV固化,然后接着进行He等离子体处理,从而在阻止膜应力增加的同时,可以固化层间绝缘膜,而且能够充分地降低层间绝缘膜的相对介电常数。
图14是UV固化中衬底温度与相对介电常数、杨氏模量及膜应力之间的关系图。图14A是UV固化中衬底温度与层间绝缘膜的相对介电常数之间的关系图。图14B是UV固化中衬底温度与层间绝缘膜的杨氏模量之间的关系图。图14C是UV固化中衬底温度与层间绝缘膜的膜应力之间的关系图。
在所有情况中,都是在层间绝缘膜上已经进行UV固化后进行He等离子体处理的。用于UV固化的条件及用于He等离子体处理的条件与如上所述的实例1中的条件一样。不过,适当地设置了衬底温度。
如图14A所示,UV固化中的衬底温度设置在230℃-350℃的范围,如同UV固化中衬底温度是400℃的情况,也可以获得相对低的相对介电常数。
如图14B所示,UV固化中的衬底温度设置在230℃-350℃的范围,如同UV固化中衬底温度是400℃的情况,也可以获得相对高的杨氏模量。
如图14C所示,UV固化中的衬底温度设置在230℃-350℃的范围,与UV固化中衬底温度是400℃的情况相比较,膜应力被抑制得足够小。
基于上述,可以看出通过将UV固化中的衬底温度设置在230℃-350℃,确实可以阻止层间绝缘膜的膜应力的提高。
如上所述,在本实施例中,将衬底温度设置在相对低的温度350℃或低于350℃,对SiOC层间绝缘膜进行UV固化。根据本实施例,将衬底温度设置得相对低来进行UV固化,在阻止层间绝缘膜的膜应力提高的同时,可以提高层间绝缘膜的硬度。由于UV固化中的衬底温度相对低,层间绝缘膜的相对介电常数在当UV固化已经完成的阶段还没有被充分地降低。为了充分降低层间绝缘膜的相对介电常数,在本实施例中,对层间绝缘膜进行He等离子体处理。在本实施例中,通过进行He等离子体处理,可以充分降低层间绝缘膜的相对介电常数。此外,即使在相对低的温度,He等离子体处理也可以充分降低层间绝缘膜的相对介电常数,而且在He等离子体处理中不会大幅提高膜应力。这样,根据本实施例,在阻止层间绝缘膜的膜应力大幅提高的同时,可以固化层间绝缘膜,并且可以充分降低层间绝缘膜的相对介电常数。因此,根据本实施例,可以提供具有高可靠性和优良电气特性的半导体器件。
【变型的实施例】
本发明不仅限于上述实施例,而是可以包括其他各种变型例。
例如,在上述实施例中,例如,形成SiOC膜作为包含硅和氧的层间绝缘膜,但是SiOC膜并不是必需的。本半导体器制造方法可以被更广泛地应用到包含硅、碳及氧的层间绝缘膜。例如,该层间绝缘膜可以是SiOCH膜。
此处叙述的全部实例和条件语言都是作为教导目的,用于帮助读者理解本发明以及发明人为了促进技术而贡献的概念并应解释为不是限制于这些具体叙述的实例和条件,说明书中的这些实例的安排也不是为了显示本发明的优劣。尽管已经详细地描述了本发明的实施例,但是应当理解,在不脱离本发明的精神和范围的情况下,可对本发明进行各种变化、替代和更改。
Claims (12)
1.一种半导体器件制造方法,包括:
通过化学气相沉积,在半导体衬底上形成包含硅、氧及碳的绝缘膜;
在形成所述绝缘膜后,对在350℃或低于350℃的温度下正在进行加热的所述绝缘膜进行UV固化;以及
在所述UV固化后,对所述绝缘膜进行氦等离子体处理。
2.如权利要求1所述的半导体器件制造方法,其中:
所述绝缘膜为SiOC膜。
3.如权利要求1所述的半导体器件制造方法,其中:
在所述UV固化中,对在230℃-350℃范围内的温度下正在进行加热的所述绝缘膜进行所述UV固化。
4.如权利要求2所述的半导体器件制造方法,其中:
在所述UV固化中,对在230℃-350℃范围内的温度下正在进行加热的所述绝缘膜进行所述UV固化。
5.如权利要求1所述的半导体器件制造方法,其中:
在所述氦等离子体处理中,对在350℃或低于350℃的温度下正在进行加热的所述绝缘膜进行所述氦等离子体处理。
6.如权利要求2所述的半导体器件制造方法,其中:
在所述氦等离子体处理中,对在350℃或低于350℃的温度下正在进行加热的所述绝缘膜进行所述氦等离子体处理。
7.如权利要求3所述的半导体器件制造方法,其中:
在所述氦等离子体处理中,对在350℃或低于350℃的温度下正在进行加热的所述绝缘膜进行所述氦等离子体处理。
8.如权利要求4所述的半导体器件制造方法,其中:
在所述氦等离子体处理中,对在350℃或低于350℃的温度下正在进行加热的所述绝缘膜进行所述氦等离子体处理。
9.如权利要求5所述的半导体器件制造方法,其中:
在所述氦等离子体处理中,对在100℃-350℃范围内的温度下正在进行加热的所述绝缘膜进行所述氦等离子体处理。
10.如权利要求6所述的半导体器件制造方法,其中:
在所述氦等离子体处理中,对在100℃-350℃范围内的温度下正在进行加热的所述绝缘膜进行所述氦等离子体处理。
11.如权利要求7所述的半导体器件制造方法,其中:
在所述氦等离子体处理中,对在100℃-350℃范围内的温度下正在进行加热的所述绝缘膜进行所述氦等离子体处理。
12.如权利要求8所述的半导体器件制造方法,其中:
在所述氦等离子体处理中,对在100℃-350℃范围内的温度下正在进行加热的所述绝缘膜进行所述氦等离子体处理。
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US20110312191A1 (en) | 2011-12-22 |
US8716148B2 (en) | 2014-05-06 |
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