CN101315917A - 配线基板及其制造方法 - Google Patents

配线基板及其制造方法 Download PDF

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CN101315917A
CN101315917A CNA2008101086729A CN200810108672A CN101315917A CN 101315917 A CN101315917 A CN 101315917A CN A2008101086729 A CNA2008101086729 A CN A2008101086729A CN 200810108672 A CN200810108672 A CN 200810108672A CN 101315917 A CN101315917 A CN 101315917A
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wiring substrate
connection pads
external connection
overlay coating
insulating barrier
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CN101315917B (zh
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金子健太郎
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Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
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Shinko Electric Co Ltd
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Abstract

本发明公开一种配线基板及其制造方法，所述配线基板具有预定数量的配线层和位于各配线层之间的绝缘层。配线基板具有外部连接焊盘，用于连接到外部电路上的表面镀层布置在所述外部连接焊盘上。外部连接焊盘的面积小于表面镀层的面积。

Description

配线基板及其制造方法
技术领域
本发明涉及一种配线基板及其制造方法。更具体地说，本发明涉及在一侧设置有用于安装半导体元件等的焊盘并在另一侧设置有用于连接到另一个安装基板上的焊盘的配线基板。
背景技术
用于在封装体上形成半导体元件、其它电子部件等的配线基板在一侧设置有用于安装半导体元件、电子部件等的焊盘，并在另一侧设置有用于连接到另一个安装基板上的焊盘。外部连接焊盘的表面设置有表面镀层，该表面镀层用于连接到半导体元件等上并结合到用于连接安装基板的焊点上。通过在焊盘侧薄薄地镀覆镍(Ni)、金(Au)等形成表面镀层。
图13示出在通过普通积层技术制造的配线基板中的外部连接焊盘的实例。附图中的外部连接焊盘101是由铜(Cu)等导电材料在配线基板最外侧的绝缘层102上形成的，并通过导通塞105连接到形成于下层配线103一端的焊盘104上，上述导通塞105在与外部连接焊盘101对应的位置处贯通绝缘层102。配线基板的最上表面设置有阻焊层106，阻焊层106设置有用于露出外部连接焊盘101的一部分上表面的开口部分107。表面镀层108布置在外部连接焊盘101的外露上表面上。
制造配线基板存在这样一种方法：该方法不使用用于通过积层技术在其两侧交替地形成配线层和绝缘层的芯板。该方法包括首先在铜板等支撑部件上形成第一外部连接焊盘(将成为配线基板一侧的焊盘)以及表面镀层，通过积层技术在表面镀层和外部连接焊盘上形成所需数量的绝缘层和配线层，接着形成第二外部连接焊盘(将成为配线基板另一侧的焊盘)，然后移除支撑部件(例如，参见JP-T-2003/039219)。
图14示出通过该方法制造的配线基板一侧(在支撑部件上首先形成)的外部连接焊盘的实例。外部连接焊盘121的一侧被表面镀层122覆盖，并且表面镀层122的一个表面从最外侧的绝缘层123的表面露出。外部连接焊盘121通过贯通绝缘层123的导通塞124连接到设置在下层配线125一端的焊盘126上。配线基板另一侧的外部连接焊盘与参照图13说明的配线基板相似。
根据参照图13说明的现有技术配线基板的外部连接焊盘101，开口部分107形成在阻焊层106上，其中，通过在形成外部连接焊盘101后使阻焊层106覆盖配线基板的整个表面，只露出外部连接焊盘101的一部分以连接到半导体元件或外部电路上，从而形成该阻焊层106。因此，外部连接焊盘101需要形成为大于阻焊层106的开口部分107，这样妨碍了配线的小型化。
此外，由于形成的外部连接焊盘101较大，因此位于外部连接焊盘101和下层配线的焊盘104之间的树脂(详细地说，位于竖直虚线、焊盘101的下表面、焊盘104的上表面以及导通塞105的侧面之间的树脂)的量较大，并且由于树脂加热和收缩带来的应力，会使导通塞的连接可靠性降低。
在参照图14说明的现有技术配线基板的外部连接焊盘121中，可以解决上述问题。然而，表面镀层122及其下方的焊盘121具有相同的尺寸，因此，如图15所示，由于表面镀层122和绝缘层123之间的应力而产生的裂纹131易于沿着焊盘121的侧面延伸至绝缘层123内部，从而容易引起配线基板的性能降低。
发明内容
本发明的示例性实施例提供一种在一侧具有外部连接焊盘的配线基板，该配线基板不妨碍配线的小型化，能够保持导通塞的连接可靠性，并且不会引起所述配线基板的性能降低。
本发明的配线基板是如下配线基板，其包括：
绝缘层；
配线层，其设置在所述绝缘层的一侧；
外部连接焊盘，其设置在所述绝缘层的另一侧；
表面镀层，其形成于所述外部连接焊盘上，用于连接到外部电路上，其中，
所述外部连接焊盘的面积小于所述表面镀层的面积。
本发明的配线基板可以通过一种制造配线基板的方法进行制造，所述方法包括以下步骤：
在支撑部件上形成表面镀层，并在形成于所述支撑部件上的表面镀层上形成外部连接焊盘；
将所述外部连接焊盘处理为使得所述外部连接焊盘的面积小于所述表面镀层的面积；
在所述支撑部件的形成有所述外部连接焊盘的表面上形成绝缘层和配线层；以及
通过蚀刻法移除所述支撑部件。
优选的是，通过蚀刻法执行使所述外部连接焊盘的面积小于所述表面镀层的面积的处理。
根据本发明，提供一种在一侧包括外部连接焊盘的配线基板，该配线基板有益于配线的小型化，能够保持导通塞的连接可靠性，还可以用于防止所述配线基板的性能降低。
从以下详细描述、附图和权利要求中可以明显看出其它特征和优点。
附图说明
图1是用于说明本发明配线基板中外部连接焊盘的面积小于表面镀层的面积的视图。
图2是用于说明本发明配线基板中在外部连接焊盘小于表面镀层的部分处在表面镀层和绝缘层之间产生裂纹的视图。
图3A至图3D是用于说明实例1的配线基板的制造的第一视图。
图4A至图4D是用于说明实例1的配线基板的制造的第二视图。
图5是示出安装有半导体元件的实例1的配线基板的视图。
图6A至图6C是用于说明实例2的配线基板的制造的视图。
图7是示出安装有半导体元件的实例2的配线基板的视图。
图8A至图8D是用于说明实例3的配线基板的制造的视图。
图9是用于说明在实例3中制造的配线基板的视图。
图10A至图10D是用于说明实例4的配线基板的制造的视图。
图11是用于说明在实例4中制造的配线基板的视图。
图12A和图12B是用于说明在实例1中剥离抗镀图案之前对外部连接焊盘进行选择性蚀刻的视图。
图13是用于说明通过积层技术制造的现有技术配线基板的外部连接焊盘的视图。
图14是用于说明另一个现有技术的配线基板的外部连接焊盘的视图。
图15是用于说明在图14中说明的焊盘部分中在表面镀层和绝缘层之间产生裂纹的视图。
具体实施方式
本发明的配线基板的特征在于，配线基板一侧的外部连接焊盘的面积小于其表面镀层的面积。
图1示出本发明的外部连接焊盘1。焊盘1包括位于与外部电路连接的一侧的表面镀层2，焊盘1形成为其尺寸(面积)小于表面镀层2的尺寸(面积)。为了实现本发明的目的，焊盘1的尺寸越小越好。然而，焊盘1的尺寸的下限取决于制造步骤的精度，该制造步骤需要保证该焊盘1与连接到配线基板内部的配线4的导通塞3的结合。另一方面，安装到焊盘1上的表面镀层2的尺寸取决于与该表面镀层连接的焊点(未示出)的尺寸。需要考虑以上因素来确定焊盘1的实际尺寸。例如，在标准基板中，在焊盘1的外周部分和表面镀层2的外周部分之间的沿着水平方向的间隔(即由图1的附图标记A所表示的尺寸)可以为大约0.1至5μm，优选的是，大约1至3μm。在图1中，导通塞3实际上布置在与焊盘1对应的位置上，并通过连接到配线4一端的焊盘5连接到配线4上。除了表面镀层2的上表面，外部连接焊盘1、表面镀层2、导通塞3、配线4和连接到配线4上的焊盘5位于绝缘层7的内部。
在之前参照图13说明的现有技术中，阻焊层106的与用于连接外部电路的焊盘101相通的开口部分107的尺寸限定设置在其中的镀层108的尺寸并取决于所连接的焊点的尺寸。出于形成覆盖焊盘101的阻焊层106以及随后在阻焊层上形成开口部分107的需要，焊盘101需要形成为大于开口部分107，即大于表面镀层。
相反，在本发明中，使得外部连接焊盘1小于表面镀层2。因此，根据本发明的配线基板，可以使配线小型化并且使得位于外部连接焊盘1和焊盘5之间的树脂量，即如图1所示，位于竖直虚线、焊盘1下表面、焊盘5上表面以及导通塞3侧面之间的树脂量小于参照图13所描述的现有技术中的树脂量，并且还保持受树脂加热和收缩所产生的应力影响的导通塞连接可靠性。
在之前参照图14所述的现有技术中，如图15所示，产生这样的问题：由于表面镀层122和绝缘层123之间的应力而产生的裂纹131容易沿着焊盘121的侧面延伸至绝缘层123内部，从而容易引起配线基板的性能降低。
相反，在本发明中，如图2所示，在表面镀层2和绝缘层7之间产生的裂纹9在沿着表面镀层2的侧面延伸的位置处停止，并且没有过深地延伸到绝缘层7中。因此，避免了因裂纹而导致配线基板性能降低的问题。
根据本发明，“外部电路”指的是布置在配线基板外部并连接到配线基板上的电路。例如，可以列举出这样的电路作为根据本发明的“外部电路”：连接到配线基板上的半导体元件等的电子部件的电路、与安装有这种半导体元件等的配线基板相连接的安装基板的电路。
构成本发明配线基板的各部件的材料可以与普通配线基板的等同部件的材料相似。例如，可以列举出铜(Cu)或其合金等一般配线材料作为外部连接焊盘的材料。作为布置在外部连接焊盘上的表面镀层的材料，可以列举出(1)Ni和Au的组合，(2)Ni、Pd和Au的组合，(3)Sn，(4)Sn和Ag的组合等等。在(1)、(2)、(4)各种组合中，依次形成镀层以将Au层或Ag层暴露于外部。
可以通过以下方法制造本发明的配线基板：首先在包括铜板、铜箔等金属的支撑部件上形成外部连接焊盘(将成为配线基板一侧的焊盘)以及表面镀层、通过积层法在外部连接焊盘和表面镀层上形成预定数量的绝缘层和配线层，接着形成外部连接焊盘(将成为另一侧的焊盘)，然后移除支撑部件；其中，在通过积层方法形成第一绝缘层之前执行使外部连接焊盘的尺寸小于表面镀层的尺寸的处理。
根据以该方法制造的配线基板，虽然首先在支撑部件上形成的外部连接焊盘成为尺寸小于表面镀层的尺寸的焊盘，但是另一侧的外部连接焊盘大于表面镀层。通常，前一焊盘可以用于在配线基板上安装半导体元件等的电子部件，而后一焊盘可以用于连接到安装基板。然而，根据不同情况，使用方式可以颠倒。
实例
接下来，将进一步通过实例说明本发明。然而，本发明不限于本文所示的实例。
实例1
根据该实例，将说明如下配线基板及其制造方法，在所述配线基板中位于安装半导体元件的一侧的外部连接焊盘小于表面镀层。
如图3A所示，在构成支撑部件31的Cu板表面上形成抗镀图案32。对于支撑部件31，除了铜板以外可以使用铜箔或者能够通过普通的蚀刻溶液移除的金属(或合金)的箔或板。如图3B所示，通过无电镀法在从抗镀图案32的开口部分32a(图3A)(直径100μm)的底部露出的铜板上依次形成表面镀层33和外部连接焊盘34。在该情况下，由厚度分别为0.5μm和5μm的Au层和Ni层(Au层和Ni层以该顺序形成)形成表面镀层33。外部连接焊盘34由厚度为10μm的Cu形成。
接下来，剥离并移除抗镀图案32，选择性地蚀刻外部连接焊盘34并且使其直径比表面镀层33的直径小大约1至3μm(图3C)。可以在剥离抗镀图案32之前对外部连接焊盘34执行选择性蚀刻(如图12A所示，在该情况下对外部连接焊盘34进行选择性蚀刻)，在通过仅溶解Cu的蚀刻溶液蚀刻外部连接焊盘34之后移除抗镀图案32(图12B)。接着，如图3D所示，通过在支撑部件31的形成有外部连接焊盘34的表面上形成树脂膜来形成绝缘层35。在形成绝缘层35时，可以使用环氧树脂、聚酰亚胺等树脂膜。
如图4A所示，通过激光加工在绝缘层35上形成过孔35a。对于过孔35a，其在绝缘层35表面处的直径为60μm并在使焊盘34露出的底部处的直径为50μm。接着，形成连接到焊盘34上的导通塞36和连接到导通塞36上的配线层37(图4B)。例如，可以使用半加成法等普通方法。
接着，如图4C所示，通过重复形成绝缘层并形成导通塞和配线层，形成预定数量的绝缘层35和配线层37并在最上面的绝缘层35上形成外部连接焊盘38，然后，形成阻焊层39，该阻焊层39具有与焊盘38相通的开口部分39a。此外，通过无电镀法在从开口部分39a露出的焊盘38上形成表面镀层40。如图4D所示，通过蚀刻移除支撑部件31并完成配线基板30。完成的配线基板30的被移除支撑部件31的一侧成为半导体元件安装面。
图5示出安装有半导体元件41的配线基板30。通过焊点回流由焊接结合部件42将半导体元件41连接到配线基板30。
实例2
这里将说明由与实例1的配线基板相反的表面构成半导体元件安装面的实例。
通过在实例1中参照图3A至图3D和图4A、图4B说明的方法，形成如图6A所示的中间产品，其中在Cu板制成的支撑部件51上形成有表面镀层52、外部连接焊盘53、绝缘层54、导通塞55和配线层56。在配线层56的一部分配线处形成外部连接焊盘57。接着，如图6B所示，形成阻焊层58，该阻焊层58具有与焊盘57相通的开口部分58a，并且通过无电镀法在从开口部分58a露出的焊盘57上形成表面镀层59。通过使用蚀刻法移除支撑部件51来完成配线基板50(图6C)。
图7示出安装有半导体元件61的配线基板50。半导体元件61通过引线结合法连接到配线基板50。密封树脂60形成在配线基板50上以覆盖半导体元件61。
此外，还可以在将半导体元件安装到移除支撑部件51之前的配线基板(在图6B所示状态下的配线基板)上之后，再移除支撑部件。
虽然在上述实例中，已经说明了这样的配线基板：其中，形成为大于外部连接焊盘的表面镀层的外侧表面设置在与绝缘层相同的表面内，但是，也可以构成这样的配线基板：其中，表面镀层凹入绝缘层的表面或者表面镀层从绝缘层表面突出。接下来，将说明这种配线基板的实例。
实例3
这里将说明表面镀层凹入绝缘层表面的配线基板。制造这种配线基板的方法基本与以上实例中描述的相似，因此，如下说明将集中于形成表面镀层凹入绝缘层表面的结构的步骤。
首先，如图8A所示，在构成支撑部件71的Cu板表面上形成具有开口部分72a的抗镀图案72，并在从开口部分72a的底部露出的支撑部件71上形成由与支撑部件71相同的Cu材料构成的镀层73。接着，如图8B所示，相似地通过无电镀法依次形成包括Au层和Ni层的表面镀层74以及Cu构成的外部连接焊盘75。
剥离并移除抗镀图案72，选择性地蚀刻外部连接焊盘75以使其直径小于表面镀层74的直径(图8C)。可以在剥离抗镀图案72之前对外部连接焊盘75进行选择性的蚀刻。接下来，如图8D所示，通过在支撑部件71的形成有外部连接焊盘75的表面上层压树脂膜来形成绝缘层76。
然后，通过使用在实例1中参照图4A至图4D说明的步骤，完成图9所示的配线基板78。对于配线基板78，在通过蚀刻法移除支撑部件71时，随之移除由与支撑部件71相同的材料制成的镀层73，并且由凹入绝缘层76表面的结构构成表面镀层74。
对于配线基板78，表面镀层74设置在从绝缘层76表面凹入的部分，因此可以将用于连接到外部电路上的焊球稳定地安装于表面镀层上。
实例4
这里说明表面镀层从绝缘层表面突出的配线基板。制造这种配线基板的方法基本与以上实例说明的相似，因此如下说明将集中于形成表面镀层从绝缘层表面突出的结构的步骤。
如图10A所示，在构成支撑部件81的Cu板表面上形成具有开口部分82a的抗镀图案82，通过采用该图案构成的掩模蚀刻支撑部件81的从开口部分82a底部露出的一部分来形成凹入部83。接下来，如图10B所示，通过电镀法形成包括Au层和Ni层的表面镀层84以填充凹入部83，并且通过无电镀Cu法形成外部连接焊盘85。
移除抗镀图案82，选择性地蚀刻外部连接焊盘85以使其直径小于表面镀层84的直径(图10C)。可以在移除抗镀图案82之前对外部连接焊盘85进行选择性蚀刻。接着，如图10D所示，通过在支撑部件81的形成有外部连接焊盘85的表面上层压树脂膜来形成绝缘层86。
然后，通过使用在实例1中参照图4A至图4D说明的步骤，完成图11所示的表面镀层84从绝缘层86表面突出的配线基板88。
对于配线基板88，表面镀层84本身包括从绝缘层86突出的宽部和嵌入绝缘层86的窄部，表面镀层的一部分由阶梯形构成，因此可以进一步防止产生裂纹。此外，通过使表面镀层84突出，可以减少安装半导体元件的焊料(焊接结合部件)量并使半导体元件的结合高度稳定。
虽然已经参照有限数量的实施例描述了本发明，本领域技术人员在阅读本发明之后将理解到，可以在不脱离本文披露的本发明的范围的情况下作出其它实施例。相应地，本发明的范围应该仅由所附权利要求书限定。
本申请要求2007年5月30日向日本专利局提交的日本专利申请No.2007-143340的优先权，该日本专利申请No.2007-143340的全部内容通过引用并入本文。

Claims (8)

1.一种配线基板，包括：
绝缘层；
配线层，其设置在所述绝缘层的一侧；
外部连接焊盘，其设置在所述绝缘层的另一侧；
表面镀层，其形成于所述外部连接焊盘上，用于连接到外部电路上，其中，
所述外部连接焊盘的面积小于所述表面镀层的面积。
2.根据权利要求1所述的配线基板，包括：
多个配线层和设置在各配线层之间的多个绝缘层。
3.根据权利要求1所述的配线基板，其中，
所述外部连接焊盘是用于将半导体元件等的电子部件安装到所述配线基板上的焊盘。
4.根据权利要求1所述的配线基板，其中，
所述外部连接焊盘是将所述配线基板安装到另一个基板上的焊盘。
5.根据权利要求1至4中任一项所述的配线基板，其中，
所述外部连接焊盘的材料是铜或其合金。
6.根据权利要求1至4中任一项所述的配线基板，其中，
所述表面镀层是由Ni和Au的组合，或Ni、Pd和Au的组合，或Sn，或Sn和Ag的组合形成的。
7.一种制造配线基板的方法，包括：
在支撑部件上形成表面镀层，并在形成于所述支撑部件上的表面镀层上形成外部连接焊盘；
将所述外部连接焊盘处理为使得所述外部连接焊盘的面积小于所述表面镀层的面积；
在所述支撑部件的形成有所述外部连接焊盘的表面上形成绝缘层和配线层；以及
通过蚀刻法移除所述支撑部件。
8.根据权利要求7所述的制造配线基板的方法，其中，
通过蚀刻法执行使得所述外部连接焊盘的面积小于所述表面镀层的面积的处理。
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