CN105374780A - 具有包括处理层的窄因子过孔的电子封装 - Google Patents

具有包括处理层的窄因子过孔的电子封装 Download PDF

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Publication number
CN105374780A
CN105374780A CN201510629023.3A CN201510629023A CN105374780A CN 105374780 A CN105374780 A CN 105374780A CN 201510629023 A CN201510629023 A CN 201510629023A CN 105374780 A CN105374780 A CN 105374780A
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via hole
insulating body
packaging
body layer
layer
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CN201510629023.3A
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CN105374780B (zh
Inventor
R·斯瓦米纳坦
S·阿加阿拉姆
A·P·阿卢尔
R·维斯瓦纳思
任纬伦
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Intel Corp
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Intel Corp
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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Abstract

本公开内容涉及具有包括处理层的窄因子过孔的电子封装。本公开内容总体上涉及电子封装以及方法，所述电子封装包括：导电焊盘、封装绝缘体层以及过孔，所述封装绝缘体层包括实质上非导电的材料，所述封装绝缘体层是实质上平坦的。所述过孔可以形成在所述封装绝缘体层内并且电耦合到所述导电焊盘。所述过孔可以包括导体和处理层，所述导体垂直延伸贯穿所述封装绝缘体层的至少部分并且具有接近所述导电焊盘的第一端部和与所述第一端部相对的第二端部，所述处理层被固定到所述导体的所述第二端部，所述处理层包括金复合物。

Description

具有包括处理层的窄因子过孔的电子封装
技术领域
本公开内容在此总体上涉及具有过孔的电子封装及其方法。
背景技术
电子封装，诸如电路板和芯片封装，通常包括具有输入/输出焊盘的硅管芯。那些焊盘可以焊接至电介质板上的其它焊盘。该板上的焊盘可以耦合到该板内的导体，其可以传输来往于管芯的电信号，从而经由该板而在硅管芯与其它器件之间提供电连通性。板常规地包括导体和其它材料的多个层，诸如接地层等。过孔可以延伸穿通该板以将一个层耦合到另一个层。
附图说明
图1示出了在示例性实施例中电子封装的侧视图。
图2示出了在示例性实施例中包括焊接至电子封装的芯片封装的电子组件。
图3示出了在示例性实施例中电子封装的实施例。
图4是在示例性实施例中用于使用微电子组件的流程图。
图5是在示例性实施例中并入了至少一个微电子组件的电子装置的框图。
具体实施方式
下面的说明书和附图充分示出了具体实施例以使得本领域技术人员能够实现它们。其它实施例可以并入结构、逻辑、电气、过程以及其它变化。一些实施例中的部分和特征可以包括在或者替代其它实施例中的部分和特征。在权利要求中阐述的实施例包括了那些权利要求的所有有效等同方式。
嵌入式桥架构可以形成过孔，该过孔具有这种尺寸：当该过孔变成相对较高(诸如通过延伸贯通电介电的多个层)时，该过孔可以在焊盘上诱导相对大量的应力。这种应力可以引起诸如焊盘上或过孔内的破裂或者分层。此外，相对大的过孔可以消耗更多的材料(诸如铜)，并且可以在板中占据更大的占覆盖区，因此增大了成本。
已经将架构发展为在保持常规过孔性能的同时可以降低过孔尺寸。此外，相对于常规过孔，该过孔可以消耗更少的铜或其它材料，可以降低焊料凸块破裂，可以降低过孔分层，并且可以维持第一级互连(FLI)崩塌。与常规过孔不同，该过孔架构形成在该板的封装绝缘体层内并且包括导体和处理层(finishlayer)。该导体垂直延伸贯穿封装绝缘体层中的至少一些层。在实施例中，该处理层被固定到该导体并且包括钯-金复合物。在各个替代实施例中，该处理层包括诸如无电镀镍浸金(ENIG)、ENIG加上无电镀金(ENIG+EG)、以及镍-钯-金(NiPdAu)之类的多种金基组合物中的任何一种。额外地或者替代地，该处理层可以包括或者可以是有机可焊性保护剂(OSP)。作为该架构的结果，该过孔可以小于常规过孔，由此降低了焊盘上的应力并且改善了可靠性，而且在各个示例中，减少了使用的材料，由此降低了成本。
图1示出了在示例性实施例中电子封装100的侧视图。电子封装100可以是电路板或电子部件，硅管芯可以耦合到该电路板或电子部件上，由此以提供至硅管芯的输入/输出。
电子封装100包括封装绝缘体层102A、102B、102C(通称“封装绝缘体层102”)。在各个实施例中，封装绝缘体层可以是增层(buildup)电介质材料或阻焊剂。在示例中，增层电介质材料是Aiinomoto增层膜。封装绝缘体层102可以是实质上非导电的，并且各层102A、102B、102C可以顺序地并且在单独步骤中形成，每一个绝缘体层102是实质上平坦的。
电子封装100还包括嵌入在封装绝缘体层中的一个层102C内的硅桥104。硅桥104可以在电子封装100内或附接至电子封装100的诸如包括但不限于处理器芯片和存储器芯片的多个芯片之类的各个部件之间提供连通性。在示例中，硅桥104至少部分地由硅制备。在示例中，硅桥104至少部分地由陶瓷(诸如氧化铝)制备。在示例中，硅桥104至少部分地由包括有机材料的一个或多个有机内插件制备。
嵌入在封装绝缘体层102内的过孔106可以提供垂直贯穿封装绝缘体层102的电连通性。在示例中，过孔106延伸贯穿一个层102，其中多个过孔106(例如，过孔106A、106B、106C)叠置以延伸贯穿多个层102A、102B、102C。每一个过孔106包括导体108。在各个实施例中，导体108中的某些或全部由镍构成。某些过孔106A、106D、106E包括处理层110，处理层110被配置为在通常在过孔106与诸如焊球、管脚等的外部电子部件之间提供连接。在电子封装100内部并且不与外部电子部件相连接的过孔可选地不包括处理层110。
在各个示例中，处理层110由金基复合物构成。在示例中，金基复合物是钯-金复合物。在此所公开的该复合物可以是材料的不均匀混合物或者这种材料的实质上同质的层。在各个替代实施例中，该处理层包括诸如无电镀镍浸金(ENIG)、ENIG加上无电镀金(ENIG+EG)、以及镍-钯-金(NiPdAu)之类的各种金基复合物和/或组合物中的任何金基复合物和/或组合物。额外地或者替代地，处理层110可以包括或者可以是替代的贵金属基层。额外地或者替代地，处理层110可以包括或者可以是有机可焊性保护剂(OSP)。例如与铜或在过孔结构中常规使用的其它材料相比，该金基复合物可以相对不易受侵蚀和/或电迁移影响。
在示例中，处理层110可以由无电镀钯的层和无电镀金的层形成，无电镀钯的层和无电镀金的层可以一起形成金复合物。在示例中，钯层耦合到导体108，并且金层耦合或能够耦合到焊球或其它连接件。示例性尺寸可以包括该钯层大约为四十(40)纳米厚并且该金层大约为六十(60)纳米厚。
诸如利用无电镀工艺并且然后通过在导体108的顶部施加处理层110来电镀该镍导体，过孔106可以形成在过孔106要被嵌入到的层102中。过孔106可以在导电焊盘112、硅桥104与电子部件之间提供连通性，该电子部件可以耦合到除了其它潜在目标之外的处理层110。每一个导体108包括接近导电焊盘112的第一端部114和处理层110被固定到的第二端部116。
在各个示例中，具有处理层110的过孔106(即，过孔106A、106D、106E)包括由第一材料构成的导体108，而其它过孔106可以包括由不同于第一材料的第二材料构成的导体。在各个示例中，第一材料是镍并且第二材料是铜。在各个替代示例中，各种适合材料中的任何材料可以用于第一材料与第二材料之间。
出于多样性目的，电子封装100可以是各种适合尺寸中的任何尺寸。在示例性实现方式中，过孔106A、106B、106C包括具有四十九(49)微米的顶部直径118的导体108。导体108A、108D、108E具有七(7)微米的高度120，而导体108B、108C分别具有二十七(27)和二十五(25)微米的高度122、124。焊盘112具有十五(15)微米的垂直厚度126以及七十七(77)微米的水平宽度128。其它过孔106D、106E包含具有二十二(22)微米的顶部直径130和七(7)微米的高度132的导体108。在示例中，层102A具有从焊盘108的顶部136至电子封装100的外部表面138的十二(12)微米的厚度134。在示例中，在焊盘108之间的间隔140可以为至少十三(13)微米。可选地耦合在过孔106F、106G与硅桥104之间的焊盘142可以具有五十(50)微米的宽度144。以上尺寸仅是出于示例性目的并且基于环境和偏差是近似的。
图2示出了在示例性实施例中包括焊接至电子封装100的芯片封装202的电子组件200。电子组件200示出了FLI架构。
芯片封装202包括硅管芯204和导电焊盘206，导电焊盘206例如由铜制成且耦合到硅管芯204。焊球208耦合或者可以耦合到导电焊盘206并且能够耦合到电子封装100的处理层110。应当指出，电子组件200未完全形成，如所示出的。相反，一旦焊球208耦合到处理层110，在所示实施例中就可以充分组装电子组件200。
在所示出的示例中，芯片封装202还包括晶圆级底流(underflow)层210和毛细管底部填充层212，晶圆级底流层210围绕导电焊盘206。这种层210、212可以为芯片封装202提供稳定性和绝缘。出于相同或其它目的，这种层210、212可以省略或由其它层补充。
在电子封装100包括以上所提供的示例性尺寸的示例中，焊盘206和晶圆级底流层210可以具有大约十六(16)微米的厚度。焊球208A以及毛细管底部填充层212可以具有从十(10)至十五(15)微米的厚度。焊球208B、208C可以具有大约二十(20)微米的厚度。
图3示出了在示例性实施例中电子封装300的示例。电子封装300可以与电子封装100相同或类似并且还包括诸如膏状印刷焊料之类的耦合到过孔106的处理层110的焊球302。因此，电子封装300可以完全被配置为耦合到诸如芯片封装202之类的芯片封装。
图4是在示例性实施例中用于使用微电子组件的流程图。该微电子组件可以是微电子组件100或者可以是包括温度传感器102的任何微电子组件。
在操作400，形成导电焊盘。在示例中，焊盘耦合到硅桥。
在操作402，形成包括实质上非导电的材料的封装绝缘体层，该封装绝缘体层是实质上平坦的。在示例中，封装绝缘体层包括增层电介质材料和阻焊剂中的至少一种。在示例中，增层电介质材料是Aiinomoto增层膜。在示例中，封装绝缘体层至少部分地围绕导电焊盘。
在操作404，过孔的导体形成为垂直延伸贯穿封装绝缘体层的至少部分并且具有接近导电焊盘的第一端部和与第一端部相对的第二端部。
在操作406，过孔的处理层耦合到导体的第二端部，处理层包括钯-金复合物。
在操作408，第二过孔形成为电耦合在过孔与导电焊盘之间，并且至少部分地由封装绝缘体层围绕。在示例中，第一过孔的导体由第一材料构成，并且第二过孔包括由不同于第一材料的第二材料构成的导体。在示例中，第一材料是镍。
在操作410，焊球耦合到处理层。在示例中，焊料被配置为电耦合到硅管芯的连接件。
包括了使用如在本公开内容中所描述的电子组件的电子器件的示例，以示出针对所公开主题的更高级器件应用的示例。图5是并入了诸如电子封装100或与本文示例有关的其它电子或微电子组件之类的至少一个电子组件的电子装置500的框图。电子装置500仅是在其中可以使用本发明的实施例的电子系统的一个示例。电子装置500的示例包括但不限于个人计算机、台式计算机、移动电话、个人数字助理、MP3或者其它数字音乐播放器、可穿戴装置、物联网(IOTS)装置等。在此示例中，电子装置500包括数据处理系统，该数据处理系统包括用以耦合系统的各个部件的系统总线502。系统总线502在电子装置500的各个部件之中提供了通信链路，并且能够实现为单总线、为总线的组合或者以其它任何合适的方式。
电子组件510耦合到系统总线502。电子组件510可以包括任何电路或者电路的组合。在一个实施例中，电子组件510包括可以是任何类型的处理器512。如在此所使用的，“处理器”意指任何类型的计算电路，诸如但不限于微处理器、微控制器、复杂指令集计算(CISC)微处理器、精简指令集计算(RISC)微处理器、超长指令字(VLIW)微处理器、图形处理器、数字信号处理器(DSP)、多核处理器、或者任何其它类型的处理器或处理电路。
可以包括在电子组件510中的其它类型电路是定制电路、专用集成电路(ASIC)等，诸如例如在像移动电话、呼机、个人数字助理、便携式计算机、双向无线电装置以及类似电子系统的无线装置中使用的一个或多个电路(诸如，通信电路514)。该IC可以执行任何其它类型的功能。
电子装置500还可以包括外部存储器520，外部存储器520继而可以包括适于特定应用的一个或多个存储器元件，诸如以随机存取存储器(RAM)形式的主存储器522、一个或多个硬盘驱动器524、和/或操纵诸如光盘(CD)、数字化视频盘(DVD)等的可移动介质526的一个或多个驱动器。
电子装置500还可以包括显示器装置516、一个或多个扬声器518以及键盘和/或控制器530，键盘和/或控制器530可以包括鼠标、线路连接、触摸屏、语音识别装置，或者允许系统用户将信息输入到电子装置500以及从电子装置500接收信息的任何其它装置。
附加示例
示例1可以包括的主题(诸如设备、方法、用于执行动作的装置)可以包括：导电焊盘；封装绝缘体层，该封装绝缘体层包括实质上非导电的材料，该封装绝缘体层是实质上平坦的；以及过孔，该过孔形成在封装绝缘体层内并且电耦合到导电焊盘，该过孔包括垂直延伸贯穿封装绝缘体层的至少部分并且具有接近导电焊盘的第一端部和与第一端部相对的第二端部的导体以及被固定到该导体的第二端部的处理层，该处理层包括金复合物。
在示例2中，示例1的电子封装可选地还包括：金复合物是钯-金复合物。
在示例3中，示例1和2中的任何一个或多个示例中的电子封装可选地还包括：金复合物是无电镀镍浸金(ENIG)、ENIG加上无电镀金(ENIG+EG)、以及镍-钯-金(NiPdAu)中的一种。
在示例4中，示例1-3中的任何一个或多个示例中的电子封装可选地还包括：封装绝缘体层包括增层电介质材料和阻焊剂中的至少一种。
在示例5中，示例1-4中的任何一个或多个示例中的电子封装可选地还包括：增层电介质材料是Aiinomoto增层膜。
在示例6中，示例1-5中的任何一个或多个示例中的电子封装可选地还包括：封装绝缘体层至少部分围绕导电焊盘。
在示例7中，示例1-6中的任何一个或多个示例中的电子封装可选地还包括：过孔是第一过孔，并且电子封装还包括第二过孔，该第二过孔电耦合在过孔与导电焊盘之间并且至少部分地由封装绝缘体层围绕。
在示例8中，示例1-7中的任何一个或多个示例中的电子封装可选地还包括：第一过孔的导体由第一材料构成，并且第二过孔包括由不同于第一材料的第二材料构成的导体。
在示例9中，示例1-8中的任何一个或多个示例中的电子封装可选地还包括：第一材料是镍。
在示例10中，示例1-9中的任何一个或多个示例中的电子封装可选地还包括：焊球耦合到处理层。
在示例11中，示例1-10中的任何一个或多个示例中的电子封装可选地还包括：焊料被配置为电耦合到硅管芯的连接件。
在示例12中，示例1-11中的任何一个或多个示例中的电子封装可选地还包括：焊盘耦合到硅桥。
在示例13中，示例1-12中的任何一个或多个示例中的电子封装可选地还包括：硅桥由硅、陶瓷以及有机内插件中的至少一种制备。
示例14可以包括的主题(诸如设备、方法、用于执行行动的装置)可以包括：形成导电焊盘；形成封装绝缘体层，该封装绝缘体层包括实质上非导电的材料，该封装绝缘体层是实质上平坦的；形成过孔的导体，该导体垂直延伸贯穿封装绝缘体层的至少部分并且具有接近导电焊盘的第一端部和与第一端部相对的第二端部；以及将过孔的处理层耦合到导体的第二端部，该处理层包括钯-金复合物。
在示例15中，示例14的方法可选地还包括：金复合物是钯-金复合物。
在示例16中，示例14和15中的任何一个或多个示例的方法可选地还包括：金复合物是无电镀镍浸金(ENIG)、ENIG加上无电镀金(ENIG+EG)、以及镍-钯-金(NiPdAu)中的一种。
在示例17中，示例14-16中的任何一个或多个示例的方法可选地还包括：封装绝缘体层包括增层电介质材料和阻焊剂中至少一种。
在示例18中，示例14-17中的任何一个或多个示例的方法可选地还包括：增层电介质材料是Aiinomoto增层膜。
在示例19中，示例14-18中的任何一个或多个示例的方法可选地还包括：封装绝缘体层至少部分围绕导电焊盘。
在示例20中，示例14-19中的任何一个或多个示例的方法可选地还包括：过孔是第一过孔，并且该方法还包括形成第二过孔，该第二过孔电耦合在过孔与导电焊盘之间并且至少部分地由封装绝缘体层围绕。
在示例21中，示例14-20中的任何一个或多个示例的方法可选地还包括：第一过孔的导体由第一材料构成，并且第二过孔包括由不同于第一材料的第二材料构成的导体。
在示例22中，示例14-21中的任何一个或多个示例的方法可选地还包括：第一材料是镍。
在示例23中，示例14-22中的任何一个或多个示例的方法可选地还包括：将焊球耦合到处理层。
在示例24中，示例14-23中的任何一个或多个示例的方法可选地还包括：焊料被配置为电耦合到硅管芯的连接件。
在示例25中，示例14-24中的任何一个或多个示例的方法可选地还包括：将焊盘耦合到硅桥。
在示例26中，示例14-25中的任何一个或多个示例的方法可选地还包括：由硅、陶瓷以及有机内插件中的至少一种来制备硅桥。
这些非限制性示例中的每一个均可以立足于其自身，或者可以与其它示例中的一个或多个示例以任何置换或组合进行组合。
以上的具体实施方式包括对附图的参照，附图形成了具体实施方式的一部分。附图以示例的方式示出了在其中可以实现本发明的具体实施例。这些实施例在此也被称为“示例”。这些示例可以包括除了所示出或者所描述的元素之外的元素。然而，本发明人还预期了在其中仅提供了所示出的或所描述的那些元素的示例。此外，相对于特定示例(或者其一个或多个方面)或者相对于在此所示出的或所描述的其它示例(或者其一个或多个方面)，本发明人还预期了使用所示出的或所描述的那些元素(或者其一个或多个方面)的任何组合或者置换的示例。
在本文献中，使用了专利文献中常见的术语“一”或“一个”以包括一个或者多于一个，独立于“至少一个”或者“一个或多个”的任何其它实例或用法。在本文献中，术语“或者”用于指代是无排他性或者使得“A或者B”包括“A而无B”、“B而无A”以及“A和B”，除非另有指示。在本文献中，属于“包含”以及“在其中”用作各自术语“包括”和“其中”的通俗英语等价词。而且，在下面的权利要求中，术语“包含”和“包括”是开放式的，即，在权利要求中包括除了在这种术语之后列出的那些元素之外的元素的系统、装置、制品、组分、构思或者过程还仍然被视为落入该权利要求的范围内。此外，在下面的权利要求中，术语“第一”、“第二”和“第三”等仅用作标记，并且不旨在对其对象施加数值要求。
以上的描述旨在是示例性的而非限制性的。例如，上述示例(或者其一个或多个方面)可以彼此结合使用。一旦回顾了以上描述，就可以诸如由本领域技术人员使用其它实施例。摘要提供为符合37C.F.R.§1.72(b)，以容许读者快速地确定技术公开内容的本质。提交了摘要，应理解为其将不用于解释或限制权利要求的范围或意义。此外，在上述具体实施方式中，各个特征可以组合在一起以使得本公开内容简单化。这不应解释为旨在使得未要求保护的所公开的特征对于任何权利要求是必需的。相反，发明的主题可以在于少于特定的所公开的实施例的所有特征。因此，下面的权利要求在此被并入到具体实施方式中，其中每一个权利要求自身作为一单独实施例，并且可以预期，这种实施例可以以各种组合或者置换彼此组合。本发明的范围应当参考所附的权利要求连同这种权利要求所要求的等同方式的全部范围一起来确定。

Claims (20)

1.一种电子封装，包括：
导电焊盘；
封装绝缘体层，所述封装绝缘体层包括实质上非导电的材料，所述封装绝缘体层是实质上平坦的；以及
过孔，所述过孔形成在所述封装绝缘体层内，所述过孔电耦合到所述导电焊盘，所述过孔包括：
导体，所述导体垂直延伸贯穿所述封装绝缘体层的至少部分并且具有接近所述导电焊盘的第一端部和与所述第一端部相对的第二端部；以及
处理层，所述处理层被固定到所述导体的所述第二端部，所述处理层包括金复合物。
2.根据权利要求1所述的电子封装，其中，所述金复合物是钯-金复合物。
3.根据权利要求1所述的电子封装，其中，所述金复合物是无电镀镍浸金(ENIG)、ENIG加上无电镀金(ENIG+EG)、以及镍-钯-金(NiPdAu)中的一种。
4.根据权利要求1-3中的任一项所述的电子封装，其中，所述封装绝缘体层包括增层电介质材料和阻焊剂中的至少一种。
5.根据权利要求4所述的电子封装，其中，所述增层电介质材料是Ajinomoto增层膜。
6.根据权利要求1-3中的任一项所述的电子封装，其中，所述封装绝缘体层至少部分地围绕所述导电焊盘。
7.根据权利要求1-3中的任一项所述的电子封装，其中，所述过孔是第一过孔，并且所述电子封装还包括第二过孔，所述第二过孔电耦合在所述过孔与所述导电焊盘之间并且至少部分地由所述封装绝缘体层围绕。
8.根据权利要求7所述的电子封装，其中，所述第一过孔的所述导体由第一材料构成并且所述第二过孔包括由不同于所述第一材料的第二材料构成的导体。
9.根据权利要求8所述的电子封装，其中，所述第一材料是镍。
10.根据权利要求1-3中的任一项所述的电子封装，还包括耦合到所述处理层的焊球。
11.根据权利要求10所述的电子封装，其中，焊料被配置为电耦合到硅管芯的连接件。
12.根据权利要求1-3中的任一项所述的电子封装，其中，所述焊盘耦合到硅桥。
13.根据权利要求12所述的电子封装，其中，所述硅桥由硅、陶瓷、以及有机内插件中的至少一种制备。
14.一种制造电子封装的方法，包括：
形成导电焊盘；
形成封装绝缘体层，所述封装绝缘体层包括实质上非导电的材料，所述封装绝缘体层是实质上平坦的；
形成过孔的导体，所述导体垂直延伸贯穿所述封装绝缘体层的至少部分并且具有接近所述导电焊盘的第一端部和与所述第一端部相对的第二端部；以及
将所述过孔的处理层耦合到所述导体的所述第二端部，所述处理层包括金复合物。
15.根据权利要求14所述的方法，其中，所述金复合物是钯-金复合物。
16.根据权利要求14所述的方法，其中，所述金复合物是无电镀镍浸金(ENIG)、ENIG加上无电镀金(ENIG+EG)、以及镍-钯-金(NiPdAu)中的一种。
17.根据权利要求14-16中的任一项所述的方法，其中，所述封装绝缘体层包括增层电介质材料和阻焊剂中的至少一种。
18.根据权利要求17所述的方法，其中，所述增层电介质材料是Ajinomoto增层膜。
19.根据权利要求14-16中的任一项所述的方法，其中，所述封装绝缘体层至少部分地围绕所述导电焊盘。
20.根据权利要求14-16中的任一项所述的方法，其中，所述过孔是第一过孔，并且所述方法还包括形成第二过孔，所述第二过孔电耦合在所述过孔与所述导电焊盘之间并且至少部分地由所述封装绝缘体层围绕。
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