TWI670814B - 單層無芯基板 - Google Patents

單層無芯基板 Download PDF

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Publication number
TWI670814B
TWI670814B TW102116163A TW102116163A TWI670814B TW I670814 B TWI670814 B TW I670814B TW 102116163 A TW102116163 A TW 102116163A TW 102116163 A TW102116163 A TW 102116163A TW I670814 B TWI670814 B TW I670814B
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Taiwan
Prior art keywords
layer
dielectric material
copper
wiring
chip
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TW102116163A
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English (en)
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TW201423926A (zh
Inventor
卓爾 赫爾維茨
陳先明
黃士輔
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大陸商珠海越亞半導體股份有限公司
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Publication of TW201423926A publication Critical patent/TW201423926A/zh
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Publication of TWI670814B publication Critical patent/TWI670814B/zh

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Abstract

本發明提供一種電子芯片封裝，其包括與插件的布線層接合的至少一個芯片，所述插件包括布線層和通孔柱層，其中所述通孔柱層被介電材料包圍，所述介電材料包括在聚合物樹脂中的玻璃纖維，其中所述電子芯片封裝還包括包覆所述至少一個芯片、所述布線層和導線的第二介電材料層。本發明還提供一種制造該電子芯片封裝的方法。

Description

單層無芯基板
本發明涉及電子芯片封裝及其制造方法。
消費電子產品如計算機和電信裝置包括集成電路芯片。這些電子產品需要IC基板作為芯片封裝部件。
IC基板需要具有高平坦度並且具有剛性和抗翹曲性以確保與下方基板的良好接觸。這種支撐結構的一般要求是可靠性以及合適的電氣性能、薄度、剛性、平坦性、散熱性好和有競爭力的單價。
已確立的相對廉價並且實現IC電路與外界通訊的常用芯片封裝類型是引線框架。引線框架使用延伸至外殼之外的金屬引線。引線框架技術可追溯到早期的DIP芯片，但其仍廣泛用于許多封裝類型。
引線框架用作IC封裝的“骨架”，在管芯組裝為成品的過程中為管芯提供機械支撐。引線框架由管芯附著的管芯焊盤和引線構成，所述引線用作向外電連接至外界的手段。通過引線接合或通過帶式自動鍵合，將管芯經由導線連接至引線。
在引線框架與連接導線相連後，使用作為塑料保護材料的模塑料覆蓋管芯或芯片。
用于制造更先進多層基板的其它技術包括用于連接介電材料內的焊盤或特征結構的層。提供穿過介電材料的通孔來連接不同層中的特征結構。
一種制造這種通孔的方法是鑽填法，其中通常利用激光來鑽孔穿過電介質，然後用導電材料例如銅來填充該孔，由此形成通孔。
一種制造通孔的替代方法是利用稱為“圖案鍍覆”的技術在光刻膠形成的圖案中沈積銅或其它金屬。隨後移除光刻膠，並用介電材料 層壓直立的通孔柱，所述介電材料優選是用以增強剛性的聚合物浸漬玻璃纖維氈預浸料。
在圖案鍍覆中，首先沈積種子層。然後在其上沈積光刻膠層，隨後曝光形成圖案，並且選擇性移除該圖案以制成暴露出種子層的溝槽。通過將銅沈積到光刻膠溝槽中來形成通孔柱。然後移除剩余的光刻膠，蝕刻掉種子層，並在其上及其周圍層壓通常為聚合物浸漬玻璃纖維氈的介電材料，以包圍所述通孔柱。然後，可以使用各種技術和工藝來減薄所述介電材料，將其平坦化並暴露出所述通孔柱頂部以允許通過通孔柱導電連接到底平面或基准面，用于在其上構建下一金屬層。可在其上通過重複該過程來沈積後續的金屬導體層和通孔柱，以構建所需的多層結構。
在一個替代但緊密關聯的技術即下文所稱的“面板鍍覆”中，將連續的金屬或合金層沈積到基板上。在其頂部沈積光刻膠層，並在其中顯影出圖案。剝除顯影光刻膠的圖案，選擇性地暴露出其下的金屬，該金屬可隨後被蝕刻掉。未顯影的光刻膠保護其下方的金屬不被蝕刻掉，並留下直立的特征結構和通孔的圖案。剝除未顯影光刻膠後，在所述直立的銅特征結構和/或通孔柱上及周圍層壓介電材料，如聚合物浸漬玻璃纖維氈。
通過諸如前述的圖案鍍覆或面板鍍覆方法創建的通孔層通常被稱為“通孔柱”。可以利用類似的技術制造特征層。
一種制造高密度互連的靈活技術是構建由介電基質中的金屬通孔或特征結構構成的圖案鍍覆或面板鍍覆的多層結構。所述金屬可以是銅，電介質可以是纖維增強聚合物，通常使用的是具有高玻璃化轉變溫度(Tg)的聚合物，例如聚酰亞胺。這些互連可以是有芯的或無芯的，並可包括用于堆疊元件的空腔。它們可具有奇數或偶數層。實現技術描述在授予Amitec-Advanced Multilayer Interconnect Technologies Ltd.的現有專利中。例如，赫爾維茨(Hurwitz)等人的題為“高級多層無芯支撐結構及其制造方法(Advanced multilayer coreless support structures and method for their fabrication)”的美國專利US 7,682,972描述了一種制造包括在電介質中的通孔陣列的獨立膜的方法，所述膜用作構建優異的電子支撐結構的前體。該方法包括以下步驟：在包圍犧牲載體的電介質中制造導電通孔膜，和將所 述膜與犧牲載體分離以形成獨立的層壓陣列。基于該獨立膜的電子基板可通過將所述層壓陣列減薄和平坦化，隨後端接通孔來形成。該公報通過引用全文並入本文。
赫爾維茨(Hurwitz)等人的題為“集成電路支撐結構及其制造方法(integrated circuit support structures and their fabrication)”的美國專利US 7,635,641描述了一種制造電子基板的方法，包括以下步驟：(A)選擇第一基礎層；(B)將蝕刻阻擋層沈積到所述第一基礎層上；(C)形成交替的導電層和絕緣層的第一半堆疊體，所述導電層通過貫穿絕緣層的通孔而互連；(D)將第二基礎層塗覆到所述第一半堆疊體上；(E)將光刻膠保護塗層塗覆到第二基礎層上；(F)蝕刻掉所述第一基礎層；(G)移除所述光刻膠保護塗層；(H)移除所述第一蝕刻阻擋層；(I)形成交替的導電層和絕緣層的第二半堆疊體，導電層通過貫穿絕緣層的通孔而互連；其中所述第二半堆疊體具有與第一半堆疊體基本對稱的構造；(J)將絕緣層塗覆到交替的導電層和絕緣層的所述第二半堆疊體上；(K)移除所述第二基礎層，以及，(L)通過將通孔末端暴露在所述堆疊體的外表面上並對其施加端子來端接基板。該公報通過引用全文並入本文。
多層基板能夠實現更高密度的互連並用于甚至更複雜的IC芯片。它們遠比簡單單層引線框架更為昂貴，對于許多電子應用來說，更經濟的引線框架才是適合的。
然而，引線框架技術存在許多局限。芯片通過引線接合連接至引線框架，連接導線越長，形成斷路並導致故障的導線斷裂危險就越大。此外，裝在一起的導線越接近，短路的可能性就越大。
介電材料內通孔柱的方法適用于多層基板，但通常因太過易損而不用于單層基板中，應當認識到翹曲和彎曲導致接觸不良、不可靠和短路。
本發明的實施方案解決了這些問題。
本發明的實施方案涉及提供新型芯片封裝解決方案。
一種電子芯片封裝包括與插件的布線層接合的至少一個芯 片，所述插件包括布線層和通孔柱層，其中所述通孔柱層被介電材料包圍，所述介電材料包括在聚合物樹脂中的玻璃纖維，並且所述芯片和所述布線層嵌入在第二介電材料層中，所述第二介電材料層包覆所述芯片和所述布線層。
在一些實施方案中，所述電子芯片封裝還包括在所述通孔柱層的與所述布線層相反側上的金屬犧牲基底。
在一些實施方案中，所述通孔柱層中的至少一個通孔柱具有非圓柱形狀，其特征在于X-Y平面內的長尺寸是X-Y平面內的短尺寸的至少3倍長度。
在一些實施方案中，所述插件的底面包括被所述介電材料包圍的所述通孔柱的銅端部，使得所述通孔柱的銅端部與該介電材料齊平。
在其它實施方案中，所述插件的底面包括被所述介電材料包圍的所述通孔柱的銅端部，使得所述通孔柱的銅端部相對于該介電材料凹陷至多5微米。
在其它實施方案中，所述通孔層還包括銅通孔柱和覆蓋遠離所述布線層的所述通孔柱的端部的阻擋金屬層，使得所述插件的底面包括通孔柱端部，所述通孔柱端部包括被介電材料包圍的阻擋金屬，使得所述通孔柱的阻擋金屬端部與該介電材料齊平。
通常，所述阻擋金屬層選自鎳、金、錫、鉛、鈀、銀及其組合。
在一些實施方案中，所述通孔的阻擋金屬層具有1微米至10微米範圍的厚度。
在一些實施方案中，所述至少一個芯片設置為倒裝芯片，其通過凸點陣列接合至所述布線層。
在一些這樣的實施方案中，所述第二介電材料層是玻璃纖維增強聚合物。
通常，所述至少一個芯片通過引線接合與所述布線層接合，並且所述第二介電材料層是模塑料。
任選地，包圍所述通孔柱的第一介電材料層包括第一聚合物 樹脂，包圍所述布線層和所述至少一個芯片的所述第二介電材料層包括第二聚合物樹脂，其中所述第一聚合物樹脂不同于所述第二聚合物樹脂。
任選地，包圍所述通孔柱的所述第一介電材料層包括無機填料。
任選地，包圍所述通孔柱的所述第一介電材料層的聚合物樹脂選自聚酰亞胺、環氧樹脂、BT樹脂(雙馬來酰亞胺/三嗪樹脂)、聚苯醚(PPE或PPO)及其共混物。
本發明的第二方面涉及提供一種制造電子芯片封裝的方法，包括以下步驟：(a)選擇犧牲基板；(b)在所述犧牲基板上沈積蝕刻阻擋層；(c)鍍覆通孔柱層；(d)用介電材料層壓所述通孔柱層；(e)減薄和平坦化介電材料層；(f)在所述通孔層上鍍覆布線特征層；(g)連接至少一個芯片；(h)用第二介電材料包覆所述至少一個芯片和布線特征結構；(i)移除所述犧牲基板，和(j)移除所述蝕刻阻擋層。
在一些實施方案中，步驟(g)包括將所述至少一個芯片引線接合至所述布線特征結構，步驟(h)包括用模塑料包覆所述至少一個芯片和布線特征結構。
在一些實施方案中，步驟(g)包括將所述至少一個芯片利用凸點陣列倒裝芯片接合至所述布線特征結構。
任選地，在這樣的實施方案中，步驟(h)包括用玻璃纖維聚合物預浸料進行包覆。
在一些實施方案中，所述犧牲基板包括可剝離銅基板、離型層和超薄銅箔，移除犧牲基板的步驟(i)包括剝除所述可剝離銅基板並蝕刻掉剩余的銅箔。
在一些實施方案中，所述犧牲基板包括覆銅層壓板，移除犧牲基板的步驟(j)包括蝕刻掉銅。
在一些實施方案中，所述方法還包括步驟(k)：通過移除所述蝕刻阻擋層以暴露出堆疊體外表面上的通孔端部並對所述通孔端部施加端子來端接所述基板。
在一些實施方案中，步驟(b)的阻擋層的沈積厚度為0.1微米至數十微米範圍，並且步驟(b)的蝕刻阻擋層：●包括選自鉭、鎢、鈦、鈦-鉭合金、鈦-鎢合金、鎳、錫、鉛和錫-鉛合金中的金屬，並且所述沈積包括濺射，或●包括選自鎳、錫、鉛和錫/鉛合金中的金屬，並且所述沈積通過選自電鍍和化學鍍的工藝進行。
在一些實施方案中，鍍覆通孔柱層的步驟(c)包括通過以下子步驟來圖案鍍覆所述通孔柱層：●敷設光刻膠層；●在所述光刻膠層中顯影出通孔圖案；●在所述圖案中鍍銅；和●剝除所述光刻膠層以留下直立的所述通孔。
在一些實施方案中，鍍覆通孔柱層的步驟(c)包括沈積端子材料和在所述端子材料上構建通孔柱。
在一些實施方案中，所述端子材料包括錫、錫-鉛合金、金、銀和鈀中的至少其一。
在一些實施方案中，鍍覆通孔柱層的步驟(c)包括通過以下子步驟來面板鍍覆所述通孔柱層：●面板鍍覆連續銅層；●在所述連續銅層上沈積光刻膠層；●在所述光刻膠層中顯影出通孔圖案；●蝕刻掉過量的銅以留下所述圖案；和●剝除已顯影的光刻膠層，留下直立的所述通孔。
在一些實施方案中，第一介電材料層包括聚合物樹脂，選自 聚四氟乙烯、聚四氟乙烯衍生物、雙馬來酰亞胺三嗪樹脂、環氧樹脂、聚酰亞胺樹脂、聚苯醚(PPE或PPO)及其混合物。
在一些實施方案中，第一介電材料層還包括以下至少其一：(a)無機顆粒填料，其平均粒徑為0.5微米至30微米，顆粒含量為15wt%-30wt%；(b)纖維，選自有機纖維和玻璃纖維，其排列成選自交叉複合排列、織造氈和隨機取向短纖維的排列。
在一些實施方案中，用介電材料層層壓通孔柱層的步驟(d)包括在通孔上施加預浸料以及通過熱壓機層壓預浸料進行固化，所述預浸料包括在基質中的玻璃纖維，所述基質選自聚酰亞胺、環氧樹脂或BT樹脂(雙馬來酰亞胺/三嗪樹脂)、聚苯醚(PPE或PPO)或其混合物。
在一些實施方案中，第二介電材料層包括聚合物樹脂，其選自聚四氟乙烯、聚四氟乙烯衍生物、雙馬來酰亞胺三嗪樹脂、環氧樹脂、聚酰亞胺樹脂、聚苯醚(PPE或PPO)及其混合物。
在一些實施方案中，第二介電材料層還包括以下至少其一：(a)無機顆粒填料，其平均粒徑為0.5微米至30微米，顆粒含量為15wt%-30wt%；(b)纖維，選自有機纖維和玻璃纖維，其排列成選自交叉複合排列、織造氈和隨機取向短纖維的排列。
在一些實施方案中，用介電材料層層壓通孔柱層的步驟(h)包括在芯片和布線層上施加預浸料以及通過熱壓層壓預浸料進行固化，所述預浸料包括在基質中的玻璃纖維，所述基質選自聚酰亞胺、環氧樹脂或BT樹脂(雙馬來酰亞胺/三嗪樹脂)、聚苯醚(PPE或PPO)或其混合物。
在一些實施方案中，減薄和平坦化介電材料層的步驟(e)包括選自幹蝕刻、機械研磨、化學機械抛光(CMP)、其組合及其兩階段過程的工藝。
在一些實施方案中，在通孔層上鍍覆布線特征層的步驟(f)包括：(i)在介電層上面板鍍覆銅，在其上敷設光刻膠層，顯影出布線特征 層的正性圖案，選擇性地蝕刻掉過量的銅以留下所述布線特征層，以及剝除所述光刻膠層；或(ii)敷設光刻膠層，顯影出溝槽圖案，在所述溝槽中圖案鍍覆布線特征層，以及剝除所述光刻膠層。
在一些實施方案中，步驟(f)還包括在經減薄的介電材料層上沈積粘附金屬層的預先步驟。
在一些實施方案中，所述粘附金屬層選自鈦、鉻、鎢、鎳-鉻合金和鈦-鎢合金。
在一些實施方案中，連接至少一個芯片的步驟(g)包括施加焊劑。
在一些實施方案中，將至少一個芯片連接至布線特征層的步驟(g)包括將金、鋁或銅導線從所述芯片延伸至所述布線特征層。
在一些實施方案中，移除犧牲基板的步驟(i)包括蝕刻掉銅。
在一些實施方案中，移除犧牲基板的步驟(i)包括剝除第一銅層和蝕刻掉剩余的銅。
在一些實施方案中，移除犧牲基板的步驟(i)采用濕蝕刻工藝，並且利用在步驟(b)中制造的蝕刻阻擋層作為蝕刻停止層。
在一些實施方案中，在步驟(b)中制造的蝕刻阻擋層包括鉭，用于蝕刻掉犧牲基板的步驟(i)中的蝕刻過程包括將犧牲基板暴露于升高溫度下的氫氧化銨溶液中。
在一些實施方案中，在步驟(b)中制造的蝕刻阻擋層選自鉭、鈦和鎢以及鈦-鎢合金，並且移除蝕刻阻擋層的步驟(j)包括使用CF4和氬氣的混合物的等離子體蝕刻，其中所述混合物通常具有的CF4與氬氣之比為1：1至3：1。
在一些實施方案中，在步驟(b)中制造的蝕刻阻擋層選自鉭、鈦和鎢以及鈦-鎢合金，並且移除蝕刻阻擋層的步驟(j)包括使用CF4和氧氣的混合物的等離子體蝕刻。
在一些實施方案中，所述方法還包括對通孔的暴露端部施加最終塗層，所述塗層選自鎳、金、錫、鉛、銀、鈀及其合金以及有機防鏽 面層。
術語微米或μm是指微米或10-6米。
100‧‧‧超薄芯片封裝、芯片封裝
110‧‧‧芯片
112‧‧‧銅通孔柱、通孔、通孔柱層、銅通孔、通孔柱
114‧‧‧布線特征層、布線層
116‧‧‧介電材料、阻擋層、介電層
118‧‧‧焊線、引線接合
120‧‧‧模塑料
122‧‧‧犧牲基板、基板
124‧‧‧插件
126‧‧‧阻擋層
128‧‧‧沈積端子材料、端子
222‧‧‧犧牲基板、基板、銅箔、可剝離銅基板
300‧‧‧支撐結構、芯片封裝
310‧‧‧芯片
314‧‧‧特征結構
318‧‧‧球形柵格陣列
320‧‧‧預浸料
324‧‧‧插件
412‧‧‧銅通孔、通孔柱
414‧‧‧布線層
418‧‧‧銅線
424‧‧‧插件
圖1是根據本發明的一個實施方案的電子芯片封裝的簡化截面圖。
圖2是根據本發明的第二實施方案的電子芯片封裝的簡化截面圖。
圖3是根據本發明的第三實施方案的電子芯片封裝的簡化截面圖。
圖4是根據本發明的第四實施方案的電子芯片封裝的簡化截面圖，示出能夠通過接點柵格陣列(LGA)或球形柵格陣列(BGA)實現芯片與基板連接的插件。
圖5是示出本文描述的電子芯片封裝可如何制造的流程圖。
各個附圖中相同的參考數字和附圖標記指示相同的要素。
為了更好地理解本發明並示出本發明的實施方式，純粹以舉例的方式參照附圖。
具體參照附圖時，必須強調的是特定的圖示是示例性的並且目的僅在于說明性地討論本發明的優選實施方案，並且基于提供被認為是對于本發明的原理和概念方面的描述最有用和最易于理解的圖示的原因而被呈現。就此而言，沒有試圖將本發明的結構細節以超出對本發明基本理解所必需的詳細程度來圖示；參照附圖的說明使本領域技術人員認識到本發明的幾種形式可如何實際體現出來。
在以下說明中，涉及的是包括在介電基體中的金屬通孔的支撐結構，特別是在聚合物基體中的銅通孔柱，所述聚合物基質例如是玻璃纖維增強的聚酰亞胺、環氧樹脂或BT樹脂(雙馬來酰亞胺/三嗪樹脂)、聚苯醚(PPE或PPO)或它們的共混物。
參照圖1，示出超薄電子芯片封裝的示意性截面圖。超薄芯片封裝100包括至少一個芯片110，所述芯片110通過銅布線特征層114連接至包圍在介電材料116內的銅通孔柱112，所述介電材料116由玻璃纖維增強的聚合物基質構成。所述芯片110可以通過焊線118(通常是金導線) 引線接合至布線特征層114，並且超薄芯片封裝100還包括包覆芯片110、布線特征層114和焊線118的模塑料120。
超薄芯片封裝100制造在通常為銅或銅合金的犧牲基板122上，僅在芯片110被接合到插件124即布線層114和通孔112上並且被模塑料120包覆後，才可以移除犧牲基板122。
利用這種獨特的構造，即芯片110和模塑料120提供主體並由此為包括單層通孔112的極薄插件124提供剛性，可以實現非常薄的芯片封裝。實際上，可以實現芯片尺寸封裝(CSP)。這樣的封裝是對小外形集成電路(SOIC)、方形扁平無引腳封裝(QFN)和兩層芯片尺寸封裝(2L CSP)的成本有效且高性能的替代。
如圖所示，芯片110連接至經抛光和減薄的通孔層上。所公開的構造比多層基板更薄，但不適合非常高密度的大數量互連。然而，與常規的引線框架不同，利用布線層114可以提供短焊線118，並且避免易于折斷的長焊線。而且，引線接合通常使用金線來實現，並且布線層是銅。因此，雖然實際的插件124往往比常規的引線框架更昂貴，但是在考慮到每個芯片110的全部封裝成本時，這樣的超薄芯片封裝100可能是成本有效的。此外，應當認識到，兩個以上的芯片110可以在常用插件124上並排安裝。
在圖2構造中，犧牲基板222包括市售的可剝離銅基板、離型層和超薄銅箔。Furukawa供應這種箔，商品名為F-DP和H-DP，具體參見Furukawa Review 38,2010.http：//www.furukawa.co.jp/review/fr038/fr38_06.pdf。
使用這種膜能夠剝離大多數基板222，並且只需要蝕刻掉相對薄的銅層，通常2-5微米的銅222，以暴露出在通孔柱112端部上的蝕刻阻擋層126。這可以在常規的芯片封裝廠實現。作為替代方案，基板制造廠可將芯片110附著在插件124上並以目標垂直整合進行包覆。
另一候選的基板是覆銅層壓板(CCL)，例如廣泛用于制造印刷電路板的CCL。
為了能夠實現蝕刻掉銅基板而不損傷通孔柱端部，在一些實 施方案中，通常是銅的通孔柱的沈積是以沈積抗蝕刻材料的阻擋層126開始的，所述阻擋層116例如是通過濺射沈積的鉭、鎢、鈦、鈦-鉭合金、鈦-鎢合金、鎳、錫、鉛或錫-鉛合金，或者是通過電鍍或化學鍍沈積的鎳、錫、鉛或錫-鉛合金。如果沒有這種蝕刻阻擋層，則通孔柱自身的前幾個微米通常是3-5微米被蝕刻掉，導致通孔柱端部相對于介電材料凹陷。雖然當芯片封裝附著至印刷電路板(PCB)時，凹陷的通孔柱需要更多的焊劑或其它連接材料來提供電連接，但是增加阻擋層增加了單位成本，因此有時候將其省去。
本發明的構造預期比兩層芯片尺寸封裝(CSP)具有更好的熱性能、更薄以及更低的單位成本，並且比微型引線框架具有更好的電氣性能和總體更低的成本。
參照圖3，示出一種經過適當修改的變化方案的支撐結構300，其中芯片310以倒裝芯片構造安裝並且通過球形柵格陣列318連接至插件324的布線特征結構314上。在該變化方案的支撐結構中，一個或更多個芯片310可采用玻璃纖維聚合物預浸料320而不是模塑料120進行包覆。
參照圖4，為了將芯片110或多芯片陣列以扇入(fan-in)型排列連接至基板，可以采用接點柵格陣列(LGA)或球形柵格陣列(BGA)。銅通孔412等距間隔排列成矩形格柵，如截面圖所示，其中一列顯示為等距間隔的通孔柱412隊列。布線層414縮短了銅線418需要跨越的距離，並且能夠使通孔柱412位于芯片110下方使用。以此方式，芯片可以引線接合(或倒裝芯片可以采用凸點陣列連接)至插件424，該插件424連接至接點柵格陣列。
在圖1-3中，沒有示出阻焊層以保持附圖簡潔。然而，應當認識到可以使用阻焊層來隔離布線層的端部。
參照圖5，一種制造電子芯片封裝的方法包括以下步驟：選擇犧牲基板122-步驟(a)。基板122通常是銅或銅合金，並且可以是簡單的銅片或市售的可剝離銅基板222，如下所述。
接著，在所述犧牲基板上沈積蝕刻阻擋層126-步驟(b)。通 常，蝕刻阻擋層的沈積厚度為0.1微米至數十微米的範圍，並且可包括濺射沈積的鉭、鎢、鈦、鈦-鉭合金、鈦-鎢合金、鎳、錫、鉛或錫-鉛合金或者電鍍或化學鍍沈積的鎳、錫、鉛或錫-鉛合金。
然後，在蝕刻阻擋層126上鍍覆通孔柱層112-步驟(c)。
在一個變化方案的制造方法中，鍍覆通孔柱層的步驟(c)包括通過以下子步驟圖案鍍覆所述通孔柱層：(i)敷設光刻膠層；(ii)在所述光刻膠層內顯影出通孔112的圖案；(iii)在所述圖案內鍍覆銅通孔112；和(iv)剝除所述光刻膠層，保留下直立的通孔柱112。
任選地，鍍覆通孔柱層的步驟(c)包括在所述圖案中沈積端子材料128，例如鎳、金、錫、鉛、錫-鉛合金、銀、鈀或其合金，並且在所述端子材料上通過在其上電鍍銅來構建銅通孔柱。
在另一變化方案的制造方法中，鍍覆通孔柱層的步驟(c)包括通過以下子步驟面板鍍覆所述通孔柱層：●面板鍍覆連續銅層；●在所述連續銅層上沈積光刻膠層；●在所述光刻膠層中顯影出通孔圖案；●蝕刻掉過量的銅以留下直立的通孔柱112；和●剝除已顯影的光刻膠，留下直立的通孔柱112。
應該認識到，與特征在于通孔基本為圓柱形並且所有通孔均相同的鑽填制通孔技術不同，本發明的制造方法采用鍍覆技術，其中通孔柱是被鍍覆到光刻膠圖案內或者從面板鍍覆層中蝕刻掉周圍材料而留下通孔柱，這在制造上具有無法比擬的靈活性，並且部分或全部通孔自身可提供平面布線。這樣的通孔柱可以條狀的，並且具有一個明顯更長的平面內尺寸，其可能是其它平面內尺寸的3倍以上長度。
接著，用介電材料116層壓通孔柱層112-步驟(d)。介電材料116可以選自聚四氟乙烯、聚四氟乙烯衍生物、雙馬來酰亞胺三嗪樹脂、環氧樹脂、聚酰亞胺樹脂、聚苯醚(PPE或PPO)及其混合物和共混物。
通常，介電材料116還包括以下至少其一：(a)無機顆粒填料，平均粒徑為0.5微米至30微米，顆粒含量為15wt%-30wt%；(b)纖維，選自有機纖維和玻璃纖維，其排列成選自交叉複合排列、織造氈和隨機取向短纖維的排列。
在一些實施方案中，用介電材料116層壓通孔柱層112的步驟(d)包括施加包括基質中玻璃纖維的預浸料，所述基質選自聚酰亞胺、環氧樹脂或BT(雙馬來酰亞胺/三嗪樹脂)、聚苯醚(PPE或PPO)或其共混物，然後通過熱壓層壓該預浸料進行固化。
通過在通孔柱上層壓預浸料，基板可具有剛性和抗翹曲性。選擇的聚合物具有對銅柱的良好粘附性。
接著，對介電層116進行減薄和平坦化以暴露出通孔柱112的端部-步驟(e)。在各種工藝路線中，介電層的減薄和平坦化通過幹蝕刻、機械研磨、化學機械抛光(CMP)及其組合以及其兩階段工藝來實現。
然後，在通孔柱層112上鍍覆布線特征層114。
在通孔柱層112上鍍覆布線特征層114可包括：(i)在所述介電層上面板鍍覆銅，在其上敷設光刻膠層，顯影出布線特征結構的正性圖案，選擇性地蝕刻掉過量的銅以留下布線特征結構114，以及剝除所述光刻膠層；或(ii)敷設光刻膠層，顯影出溝槽圖案，在所述溝槽中圖案鍍覆布線特征結構112，以及剝除所述光刻膠層。
為了有助于布線特征結構粘附至下方的介電材料116，可以先在減薄的介電材料上沈積粘附金屬層例如鈦、鉻或鎳/鉻合金，所述粘附金屬層通常具有0.04微米至0.1微米範圍的厚度。通過先沈積種子層而在其上沈積銅，這通常通過濺射或化學鍍進行，接著通過電鍍在其上構建銅層。
然後，將芯片110連接至介電層116-步驟(g)。在一些實施方案中，將芯片310連接至介電層116的步驟(g)包括施加焊劑。這可以用于簡單的機械接合，或者參照圖3，用于倒裝芯片構造中，采取球形柵格陣列318將芯片110電連接至基板(這不能采用常規的引線框架進行)。
利用采取球形柵格陣列318的倒裝芯片設置，可以用預浸料320而不是用傳統的模塑料來層壓芯片310和布線層312。這提供更薄且更剛性的產品。
在其它實施方案中，如圖1和2所示，芯片110連接至插件124是通過利用從芯片110至布線特征結構114延伸的金(或較不常用的鋁或銅)導線將芯片110引線接合至布線特征結構114來進行的。
由于布線特征結構，使得所需的焊線118長度可以少于常規引線框架排列所需的焊線長度。這顯著增加了芯片封裝的可靠性並且由于需要較少的金導線從而通常降低總成本。
接著，用模塑料120包覆芯片110、布線特征結構114和焊線118-步驟(h)。如果采用球形柵格陣列(圖3中的318)來連接倒裝芯片310至插件324，則可以使用具有增強纖維的介電材料，例如纖維在基質中的預浸料320。這比模塑料120具有更好的剛性，但是這不能與引線接合一同使用，因為玻璃纖維會破壞金焊線118。
在使用芯片110和模塑料20(纖維增強電介質320)來使結構100(300)具有剛性後，可以移除犧牲基板112-步驟(i)。這種在移除犧牲基板112之前施加芯片110和模塑料120的工藝路線是非常革命性的，因為這需要將未完成的基板供應至封裝裝配機或在基板裝配機中加入芯片110。當采用球形柵格陣列時，使用介電預浸料320替代模塑料120進一步增加了革命性的進展。
在一些實施方案中，移除犧牲基板的步驟(i)包括剝除可剝離銅基板222和蝕刻掉剩余的銅箔。
在一些實施方案中，蝕刻掉犧牲基板112/222的步驟(i)采用濕蝕刻過程，並且使用在步驟(b)中制造的蝕刻阻擋層126作為蝕刻停止層。
在一個制造路線中，在步驟(b)中制造的蝕刻阻擋層126包括鉭，並且由于蝕刻掉犧牲基板的步驟(i)中的蝕刻過程包括將犧牲基板暴露于升高溫度的氫氧化銨溶液中。作為替代方案，可以使用氯化銅作為蝕刻劑。
然後，可以利用合適的蝕刻劑來移除蝕刻阻擋層-步驟(j)。
在一個制造路線中，在步驟(b)中制造的蝕刻阻擋層126選自鉭、鈦和鎢，並且移除蝕刻阻擋層的步驟(j)包括使用CF4和氬氣的混合物的等離子體蝕刻，其中該混合物通常具有CF4與氬氣之比為1：1至3：1。在另一實施例中，蝕刻掉蝕刻阻擋層的方法通過使用比例為93：7的CF4：O2的等離子體蝕刻來進行。
在移除犧牲基板112(222)之後，如果蝕刻阻擋層126不適合用作端子，則任選地所述方法還包括移除蝕刻阻擋層126-步驟(j)以暴露出通孔柱122的端部，以及對通孔端部施加端子128-步驟(k)。
當在施加銅之前通過圖案鍍覆對蝕刻阻擋層126進行圖案化時，其可以用于端子目的。然而，通常該方法還包括步驟(1)-對通孔112的暴露端部施加最終塗層，所述最終塗層選自鎳、金、錫、鉛、銀、鈀及其合金或其汞合金以及有機防鏽面層。
由單通孔和布線層124一起構成的插件通常具有25至40微米厚度並且不能自支撐。但是，其可制造在犧牲基板112(222)上，例如約20微米厚的銅片上。傳統上，插件是以完全完成的形式供應至芯片封裝廠的。本發明的特征則在于將插件提供至基板上的芯片封裝機或者基板制造商將芯片110連接至插件124(324)，形成垂直整合(vertical integration)並簡化制造過程。
如上所述，芯片封裝100(300)包含單個管芯或芯片，但是應該認識到兩個管芯可以封裝在一起。例如，存儲器芯片和控制器可以並排設置在包括布線層和通孔層的插件上，通過球形柵格陣列318或通過引線接合118電連接至布線層312，或者一個芯片110利用倒裝芯片技術連接而另一個芯片利用引線接合連接，然後可以用模塑料包覆基板124的芯片110和布線層312，或者如果兩個芯片都是倒裝芯片通過且行柵格陣列318連接至插件324，則可以通過在其上層壓預浸料320進行包覆。
本文所述的新型封裝技術與化學鍍鎳/化學鍍鈀/浸鍍金(ENEPIG)端子技術兼容。
本領域技術人員將會認識到，本發明不限于上文中具體圖示 和描述的內容。而且，本發明的範圍由所附權利要求限定，包括上文所述的各個技術特征的組合和子組合以及其變化和改進，本領域技術人員在閱讀前述說明後將會預見到這樣的組合、變化和改進。
在權利要求書中，術語“包括”及其變體例如“包含”、“含有”等是指所列舉的組件被包括在內，但一般不排除其他組件。

Claims (45)

  1. 一種電子芯片封裝，包括與插件的布線層接合的至少一個芯片，所述插件包括布線層和通孔柱層，其中所述通孔柱層包括嵌入在介電材料中的通孔柱，所述通孔柱為具有基本恒定截面的實心柱體，所述介電材料包括在聚合物樹脂中的玻璃纖維，並且所述芯片和所述布線層嵌入在第二介電材料層中，所述第二介電材料層包覆所述芯片和所述布線層。
  2. 如請求項1所述的電子芯片封裝，還包括在所述通孔柱層的與所述布線層相反側上的金屬犧牲基底。
  3. 如請求項1所述的電子芯片封裝，其中所述通孔柱層中的至少一個通孔柱具有非圓柱形狀，其特征在于所述至少一個通孔柱的X-Y平面內的長尺寸是X-Y平面內的短尺寸的至少3倍長度。
  4. 如請求項1所述的電子芯片封裝，其中所述插件的底面包括被所述介電材料包圍的所述通孔柱的銅端部，使得所述通孔柱的銅端部與所述介電材料齊平。
  5. 如請求項1所述的電子芯片封裝，其中所述插件的底面包括被所述介電材料包圍的所述通孔柱的銅端部，使得所述通孔柱的銅端部相對于所述介電材料凹陷至多5微米。
  6. 如請求項1所述的電子芯片封裝，其中所述通孔層還包括銅通孔柱和覆蓋遠離所述布線層的所述通孔柱的端部的阻擋金屬層，使得所述插件的底面包括通孔柱端部，所述通孔柱端部包括被所述介電材料包圍的阻擋金屬層，使得所述通孔柱的端部的阻擋金屬層與所述介電材料齊平。
  7. 如請求項6所述的電子芯片封裝，其中所述阻擋金屬層選自鎳、金、錫、鉛、鈀、銀及其組合。
  8. 如請求項7所述的電子芯片封裝，其中所述阻擋金屬層具有1微米至10微米範圍的厚度。
  9. 如請求項1所述的電子芯片封裝，其中所述至少一個芯片設置為倒裝芯片，其通過凸點陣列接合至所述布線層。
  10. 如請求項9所述的電子芯片封裝，其中所述第二介電材料層是玻璃纖維增強聚合物。
  11. 如請求項1所述的電子芯片封裝，其中所述至少一個芯片通過引線接合與所述布線層接合，並且所述第二介電材料層是模塑料。
  12. 如請求項1所述的電子芯片封裝，其中包圍所述通孔柱的所述第一介電材料層包括第一聚合物樹脂，並且包圍所述布線層和所述至少一個芯片的所述第二介電材料層包括第二聚合物樹脂，其中所述第一聚合物樹脂不同于所述第二聚合物樹脂。
  13. 如請求項1所述的電子芯片封裝，其中包圍所述通孔柱的所述第一介電材料層包括無機填料。
  14. 如請求項1所述的電子芯片封裝，其中包圍所述通孔柱的所述第一介電材料層的聚合物樹脂選自聚酰亞胺、環氧樹脂、雙馬來酰亞胺/三嗪樹脂、聚苯醚及其共混物。
  15. 一種制造電子芯片封裝的方法，包括以下步驟：(a)選擇犧牲基板；(b)在所述犧牲基板上沈積蝕刻阻擋層；(c)鍍覆通孔柱層；(d)用介電材料層壓所述通孔柱層；(e)減薄和平坦化該介電材料層；(f)在所述通孔層上鍍覆布線特征層；(g)連接至少一個芯片；(h)用第二介電材料包覆所述至少一個芯片和布線特征結構；(i)移除所述犧牲基板，和(j)移除所述蝕刻阻擋層。
  16. 如請求項15所述的方法，其中步驟(g)包括將所述至少一個芯片引線接合至所述布線特征結構，並且步驟(h)包括用模塑料包覆。
  17. 如請求項15所述的方法，其中步驟(g)包括將所述至少一個芯片利用凸點陣列倒裝芯片接合至所述布線特征結構。
  18. 如請求項17所述的方法，其中步驟(h)包括用玻璃纖維聚合物預浸料進行包覆。
  19. 如請求項15所述的方法，其中所述犧牲基板包括可剝離銅基板、離型層和超薄銅箔，並且移除所述犧牲基板的步驟(i)包括剝除所述可剝離銅基板並蝕刻掉剩余的銅箔。
  20. 如請求項15所述的方法，還包括步驟(k)：通過移除所述蝕刻阻擋層以暴露出堆疊體外表面上的通孔端部並對所述通孔端部施加端子來端接所述基板。
  21. 如請求項15所述的方法，其中步驟(b)的所述蝕刻阻擋層沈積的厚度為0.1微米至數十微米範圍，並且步驟(b)的所述蝕刻阻擋層：包括選自鉭、鎢、鈦、鈦-鉭合金、鈦-鎢合金、鎳、錫、鉛和錫-鉛合金中的金屬，並且所述沈積包括濺射，或包括選自鎳、錫、鉛和錫/鉛合金中的金屬，並且所述沈積通過選自電鍍和化學鍍的工藝進行。
  22. 如請求項21所述的方法，其中鍍覆通孔柱層的步驟(c)包括通過以下子步驟來圖案鍍覆所述通孔柱層：敷設光刻膠層；在所述光刻膠層中顯影出通孔圖案；在所述圖案中鍍銅；和剝除所述光刻膠層以留下直立的通孔。
  23. 如請求項21所述的方法，其中鍍覆通孔柱層的步驟(c)包括沈積端子材料和在所述端子材料上構建通孔柱。
  24. 如請求項23所述的方法，其中所述端子材料包括錫、錫-鉛合金、金、銀和鈀中的至少其一。
  25. 如請求項15所述的方法，其中鍍覆通孔柱層的步驟(c)包括通過以下子步驟來面板鍍覆所述通孔柱層：面板鍍覆連續銅層；在所述連續銅層上沈積光刻膠層；在所述光刻膠層中顯影出通孔圖案；蝕刻掉過量的銅以留下所述圖案；和剝除已顯影的光刻膠以留下直立的通孔。
  26. 如請求項15所述的方法，其中所述第一介電材料包括聚合物樹脂，其選自聚四氟乙烯、聚四氟乙烯衍生物、雙馬來酰亞胺三嗪樹脂、環氧樹脂、聚酰亞胺樹脂、聚苯醚及其混合物。
  27. 如請求項26所述的方法，其中所述第一介電材料還包括以下至少其一：(a)無機顆粒填料，其平均粒徑為0.5微米至30微米，並且顆粒含量為15wt%-30wt%；(b)纖維，其選自有機纖維和玻璃纖維，所述纖維排列成選自交叉複合排列、織造氈和隨機取向短纖維的排列。
  28. 如請求項15所述的方法，其中用介電材料層層壓通孔柱層的步驟(d)包括在所述通孔層上施加預浸料以及通過熱壓層壓所述預浸料進行固化，所述預浸料包括在基質中的玻璃纖維，所述基質選自聚酰亞胺、環氧樹脂或雙馬來酰亞胺/三嗪樹脂、聚苯醚或其混合物。
  29. 如請求項15所述的方法，其中所述第二介電材料包括聚合物樹脂，所述聚合物樹脂選自聚四氟乙烯、聚四氟乙烯衍生物、雙馬來酰亞胺三嗪樹脂、環氧樹脂、聚酰亞胺樹脂、聚苯醚及其混合物。
  30. 如請求項29所述的方法，其中所述第二介電材料還包括以下至少其一：(a)無機顆粒填料，其平均粒徑為0.5微米至30微米，顆粒含量為15wt%-30wt%；(b)纖維，其選自有機纖維和玻璃纖維，所述纖維排列成選自交叉複合排列、織造氈和隨機取向短纖維的排列。
  31. 如請求項15所述的方法，其中用介電材料層壓通孔柱層的步驟(h)包括在所述芯片和所述布線層上施加預浸料以及通過熱壓層壓所述預浸料進行固化，所述預浸料包括在基質中的玻璃纖維，所述基質選自聚酰亞胺、環氧樹脂或雙馬來酰亞胺/三嗪樹脂、聚苯醚或其混合物。
  32. 如請求項15所述的方法，其中減薄和平坦化所述介電材料層的步驟(e)選自幹蝕刻、機械研磨、化學機械抛光及其組合及其兩階段過程。
  33. 如請求項15所述的方法，其中在所述通孔層上鍍覆布線特征層的步驟(f)包括：(i)在所述介電材料層上面板鍍覆銅，在其上敷設光刻膠層，顯影出布線特征層的正性圖案，選擇性地蝕刻掉過量的銅以留下所述布線特征層，以及剝除所述光刻膠層；或(ii)敷設光刻膠層，顯影出溝槽圖案，在所述溝槽中圖案鍍覆布線特征層，以及剝除所述光刻膠層。
  34. 如請求項33所述的方法，其中步驟(f)還包括在減薄的所述介電材料層上沈積粘附金屬層的預先步驟。
  35. 如請求項34所述的方法，其中所述粘附金屬層選自鈦、鉻和鎳-鉻合金。
  36. 如請求項15所述的方法，其中連接所述芯片的步驟(g)包括施加焊劑。
  37. 如請求項15所述的方法，其中將所述芯片連接至所述布線特征結構的步驟(g)包括將金、鋁或銅導線從所述芯片延伸至所述布線特征結構。
  38. 如請求項15所述的方法，其中移除所述犧牲基板的步驟(i)包括蝕刻掉銅。
  39. 如請求項15所述的方法，其中移除所述犧牲基板的步驟(i)包括剝除第一銅層和蝕刻掉剩余的銅。
  40. 如請求項39所述的方法，其中移除所述犧牲基板的步驟(i)采用濕蝕刻過程，並且利用在步驟(b)中制造的所述蝕刻阻擋層作為蝕刻停止層。
  41. 如請求項40所述的方法，其中在步驟(b)中制造的所述蝕刻阻擋層包括鉭，並且用于蝕刻掉所述犧牲基板的步驟(i)中的蝕刻過程包括將所述犧牲基板暴露于升高溫度下的氫氧化銨溶液中。
  42. 如請求項15所述的方法，其中所述犧牲基板包括覆銅層壓板。
  43. 如請求項15所述的方法，其中在步驟(b)中制造的所述蝕刻阻擋層選自鉭、鈦和鎢以及鈦-鎢合金，並且移除蝕刻阻擋層的步驟(j)包括使用CF4和氬氣的混合物的等離子體蝕刻。
  44. 如請求項15所述的方法，其中在步驟(b)中制造的所述蝕刻阻擋層選自鉭、鈦和鎢以及鈦-鎢合金，並且移除蝕刻阻擋層的步驟(j)包括使用CF4和氧氣的混合物的等離子體蝕刻。
  45. 如請求項15所述的方法，還包括對所述通孔的暴露端部施加最終塗層，所述塗層選自鎳、金、錫、鉛、銀、鈀及其合金以及有機防鏽面層。
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