CN103871998B - 单层无芯基板 - Google Patents

单层无芯基板 Download PDF

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Publication number
CN103871998B
CN103871998B CN201310157191.8A CN201310157191A CN103871998B CN 103871998 B CN103871998 B CN 103871998B CN 201310157191 A CN201310157191 A CN 201310157191A CN 103871998 B CN103871998 B CN 103871998B
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Prior art keywords
layer
methods
copper
hole post
chip
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CN201310157191.8A
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CN103871998A (zh
Inventor
卓尔·赫尔维茨
陈先明
黄士辅
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Zhuhai Yueya Semiconductor Co Ltd
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Zhuhai Advanced Chip Carriers and Electronic Substrate Solutions Technologies Co Ltd
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Abstract

本发明提供一种电子芯片封装，其包括与插件的布线层接合的至少一个芯片，所述插件包括布线层和通孔柱层，其中所述通孔柱层被第一介电材料层包围，所述第一介电材料层包括在聚合物树脂中的玻璃纤维，其中所述电子芯片封装还包括包覆所述至少一个芯片、所述布线层和导线的第二介电材料层。本发明还提供一种制造该电子芯片封装的方法。

Description

单层无芯基板
技术领域
本发明涉及电子芯片封装及其制造方法。
背景技术
消费电子产品如计算机和电信装置包括集成电路芯片。这些电子产品需要IC基板作为芯片封装部件。
IC基板需要具有高平坦度并且具有刚性和抗翘曲性以确保与下方基板的良好接触。这种支撑结构的一般要求是可靠性以及合适的电气性能、薄度、刚性、平坦性、散热性好和有竞争力的单价。
已确立的相对廉价并且实现IC电路与外界通讯的常用芯片封装类型是引线框架。引线框架使用延伸至外壳之外的金属引线。引线框架技术可追溯到早期的DIP芯片，但其仍广泛用于许多封装类型。
引线框架用作IC封装的“骨架”，在管芯组装为成品的过程中为管芯提供机械支撑。引线框架由管芯附着的管芯焊盘和引线构成，所述引线用作向外电连接至外界的手段。通过引线接合或通过带式自动键合，将管芯经由导线连接至引线。
在引线框架与连接导线相连后，使用作为塑料保护材料的模塑料覆盖管芯或芯片。
用于制造更先进多层基板的其它技术包括用于连接介电材料内的焊盘或特征结构的层。提供穿过介电材料的通孔来连接不同层中的特征结构。
一种制造这种通孔的方法是钻填法，其中通常利用激光来钻孔穿过电介质，然后用导电材料例如铜来填充该孔，由此形成通孔。
一种制造通孔的替代方法是利用称为“图案镀覆”的技术在光刻胶形成的图案中沉积铜或其它金属。随后移除光刻胶，并用介电材料层压直立的通孔柱，所述介电材料优选是用以增强刚性的聚合物浸渍玻璃纤维毡预浸料。
在图案镀覆中，首先沉积种子层。然后在其上沉积光刻胶层，随后曝光形成图案，并且选择性移除该图案以制成暴露出种子层的沟槽。通过将铜沉积到光刻胶沟槽中来形成通孔柱。然后移除剩余的光刻胶，蚀刻掉种子层，并在其上及其周围层压通常为聚合物浸渍玻璃纤维毡的介电材料，以包围所述通孔柱。然后，可以使用各种技术和工艺来减薄所述介电材料，将其平坦化并暴露出所述通孔柱顶部以允许通过通孔柱导电连接到底平面或基准面，用于在其上构建下一金属层。可在其上通过重复该过程来沉积后续的金属导体层和通孔柱，以构建所需的多层结构。
在一个替代但紧密关联的技术即下文所称的“面板镀覆”中，将连续的金属或合金层沉积到基板上。在其顶部沉积光刻胶层，并在其中显影出图案。剥除显影光刻胶的图案，选择性地暴露出其下的金属，该金属可随后被蚀刻掉。未显影的光刻胶保护其下方的金属不被蚀刻掉，并留下直立的特征结构和通孔的图案。剥除未显影光刻胶后，在所述直立的铜特征结构和/或通孔柱上及周围层压介电材料，如聚合物浸渍玻璃纤维毡。
通过诸如前述的图案镀覆或面板镀覆方法创建的通孔层通常被称为“通孔柱”。可以利用类似的技术制造特征层。
一种制造高密度互连的灵活技术是构建由介电基质中的金属通孔或特征结构构成的图案镀覆或面板镀覆的多层结构。所述金属可以是铜，电介质可以是纤维增强聚合物，通常使用的是具有高玻璃化转变温度（Tg）的聚合物，例如聚酰亚胺。这些互连可以是有芯的或无芯的，并可包括用于堆叠元件的空腔。它们可具有奇数或偶数层。实现技术描述在授予Amitec-Advanced Multilayer Interconnect Technologies Ltd.的现有专利中。例如，赫尔维茨（Hurwitz）等人的题为“高级多层无芯支撑结构及其制造方法（Advancedmultilayer coreless support structures and method for their fabrication）”的美国专利US7,682,972描述了一种制造包括在电介质中的通孔阵列的独立膜的方法，所述膜用作构建优异的电子支撑结构的前体。该方法包括以下步骤：在包围牺牲载体的电介质中制造导电通孔膜，和将所述膜与牺牲载体分离以形成独立的层压阵列。基于该独立膜的电子基板可通过将所述层压阵列减薄和平坦化，随后端接通孔来形成。该公报通过引用全文并入本文。
赫尔维茨（Hurwitz）等人的题为“集成电路支撑结构及其制造方法（integratedcircuit support structures and their fabrication）”的美国专利US7,635,641描述了一种制造电子基板的方法，包括以下步骤：(A)选择第一基础层；(B)将蚀刻阻挡层沉积到所述第一基础层上；(C)形成交替的导电层和绝缘层的第一半堆叠体，所述导电层通过贯穿绝缘层的通孔而互连；(D)将第二基础层涂覆到所述第一半堆叠体上；(E)将光刻胶保护涂层涂覆到第二基础层上；(F)蚀刻掉所述第一基础层；(G)移除所述光刻胶保护涂层；(H)移除所述第一蚀刻阻挡层；(I)形成交替的导电层和绝缘层的第二半堆叠体，导电层通过贯穿绝缘层的通孔而互连；其中所述第二半堆叠体具有与第一半堆叠体基本对称的构造；(J)将绝缘层涂覆到交替的导电层和绝缘层的所述第二半堆叠体上；(K)移除所述第二基础层，以及，(L)通过将通孔末端暴露在所述堆叠体的外表面上并对其施加端子来端接基板。该公报通过引用全文并入本文。
多层基板能够实现更高密度的互连并用于甚至更复杂的IC芯片。它们远比简单单层引线框架更为昂贵，对于许多电子应用来说，更经济的引线框架才是适合的。
然而，引线框架技术存在许多局限。芯片通过引线接合连接至引线框架，连接导线越长，形成断路并导致故障的导线断裂危险就越大。此外，装在一起的导线越接近，短路的可能性就越大。
介电材料内通孔柱的方法适用于多层基板，但通常因太过易损而不用于单层基板中，应当认识到翘曲和弯曲导致接触不良、不可靠和短路。
本发明的实施方案解决了这些问题。
发明内容
本发明的实施方案涉及提供新型芯片封装解决方案。
一种电子芯片封装包括与插件的布线层接合的至少一个芯片，所述插件包括布线层和通孔柱层，其中所述通孔柱层被介电材料包围，所述介电材料包括在聚合物树脂中的玻璃纤维，并且所述芯片和所述布线层嵌入在第二介电材料层中，所述第二介电材料层包覆所述芯片和所述布线层。
在一些实施方案中，所述电子芯片封装还包括在所述通孔柱层的与所述布线层相反侧上的金属牺牲基底。
在一些实施方案中，所述通孔柱层中的至少一个通孔柱具有非圆柱形状，其特征在于X-Y平面内的长尺寸是X-Y平面内的短尺寸的至少3倍长度。
在一些实施方案中，所述插件的底面包括被所述介电材料包围的所述通孔柱的铜端部，使得所述通孔柱的铜端部与该介电材料齐平。
在其它实施方案中，所述插件的底面包括被所述介电材料包围的所述通孔柱的铜端部，使得所述通孔柱的铜端部相对于该介电材料凹陷至多5微米。
在其它实施方案中，所述通孔层还包括铜通孔柱和覆盖远离所述布线层的所述通孔柱的端部的阻挡金属层，使得所述插件的底面包括通孔柱端部，所述通孔柱端部包括被介电材料包围的阻挡金属，使得所述通孔柱的阻挡金属端部与该介电材料齐平。
通常，所述阻挡金属层选自镍、金、锡、铅、钯、银及其组合。
在一些实施方案中，所述通孔的阻挡金属层具有1微米至10微米范围的厚度。
在一些实施方案中，所述至少一个芯片设置为倒装芯片，其通过凸点阵列接合至所述布线层。
在一些这样的实施方案中，所述第二介电材料层是玻璃纤维增强聚合物。
通常，所述至少一个芯片通过引线接合与所述布线层接合，并且所述第二介电材料层是模塑料。
任选地，包围所述通孔柱的第一介电材料层包括第一聚合物树脂，包围所述布线层和所述至少一个芯片的所述第二介电材料层包括第二聚合物树脂，其中所述第一聚合物树脂不同于所述第二聚合物树脂。
任选地，包围所述通孔柱的所述第一介电材料层包括无机填料。
任选地，包围所述通孔柱的所述第一介电材料层的聚合物树脂选自聚酰亚胺、环氧树脂、BT（双马来酰亚胺/三嗪树脂）、聚苯醚（PPE或PPO）及其共混物。
本发明的第二方面涉及提供一种制造电子芯片封装的方法，包括以下步骤：
(a)选择牺牲基板；
(b)在所述牺牲基板上沉积蚀刻阻挡层；
(c)镀覆通孔柱层；
(d)用介电材料层压所述通孔柱层；
(e)减薄和平坦化介电材料层；
(f)在所述通孔层上镀覆布线特征层；
(g)连接至少一个芯片；
(h)用第二介电材料包覆所述至少一个芯片和布线特征结构；
(i)移除所述牺牲基板，和
(j)移除所述蚀刻阻挡层。
在一些实施方案中，步骤(g)包括将所述至少一个芯片引线接合至所述布线特征结构，步骤(h)包括用模塑料包覆所述至少一个芯片和布线特征结构。
在一些实施方案中，步骤(g)包括将所述至少一个芯片利用凸点阵列倒装芯片接合至所述布线特征结构。
任选地，在这样的实施方案中，步骤(h)包括用玻璃纤维聚合物预浸料进行包覆。
在一些实施方案中，所述牺牲基板包括可剥离铜基板、离型层和超薄铜箔，移除牺牲基板的步骤(i)包括剥除所述可剥离铜基板并蚀刻掉剩余的铜箔。
在一些实施方案中，所述牺牲基板包括覆铜层压板，移除牺牲基板的步骤(j)包括蚀刻掉铜。
在一些实施方案中，所述方法还包括步骤(k)：通过移除所述蚀刻阻挡层以暴露出堆叠体外表面上的通孔端部并对所述通孔端部施加端子来端接所述基板。
在一些实施方案中，步骤(b)的阻挡层的沉积厚度为0.1微米至数十微米范围，并且步骤(b)的蚀刻阻挡层：
●包括选自钽、钨、钛、钛-钽合金、钛-钨合金、镍、锡、铅和锡-铅合金中的金属，并且所述沉积包括溅射，或
●包括选自镍、锡、铅和锡/铅合金中的金属，并且所述沉积通过选自电镀和化学镀的工艺进行。
在一些实施方案中，镀覆通孔柱层的步骤(c)包括通过以下子步骤来图案镀覆所述通孔柱层：
●敷设光刻胶层；
●在所述光刻胶层中显影出通孔图案；
●在所述图案中镀铜；和
●剥除所述光刻胶层以留下直立的所述通孔。
在一些实施方案中，镀覆通孔柱层的步骤(c)包括沉积端子材料和在所述端子材料上构建通孔柱。
在一些实施方案中，所述端子材料包括锡、锡-铅合金、金、银和钯中的至少其一。
在一些实施方案中，镀覆通孔柱层的步骤(c)包括通过以下子步骤来面板镀覆所述通孔柱层：
●面板镀覆连续铜层；
●在所述连续铜层上沉积光刻胶层；
●在所述光刻胶层中显影出通孔图案；
●蚀刻掉过量的铜以留下所述图案；和
●剥除已显影的光刻胶层，留下直立的所述通孔。
在一些实施方案中，第一介电材料层包括聚合物树脂，选自聚四氟乙烯、聚四氟乙烯衍生物、双马来酰亚胺三嗪树脂、环氧树脂、聚酰亚胺树脂、聚苯醚（PPE或PPO）及其混合物。
在一些实施方案中，第一介电材料层还包括以下至少其一：
a)无机颗粒填料，其平均粒径为0.5微米至30微米，颗粒含量为15wt%-30wt%；
b)纤维，选自有机纤维和玻璃纤维，其排列成选自交叉复合排列、织造毡和随机取向短纤维的排列。
在一些实施方案中，用介电材料层层压通孔柱层的步骤(d)包括在通孔上施加预浸料以及通过热压机层压预浸料进行固化，所述预浸料包括在基质中的玻璃纤维，所述基质选自聚酰亚胺、环氧树脂或BT（双马来酰亚胺/三嗪树脂）、聚苯醚（PPE或PPO）或其混合物。
在一些实施方案中，第二介电材料层包括聚合物树脂，其选自聚四氟乙烯、聚四氟乙烯衍生物、双马来酰亚胺三嗪树脂、环氧树脂、聚酰亚胺树脂、聚苯醚（PPE或PPO）及其混合物。
在一些实施方案中，第二介电材料层还包括以下至少其一：
a)无机颗粒填料，其平均粒径为0.5微米至30微米，颗粒含量为15wt%-30wt%；
b)纤维，选自有机纤维和玻璃纤维，其排列成选自交叉复合排列、织造毡和随机取向短纤维的排列。
在一些实施方案中，用介电材料层层压通孔柱层的步骤(h)包括在芯片和布线层上施加预浸料以及通过热压层压预浸料进行固化，所述预浸料包括在基质中的玻璃纤维，所述基质选自聚酰亚胺、环氧树脂或BT（双马来酰亚胺/三嗪）、聚苯醚（PPE或PPO）或其混合物。
在一些实施方案中，减薄和平坦化介电材料层的步骤(e)包括选自干蚀刻、机械研磨、化学机械抛光（CMP）、其组合及其两阶段过程的工艺。
在一些实施方案中，在通孔层上镀覆布线特征层的步骤(f)包括：
(i)在介电层上面板镀覆铜，在其上敷设光刻胶层，显影出布线特征层的正性图案，选择性地蚀刻掉过量的铜以留下所述布线特征层，以及剥除所述光刻胶层；或
(ii)敷设光刻胶层，显影出沟槽图案，在所述沟槽中图案镀覆布线特征层，以及剥除所述光刻胶层。
在一些实施方案中，步骤(f)还包括在经减薄的介电材料层上沉积粘附金属层的预先步骤。
在一些实施方案中，所述粘附金属层选自钛、铬、钨、镍-铬合金和钛-钨合金。
在一些实施方案中，连接至少一个芯片的步骤(g)包括施加焊剂。
在一些实施方案中，将至少一个芯片连接至布线特征层的步骤(g)包括将金、铝或铜导线从所述芯片延伸至所述布线特征层。
在一些实施方案中，移除牺牲基板的步骤(i)包括蚀刻掉铜。
在一些实施方案中，移除牺牲基板的步骤(i)包括剥除第一铜层和蚀刻掉剩余的铜。
在一些实施方案中，移除牺牲基板的步骤(i)采用湿蚀刻工艺，并且利用在步骤(b)中制造的蚀刻阻挡层作为蚀刻停止层。
在一些实施方案中，在步骤(b)中制造的蚀刻阻挡层包括钽，用于蚀刻掉牺牲基板的步骤(i)中的蚀刻过程包括将牺牲基板暴露于升高温度下的氢氧化铵溶液中。
在一些实施方案中，在步骤(b)中制造的蚀刻阻挡层选自钽、钛和钨以及钛-钨合金，并且移除蚀刻阻挡层的步骤(j)包括使用CF4和氩气的混合物的等离子体蚀刻，其中所述混合物通常具有的CF4与氩气之比为1:1至3:1。
在一些实施方案中，在步骤(b)中制造的蚀刻阻挡层选自钽、钛和钨以及钛-钨合金，并且移除蚀刻阻挡层的步骤(j)包括使用CF4和氧气的混合物的等离子体蚀刻。
在一些实施方案中，所述方法还包括对通孔的暴露端部施加最终涂层，所述涂层选自镍、金、锡、铅、银、钯及其合金以及有机防锈面层。
术语微米或μm是指微米或10-6米。
附图说明
为了更好地理解本发明并示出本发明的实施方式，纯粹以举例的方式参照附图。
具体参照附图时，必须强调的是特定的图示是示例性的并且目的仅在于说明性地讨论本发明的优选实施方案，并且基于提供被认为是对于本发明的原理和概念方面的描述最有用和最易于理解的图示的原因而被呈现。就此而言，没有试图将本发明的结构细节以超出对本发明基本理解所必需的详细程度来图示；参照附图的说明使本领域技术人员认识到本发明的几种形式可如何实际体现出来。在附图中：
图1是根据本发明的一个实施方案的电子芯片封装的简化截面图；
图2是根据本发明的第二实施方案的电子芯片封装的简化截面图；
图3是根据本发明的第三实施方案的电子芯片封装的简化截面图；
图4是根据本发明的第四实施方案的电子芯片封装的简化截面图，示出能够通过接点栅格阵列（LGA）或球形栅格阵列（BGA）实现芯片与基板连接的插件；
图5是示出本文描述的电子芯片封装可如何制造的流程图；
各个附图中相同的参考数字和附图标记指示相同的要素。
具体实施方式
在以下说明中，涉及的是包括在介电基体中的金属通孔的支撑结构，特别是在聚合物基体中的铜通孔柱，所述聚合物基质例如是玻璃纤维增强的聚酰亚胺、环氧树脂或BT（双马来酰亚胺/三嗪树脂）、聚苯醚（PPE或PPO）或它们的共混物。
参照图1，示出超薄电子芯片封装的示意性截面图。超薄芯片封装100包括至少一个芯片110，所述芯片110通过铜布线特征层114连接至包围在介电材料116内的铜通孔柱112，所述介电材料116由玻璃纤维增强的聚合物基质构成。所述芯片110可以通过焊线118（通常是金导线）引线接合至布线特征层114，并且超薄芯片封装100还包括包覆芯片110、布线特征层114和焊线118的模塑料120。
超薄芯片封装100制造在通常为铜或铜合金的牺牲基板122上，仅在芯片110被接合到插件124即布线层114和通孔112上并且被模塑料120包覆后，才可以移除牺牲基板122。
利用这种独特的构造，即芯片110和模塑料120提供主体并由此为包括单层通孔112的极薄插件124提供刚性，可以实现非常薄的芯片封装。实际上，可以实现芯片尺寸封装（CSP）。这样的封装是对小外形集成电路（SOIC）、方形扁平无引脚封装（QFN）和两层芯片尺寸封装（2L CSP）的成本有效且高性能的替代。
如图所示，芯片110连接至经抛光和减薄的通孔层上。所公开的构造比多层基板更薄，但不适合非常高密度的大数量互连。然而，与常规的引线框架不同，利用布线层114可以提供短焊线118，并且避免易于折断的长焊线。而且，引线接合通常使用金线来实现，并且布线层是铜。因此，虽然实际的插件124往往比常规的引线框架更昂贵，但是在考虑到每个芯片110的全部封装成本时，这样的超薄芯片封装100可能是成本有效的。此外，应当认识到，两个以上的芯片110可以在常用插件124上并排安装。
在图2构造中，牺牲基板222包括市售的可剥离铜基板、离型层和超薄铜箔。Furukawa供应这种箔，商品名为F-DP和H-DP，具体参见Furukawa Review38,2010.http:// www.furukawa.co.jp/review/fr038/fr38_06.pdf。
使用这种膜能够剥离大多数基板222，并且只需要蚀刻掉相对薄的铜层，通常2-5微米的铜222，以暴露出在通孔柱112端部上的蚀刻阻挡层126。这可以在常规的芯片封装厂实现。作为替代方案，基板制造厂可将芯片110附着在插件124上并以目标垂直整合进行包覆。
另一候选的基板是覆铜层压板（CCL），例如广泛用于制造印刷电路板的CCL。
为了能够实现蚀刻掉铜基板而不损伤通孔柱端部，在一些实施方案中，通常是铜的通孔柱的沉积是以沉积抗蚀刻材料的阻挡层126开始的，所述阻挡层116例如是通过溅射沉积的钽、钨、钛、钛-钽合金、钛-钨合金、镍、锡、铅或锡-铅合金，或者是通过电镀或化学镀沉积的镍、锡、铅或锡-铅合金。如果没有这种蚀刻阻挡层，则通孔柱自身的前几个微米通常是3-5微米被蚀刻掉，导致通孔柱端部相对于介电材料凹陷。虽然当芯片封装附着至印刷电路板（PCB）时，凹陷的通孔柱需要更多的焊剂或其它连接材料来提供电连接，但是增加阻挡层增加了单位成本，因此有时候将其省去。
本发明的构造预期比两层芯片尺寸封装（CSP）具有更好的热性能、更薄以及更低的单位成本，并且比微型引线框架具有更好的电气性能和总体更低的成本。
参照图3，示出一种经过适当修改的变化方案的支撑结构300，其中芯片310以倒装芯片构造安装并且通过球形栅格阵列318连接至插件324的布线特征结构314上。在该变化方案的支撑结构中，一个或更多个芯片310可采用玻璃纤维聚合物预浸料320而不是模塑料120进行包覆。
参照图4，为了将芯片110或多芯片阵列以扇入（fan-in）型排列连接至基板，可以采用接点栅格阵列（LGA）或球形栅格阵列（BGA）。铜通孔412等距间隔排列成矩形格栅，如截面图所示，其中一列显示为等距间隔的通孔柱412队列。布线层414缩短了铜线418需要跨越的距离，并且能够使通孔柱412位于芯片110下方使用。以此方式，芯片可以引线接合（或倒装芯片可以采用凸点阵列连接）至插件424，该插件424连接至接点栅格阵列。
在图1-3中，没有示出阻焊层以保持附图简洁。然而，应当认识到可以使用阻焊层来隔离布线层的端部。
参照图5，一种制造电子芯片封装的方法包括以下步骤：选择牺牲基板122—步骤(a)。基板122通常是铜或铜合金，并且可以是简单的铜片或市售的可剥离铜基板222，如下所述。
接着，在所述牺牲基板上沉积蚀刻阻挡层126—步骤(b)。通常，蚀刻阻挡层的沉积厚度为0.1微米至数十微米的范围，并且可包括溅射沉积的钽、钨、钛、钛-钽合金、钛-钨合金、镍、锡、铅或锡-铅合金或者电镀或化学镀沉积的镍、锡、铅或锡-铅合金。
然后，在蚀刻阻挡层126上镀覆通孔柱层112—步骤(c)。
在一个变化方案的制造方法中，镀覆通孔柱层的步骤(c)包括通过以下子步骤图案镀覆所述通孔柱层：
(i)敷设光刻胶层；
(ii)在所述光刻胶层内显影出通孔112的图案；
(iii)在所述图案内镀覆铜通孔112；和
(iv)剥除所述光刻胶层，保留下直立的通孔柱112。
任选地，镀覆通孔柱层的步骤(c)包括在所述图案中沉积端子材料128，例如镍、金、锡、铅、锡-铅合金、银、钯或其合金，并且在所述端子材料上通过在其上电镀铜来构建铜通孔柱。
在另一变化方案的制造方法中，镀覆通孔柱层的步骤(c)包括通过以下子步骤面板镀覆所述通孔柱层：
●面板镀覆连续铜层；
●在所述连续铜层上沉积光刻胶层；
●在所述光刻胶层内显影出通孔图案；
●蚀刻掉过量的铜以留下直立的通孔柱112；和
●剥除已显影的光刻胶，留下直立的通孔柱112。
应该认识到，与特征在于通孔基本为圆柱形并且所有通孔均相同的钻填制通孔技术不同，本发明的制造方法采用镀覆技术，其中通孔柱是被镀覆到光刻胶图案内或者从面板镀覆层中蚀刻掉周围材料而留下通孔柱，这在制造上具有无法比拟的灵活性，并且部分或全部通孔自身可提供平面布线。这样的通孔柱可以条状的，并且具有一个明显更长的平面内尺寸，其可能是其它平面内尺寸的3倍以上长度。
接着，用介电材料116层压通孔柱层112—步骤(d)。介电材料116可以选自聚四氟乙烯、聚四氟乙烯衍生物、双马来酰亚胺三嗪树脂、环氧树脂、聚酰亚胺树脂、聚苯醚（PPE或PPO）及其混合物和共混物。
通常，介电材料116还包括以下至少其一：
(a)无机颗粒填料，平均粒径为0.5微米至30微米，颗粒含量为15wt%-30wt%；
(b)纤维，选自有机纤维和玻璃纤维，其排列成选自交叉复合排列、织造毡和随机取向短纤维的排列。
在一些实施方案中，用介电材料116层压通孔柱层112的步骤(d)包括施加包括基质中玻璃纤维的预浸料，所述基质选自聚酰亚胺、环氧树脂或BT（双马来酰亚胺/三嗪树脂）、聚苯醚（PPE或PPO）或其共混物，然后通过热压层压该预浸料进行固化。
通过在通孔柱上层压预浸料，基板可具有刚性和抗翘曲性。选择的聚合物具有对铜柱的良好粘附性。
接着，对介电层116进行减薄和平坦化以暴露出通孔柱112的端部—步骤(e)。在各种工艺路线中，介电层的减薄和平坦化通过干蚀刻、机械研磨、化学机械抛光（CMP）及其组合以及其两阶段工艺来实现。
然后，在通孔柱层112上镀覆布线特征层114。
在通孔柱层112上镀覆布线特征层114可包括：
(i)在所述介电层上面板镀覆铜，在其上敷设光刻胶层，显影出布线特征结构的正性图案，选择性地蚀刻掉过量的铜以留下布线特征结构114，以及剥除所述光刻胶层；或
(ii)敷设光刻胶层，显影出沟槽图案，在所述沟槽中图案镀覆布线特征结构112，以及剥除所述光刻胶层。
为了有助于布线特征结构粘附至下方的介电材料116，可以先在减薄的介电材料上沉积粘附金属层例如钛、铬或镍/铬合金，所述粘附金属层通常具有0.04微米至0.1微米范围的厚度。通过先沉积种子层而在其上沉积铜，这通常通过溅射或化学镀进行，接着通过电镀在其上构建铜层。
然后，将芯片110连接至介电层116—步骤(g)。在一些实施方案中，将芯片110连接至介电层116的步骤(g)包括施加焊剂。这可以用于简单的机械接合，或者参照图3，用于倒装芯片构造中，采取球形栅格阵列318将芯片110电连接至基板（这不能采用常规的引线框架进行）。
利用采取球形栅格阵列318的倒装芯片设置，可以用预浸料320而不是用传统的模塑料来层压芯片110和布线层312。这提供更薄且更刚性的产品。
在其它实施方案中，如图1和2所示，芯片110连接至插件124是通过利用从芯片110至布线特征结构114延伸的金（或较不常用的铝或铜）导线将芯片110引线接合至布线特征结构114来进行的。
由于布线特征结构，使得所需的焊线118长度可以少于常规引线框架排列所需的焊线长度。这显著增加了芯片封装的可靠性并且由于需要较少的金导线从而通常降低总成本。
接着，用模塑料120包覆芯片110、布线特征结构114和焊线118—步骤(h)。如果采用球形栅格阵列（图3中的318）来连接倒装芯片310至插件324，则可以使用具有增强纤维的介电材料，例如纤维在基质中的预浸料320。这比模塑料120具有更好的刚性，但是这不能与引线接合一同使用，因为玻璃纤维会破坏金焊线118。
在使用芯片110和模塑料20（纤维增强电介质320）来使结构100（300）具有刚性后，可以移除牺牲基板112—步骤(i)。这种在移除牺牲基板112之前施加芯片110和模塑料120的工艺路线是非常革命性的，因为这需要将未完成的基板供应至封装装配机或在基板装配机中加入芯片110。当采用球形栅格阵列时，使用介电预浸料320替代模塑料120进一步增加了革命性的进展。
在一些实施方案中，移除牺牲基板的步骤(i)包括剥除可剥离铜基板222和蚀刻掉剩余的铜箔。
在一些实施方案中，蚀刻掉牺牲基板112/222的步骤(i)采用湿蚀刻过程，并且使用在步骤(b)中制造的蚀刻阻挡层126作为蚀刻停止层。
在一个制造路线中，在步骤(b)中制造的蚀刻阻挡层126包括钽，并且由于蚀刻掉牺牲基板的步骤(i)中的蚀刻过程包括将牺牲基板暴露于升高温度的氢氧化铵溶液中。作为替代方案，可以使用氯化铜作为蚀刻剂。
然后，可以利用合适的蚀刻剂来移除蚀刻阻挡层—步骤(j)。
在一个制造路线中，在步骤(b)中制造的蚀刻阻挡层126选自钽、钛和钨，并且移除蚀刻阻挡层的步骤(j)包括使用CF4和氩气的混合物的等离子体蚀刻，其中该混合物通常具有CF4与氩气之比为1:1至3:1。在另一实施例中，蚀刻掉蚀刻阻挡层的方法通过使用比例为93:7的CF4:O2的等离子体蚀刻来进行。
在移除牺牲基板112（222）之后，如果蚀刻阻挡层126不适合用作端子，则任选地所述方法还包括移除蚀刻阻挡层126—步骤(j)以暴露出通孔柱122的端部，以及对通孔端部施加端子128—步骤(k)。
当在施加铜之前通过图案镀覆对蚀刻阻挡层126进行图案化时，其可以用于端子目的。然而，通常该方法还包括步骤(l)—对通孔112的暴露端部施加最终涂层，所述最终涂层选自镍、金、锡、铅、银、钯及其合金或其汞合金以及有机防锈面层。
由单通孔和布线层124一起构成的插件通常具有25至40微米厚度并且不能自支撑。但是，其可制造在牺牲基板112（222）上，例如约20微米厚的铜片上。传统上，插件是以完全完成的形式供应至芯片封装厂的。本发明的特征则在于将插件提供至基板上的芯片封装机或者基板制造商将芯片110连接至插件124（324），形成垂直整合（verticalintegration）并简化制造过程。
如上所述，芯片封装100（300）包含单个管芯或芯片，但是应该认识到两个管芯可以封装在一起。例如，存储器芯片和控制器可以并排设置在包括布线层和通孔层的插件上，通过球形栅格阵列318或通过引线接合118电连接至布线层312，或者一个芯片110利用倒装芯片技术连接而另一个芯片利用引线接合连接，然后可以用模塑料包覆基板124的芯片110和布线层312，或者如果两个芯片都是倒装芯片通过且行栅格阵列318连接至插件324，则可以通过在其上层压预浸料320进行包覆。
本文所述的新型封装技术与化学镀镍/化学镀钯/浸镀金（ENEPIG）端子技术兼容。
本领域技术人员将会认识到，本发明不限于上文中具体图示和描述的内容。而且，本发明的范围由所附权利要求限定，包括上文所述的各个技术特征的组合和子组合以及其变化和改进，本领域技术人员在阅读前述说明后将会预见到这样的组合、变化和改进。
在权利要求书中，术语“包括”及其变体例如“包含”、“含有”等是指所列举的组件被包括在内，但一般不排除其他组件。

Claims (43)

1.一种电子芯片封装，包括与插件的布线层接合的至少一个芯片，所述插件包括布线层和通孔柱层，其中所述通孔柱层包括嵌入在第一介电材料层中的通孔柱，所述第一介电材料层包括在聚合物树脂中的玻璃纤维，并且所述芯片和所述布线层嵌入在第二介电材料层中，所述第二介电材料层包覆所述芯片和所述布线层，使得：
1)所述插件的底面包括被包围或嵌入在所述第一介电材料层中的所述通孔柱的铜端部，使得所述通孔柱的铜端部与所述第一介电材料层齐平；或
2)所述插件的底面包括被包围或嵌入在所述第一介电材料层中的所述通孔柱的铜端部，使得所述通孔柱的铜端部相对于所述第一介电材料层凹陷至多5微米。
2.如权利要求1所述的电子芯片封装，还包括在所述通孔柱层的与所述布线层相反侧上的金属牺牲基底。
3.如权利要求1所述的电子芯片封装，其中所述通孔柱层中的至少一个通孔柱具有非圆柱形状，其特征在于所述至少一个通孔柱的X-Y平面内的长尺寸是X-Y平面内的短尺寸的至少3倍长度。
4.如权利要求1所述的电子芯片封装，其中所述通孔层还包括铜通孔柱和覆盖远离所述布线层的所述通孔柱的端部的阻挡金属层，使得所述插件的底面包括通孔柱端部，所述通孔柱端部包括被所述第一介电材料层包围的阻挡金属层，使得所述通孔柱的端部的阻挡金属层与所述第一介电材料层齐平。
5.如权利要求4所述的电子芯片封装，其中所述阻挡金属层选自镍、金、锡、铅、钯、银及其组合。
6.如权利要求5所述的电子芯片封装，其中所述阻挡金属层具有1微米至10微米范围的厚度。
7.如权利要求1所述的电子芯片封装，其中所述至少一个芯片设置为倒装芯片，其通过凸点阵列接合至所述布线层。
8.如权利要求7所述的电子芯片封装，其中所述第二介电材料层是玻璃纤维增强聚合物。
9.如权利要求7所述的电子芯片封装，其中所述至少一个芯片通过引线接合与所述布线层接合，并且所述第二介电材料层是模塑料。
10.如权利要求1所述的电子芯片封装，其中包围所述通孔柱的所述第一介电材料层包括第一聚合物树脂，并且包围所述布线层和所述至少一个芯片的所述第二介电材料层包括第二聚合物树脂，其中所述第一聚合物树脂不同于所述第二聚合物树脂。
11.如权利要求1所述的电子芯片封装，其中包围所述通孔柱的所述第一介电材料层包括无机填料。
12.如权利要求1所述的电子芯片封装，其中包围所述通孔柱的所述第一介电材料层的聚合物树脂选自聚酰亚胺、环氧树脂、双马来酰亚胺/三嗪树脂、聚苯醚及其共混物。
13.一种制造电子芯片封装的方法，包括以下步骤：
(a)选择牺牲基板；
(b)在所述牺牲基板上沉积蚀刻阻挡层；
(c)镀覆通孔柱层；
(d)用第一介电材料层压所述通孔柱层；
(e)减薄和平坦化该第一介电材料层；
(f)在所述通孔层上镀覆布线特征层；
(g)连接至少一个芯片；
(h)用第二介电材料包覆所述至少一个芯片和布线特征结构；
(i)移除所述牺牲基板，和
(j)移除所述蚀刻阻挡层。
14.如权利要求13所述的方法，其中步骤(g)包括将所述至少一个芯片引线接合至所述布线特征结构，并且步骤(h)包括用模塑料包覆。
15.如权利要求13所述的方法，其中步骤(g)包括将所述至少一个芯片利用凸点阵列倒装芯片接合至所述布线特征结构。
16.如权利要求15所述的方法，其中步骤(h)包括用玻璃纤维聚合物预浸料进行包覆。
17.如权利要求13所述的方法，其中所述牺牲基板包括可剥离铜基板、离型层和超薄铜箔，并且移除所述牺牲基板的步骤(i)包括剥除所述可剥离铜基板并蚀刻掉剩余的铜箔。
18.如权利要求13所述的方法，还包括步骤(k)：通过移除所述蚀刻阻挡层以暴露出堆叠体外表面上的通孔端部并对所述通孔端部施加端子来端接所述基板。
19.如权利要求13所述的方法，其中步骤(b)的所述蚀刻阻挡层沉积的厚度为0.1微米至数十微米范围，并且步骤(b)的所述蚀刻阻挡层：
包括选自钽、钨、钛、钛-钽合金、钛-钨合金、镍、锡、铅和锡-铅合金中的金属，并且所述沉积包括溅射，或
包括选自镍、锡、铅和锡/铅合金中的金属，并且所述沉积通过选自电镀和化学镀的工艺进行。
20.如权利要求19所述的方法，其中镀覆通孔柱层的步骤(c)包括通过以下子步骤来图案镀覆所述通孔柱层：
敷设光刻胶层；
在所述光刻胶层中显影出通孔图案；
在所述图案中镀铜；和
剥除所述光刻胶层以留下直立的通孔。
21.如权利要求19所述的方法，其中镀覆通孔柱层的步骤(c)包括沉积端子材料和在所述端子材料上构建通孔柱。
22.如权利要求21所述的方法，其中所述端子材料包括锡、锡-铅合金、金、银和钯中的至少其一。
23.如权利要求13所述的方法，其中镀覆通孔柱层的步骤(c)包括通过以下子步骤来面板镀覆所述通孔柱层：
面板镀覆连续铜层；
在所述连续铜层上沉积光刻胶层；
在所述光刻胶层中显影出通孔图案；
蚀刻掉过量的铜以留下所述图案；和
剥除已显影的光刻胶以留下直立的通孔。
24.如权利要求13所述的方法，其中所述第一介电材料包括聚合物树脂，其选自聚四氟乙烯、聚四氟乙烯衍生物、双马来酰亚胺三嗪树脂、环氧树脂、聚酰亚胺树脂、聚苯醚及其混合物。
25.如权利要求24所述的方法，其中所述第一介电材料还包括以下至少其一：
(a)无机颗粒填料，其平均粒径为0.5微米至30微米，并且颗粒含量为15wt％-30wt％；
(b)纤维，其选自有机纤维和玻璃纤维，所述纤维排列成选自交叉复合排列、织造毡和随机取向短纤维的排列。
26.如权利要求13所述的方法，其中用介电材料层层压通孔柱层的步骤(d)包括在所述通孔层上施加预浸料以及通过热压层压所述预浸料进行固化，所述预浸料包括在基质中的玻璃纤维，所述基质选自聚酰亚胺、环氧树脂或双马来酰亚胺/三嗪树脂、聚苯醚或其混合物。
27.如权利要求13所述的方法，其中所述第二介电材料包括聚合物树脂，所述聚合物树脂选自聚四氟乙烯、聚四氟乙烯衍生物、双马来酰亚胺三嗪树脂、环氧树脂、聚酰亚胺树脂、聚苯醚及其混合物。
28.如权利要求27所述的方法，其中所述第二介电材料还包括以下至少其一：
(a)无机颗粒填料，其平均粒径为0.5微米至30微米，颗粒含量为15wt％-30wt％；
(b)纤维，其选自有机纤维和玻璃纤维，所述纤维排列成选自交叉复合排列、织造毡和随机取向短纤维的排列。
29.如权利要求13所述的方法，其中用第一介电材料层压通孔柱层的步骤(h)包括在所述芯片和所述布线层上施加预浸料以及通过热压层压所述预浸料进行固化，所述预浸料包括在基质中的玻璃纤维，所述基质选自聚酰亚胺、环氧树脂或双马来酰亚胺/三嗪树脂、聚苯醚或其混合物。
30.如权利要求13所述的方法，其中减薄和平坦化所述第一介电材料层的步骤(e)选自干蚀刻、机械研磨、化学机械抛光及其组合及其两阶段过程。
31.如权利要求13所述的方法，其中在所述通孔层上镀覆布线特征层的步骤(f)包括：
(i)在所述介电材料层上面板镀覆铜，在其上敷设光刻胶层，显影出布线特征层的正性图案，选择性地蚀刻掉过量的铜以留下所述布线特征层，以及剥除所述光刻胶层；或
(ii)敷设光刻胶层，显影出沟槽图案，在所述沟槽中图案镀覆布线特征层，以及剥除所述光刻胶层。
32.如权利要求31所述的方法，其中步骤(f)还包括在减薄的所述第一介电材料层上沉积粘附金属层的预先步骤。
33.如权利要求32所述的方法，其中所述粘附金属层选自钛、铬和镍-铬合金。
34.如权利要求13所述的方法，其中连接所述芯片的步骤(g)包括施加焊剂。
35.如权利要求13所述的方法，其中将所述芯片连接至所述布线特征结构的步骤(g)包括将金、铝或铜导线从所述芯片延伸至所述布线特征结构。
36.如权利要求13所述的方法，其中移除所述牺牲基板的步骤(i)包括蚀刻掉铜。
37.如权利要求13所述的方法，其中移除所述牺牲基板的步骤(i)包括剥除第一铜层和蚀刻掉剩余的铜。
38.如权利要求37所述的方法，其中移除所述牺牲基板的步骤(i)采用湿蚀刻过程，并且利用在步骤(b)中制造的所述蚀刻阻挡层作为蚀刻停止层。
39.如权利要求38所述的方法，其中在步骤(b)中制造的所述蚀刻阻挡层包括钽，并且用于蚀刻掉所述牺牲基板的步骤(i)中的蚀刻过程包括将所述牺牲基板暴露于升高温度下的氢氧化铵溶液中。
40.如权利要求13所述的方法，其中所述牺牲基板包括覆铜层压板。
41.如权利要求13所述的方法，其中在步骤(b)中制造的所述蚀刻阻挡层选自钽、钛和钨以及钛-钨合金，并且移除蚀刻阻挡层的步骤(j)包括使用CF4和氩气的混合物的等离子体蚀刻。
42.如权利要求13所述的方法，其中在步骤(b)中制造的所述蚀刻阻挡层选自钽、钛和钨以及钛-钨合金，并且移除蚀刻阻挡层的步骤(j)包括使用CF4和氧气的混合物的等离子体蚀刻。
43.如权利要求13所述的方法，还包括对所述通孔的暴露端部施加最终涂层，所述涂层选自镍、金、锡、铅、银、钯及其合金以及有机防锈面层。
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