US20120287583A1 - Embedded chip package - Google Patents

Embedded chip package Download PDF

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Publication number
US20120287583A1
US20120287583A1 US13/557,774 US201213557774A US2012287583A1 US 20120287583 A1 US20120287583 A1 US 20120287583A1 US 201213557774 A US201213557774 A US 201213557774A US 2012287583 A1 US2012287583 A1 US 2012287583A1
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United States
Prior art keywords
substrate
package structure
chip
fan
electronic assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US13/557,774
Inventor
Klaus Pressel
Gottfried Beer
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Infineon Technologies AG
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Infineon Technologies AG
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Publication date
Priority to US11/762,411 priority Critical patent/US8237259B2/en
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to US13/557,774 priority patent/US20120287583A1/en
Publication of US20120287583A1 publication Critical patent/US20120287583A1/en
Application status is Abandoned legal-status Critical

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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/191Disposition
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Abstract

An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. patent application Ser. No. 11/762,411, entitled “EMBEDDED CHIP PACKAGE,” having a filing date of Jun. 13, 2007, and is incorporated herein by reference.
  • BACKGROUND
  • The invention relates to embedding electronic components into a substrate.
  • Embedding active devices into a substrate has been realized as a promising technology for applications in which size, thickness and weight of electronic devices are sought to be minimized. Such requirements are often encountered in portable applications such as cell-phones, laptop PCs, palms, PDUs (Personal Digital Assistant) etc.
  • Recently, chips have been directly embedded into build-up layers of SBU (Sequential Build-up) laminate substrates. This concept is known as Chip in Polymer (CiP) technology. In this approach, chips are mounted e.g., on a core of the substrate and embedded inside a film of dielectric layer.
  • In another embodiment, a cavity is formed in a substrate and the chip is placed inside this cavity. The chip is then bonded by conventional bonding techniques.
  • For these and other reasons, there is a need for the present invention.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
  • FIG. 1 illustrates a cross-sectional view of a substrate embedding a chip package;
  • FIG. 2 illustrates a cross-sectional view of a substrate including build-up layers embedding a chip package;
  • FIG. 3 is a cross-sectional side view of a first fan-out type package,
  • FIG. 4 illustrates a detail of FIG. 3;
  • FIG. 5 illustrates a cross-sectional side view of a second fan-out type package including a chip and a further electronic component;
  • FIG. 6 illustrates a cross-sectional side view of a third fan-out type package including a chip and a further electronic component;
  • FIG. 7 illustrates a cross-sectional side view of a fourth fan-out type package containing stacked electronic components;
  • FIG. 8 illustrates a cross-sectional side view of a fifth fan-out type package containing a chip which is flip-chip mounted on a substrate chip carrier;
  • FIG. 9 illustrates a cross-sectional side view of a sixth fan-out type package containing a chip which is wirebond mounted on a substrate chip carrier;
  • FIGS. 10 to 14 illustrate an example of a process flow used for embedding a fan-out type package into a substrate;
  • FIGS. 15 to 18 illustrate an example of a process flow for encapsulating fan-out type packages into a mold compound; and
  • FIG. 19 illustrates a cross-sectional side view of a third substrate embedding a chip package.
  • DETAILED DESCRIPTION
  • In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
  • It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
  • Fan-out type packages are packages embedding a chip, wherein at least some of the package pads and/or conducting lines connecting the chip to the package pads are located laterally outside of the outline of the chip or do at least intersect the outline of the chip. Thus, in fan-out type packages, a peripherally outer part of the package of the chip is typically (additionally) used for electrically bonding the package to external applications (e.g., application boards etc.). This outer part of the package encompassing the chip effectively enlarges the contact area of the package in relation to the footprint of the chip, thus leading to relaxed constrains in view of package pad size and pitch with regard to later processing, e.g., second level assembly.
  • Embodiments of fan-out type packages described in the following may be of various design. The fan-out area around the chip may be provided by a surface of a mold compound used for encapsulating the chip. Another possibility is to mount the chip on a substrate (or leadframe) chip carrier having lateral dimensions larger than the chip dimensions and to exploit a peripheral region of the laminate substrate chip carrier as a fan-out area.
  • Embodiments of the package may use various types of chips, among them logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, sensor circuits, MEMS (Micro-Electro-Mechanical Systems), power integrated circuits, chips with integrated passives, passives etc.
  • Embodiments of the substrate may include substrates of different type and configuration, in particular PCBs (Printed Circuit Boards), SBU (Sequential Build-Up) laminate substrates, ceramic substrates, leadframes and mold compounds, e.g., MIDs (Molded Interconnect Devices).
  • Embodiments for bonding the package pads to the wiring of the substrate may include thin-film technology, soldering, welding, diffusion or bond wire technologies.
  • FIG. 1 depicts a cross-sectional view of a first embodiment of the invention. Same reference signs designate like parts in the following drawings. A fan-out type package 1 is embedded in a substrate 2. The fan-out type package 1 contains a chip 3, the outline of which is indicated by dashed line 4.
  • A fan-out area 5 of the package 1 is delimited by the outline 4 of the chip 3 and the periphery of the fan-out type package 1. Pads 6 of the fan-out type package 1 are located at least partially within the fan-out area 5. Additional pads (not illustrated) may be distributed over a footprint area 7 of the fan-out type package 1.
  • The package pads 6 are bonded to chip pads (not illustrated) on the chip 3 by means (not illustrated) which will be exemplified further below. Virtually all known bonding techniques may be utilized.
  • Due to the increased space around chip 3 provided by the fan-out area 5 for the pads 6 (i.e. the interconnect of the package 1), fan-out packages 1 allow to increase the number of package pads 6 and/or the pitch of package pads 6 compared to fan-in packages or bare chip solutions. As a consequence, embedding fan-out type packages 1 in a substrate 2 is beneficial in view of several aspects:
  • A fan-out type package 1 provides a good protection to the chip 3 against outside damages. Especially, it is possible to protect all surfaces of the chip 3, if the package 1 completely encapsulates chip 3. Typically, at least the lateral edge of chip 3 may be protected by the package 1 by the part of the package 1 which creates the fan-out area 5.
  • Semiconductor material is expensive resulting in that the chip size is permanently shrinking Fan-out type packaging provides a low cost possibility to maintain package interconnect dimensions and geometry through the shrinkage of chip size. Consequently, the wiring provided within or on the substrate must not be modified when new technologies provide for smaller chips 3.
  • Fan-out type packages might have a high level test coverage to meet the “known good die/device” aspects.
  • As the size and/or pitch of the package pads 6 may be relatively large in fan-out type packages 1, geometric tolerances are less stringent for fan-out solutions than for fan-in solutions in any bonding process applied for connecting the package pads 6 to substrate wiring (not illustrated) or external applications. Thus, the overall yield for a package-in-substrate structure is significantly enhanced when using fan-out type packages instead of fan-in structures.
  • Fan-out type packages facilitate repair approaches compared to the case in which bare chips or fan-in structures are embedded in a substrate.
  • Fan-out type packages allow for an improved shielding of the chip 3, because more space is provided on or in the package structure for applying a metallization for shielding especially in the peripheral region of the chip 3.
  • FIG. 2 depicts a fan-out type package 1 embedded in a substrate 20. Substrate 20 is an SBU laminate substrate. SBU laminate substrate 20 includes a core 21 provided by one or more (here: four) core layers 21 a, 21 b, 21 c, 21 d and build-up layers 22, 23 at both sides of the core 21.
  • Each core layer 21 a, 21 b, 21 c, 21 d may be composed of glass-fiber-reinforced epoxy resin. Core layers 21 a, 21 b, 21 c, 21 d made of a fluoropolymer material such as e.g., polytetrafluoroethylene, aramid fibers, or carbon fibers may also be used. Metal layers 24 are arranged between the core layers 21 a, 21 b, 21 c, 21 d. By way of example, if carbon fibers are used, core layers 21 a, 21 b, 21 c, 21 d and metal layers 24 may form a copper-carbon fiber compound material. Core vias 25 are arranged to penetrate the core layers 21 a, 21 b, 21 c, 21 d and are used to electrically connect specific metal layers 24 of the multi-layer core 21. To this end, the core via 25 is internally coated by a metal jacket 26. As it is apparent for a person skilled in the art, the design of the core 21 is similar to the design of a conventional PCB and may be formed by conventional laminated PCB processing techniques. Thus, core vias 25 are typically formed by mechanical drilling and extend through the entire core 21. Core thickness may be in the range of several hundreds μm and the via size may be in the range of one or multiple hundreds of μm.
  • The fan-out type package 1 may be mounted on the uppermost core layer 21 a. Here it is embedded in build-up layer 22 a and covered by build-up layers 22 b, 22 c. Build-up layers 22 a, 22 b, 22 c may be a dielectric, e.g., silica-filled epoxies plated by metal layers 27. Metallized vias 28 interconnect between adjacent metal layers 27.
  • Typically, the build-up layers 22, metal layers 27 and vias 28 are generated by thin-film processing techniques. For example, vias 28 which are typically blind and buried may be formed by laser drilling and are tapered, having different lower and upper diameters. Other techniques like photo-structuring might also be used. Metallization of vias 28 may be formed by sputtering or plating a metal over the entire surface of the underlying build-up layer 22 a, 22 b, 22 c. Then, a photoresist material is applied and patterned. The desired metal pattern is obtained by etching the unprotected metal layer 27. Other techniques, such as printing, ink jetting or laser direct structuring a conductive material or catalytic starter may also be used. Multiple build-up layers 22 a, 22 b, 22 c, corresponding vias 28 and metal layers 27 are formed by applying an addition dielectric film and repeating the via formation and metallization processes. Passive components (not illustrated) such as capacitors, resistors and inductors may be embedded during the layer build-up process.
  • The lower build-up layers 23 are formed using a similar step-wise building process.
  • Typically, most of the wiring capability of the SBU laminate substrate 20 occurs in the build-up layers 22, 23. To this end, the trace and space dimensions in the build-up layers 22, 23 are significantly finer than those in the core 21. The thickness of build-up layers, e.g., 22 b, 22 c, may be in the range of about 10 μm and the diameter of via 28 may be some tens of μm. Layers 22 a and 22 b may be combined to one layer and may be thicker than the typical 10 μm at least on the package corners to incorporate the package. In SBU laminate substrate 20, often signal routing is performed within the build-up layers 22, 23 whereas power distribution is accomplished by the core 21. Further, the core 21 provides for an adequate rigidity of the SBU laminate substrate 20.
  • As illustrated in FIG. 2, the fan-out type package 1 may be attached directly on the uppermost core layer 21 a and/or embedded within a single build-up layer 22 a. However, the fan-out type package 1 may also be embedded in multiple build-up layers 22 a, 22 b, 22 c (i.e. the height of the fan-out type package 1 may correspond to the height of several build-up layers 22 a, 22 b, 22 c) or may be disposed on a build-up layer 22 a, 22 b, 22 c rather than directly on the uppermost core layer 21 a. Further, it is possible that the fan-out type package 1 is embedded into the core 21, i.e. encapsulated in one or more core layers 21 a, 21 b, 21 c, 21 d, rather than in one or more of the build-up layers 22 a, 22 b 22 c.
  • FIG. 3 illustrates an embodiment of a first fan-out type package 101. The fan-out type package 101 includes a chip 103 embedded in a matrix of mold compound 108. More specifically, the backside of the chip 103 and its edges are covered with mold compound 108, with the fan-out area of the mold compound 108 being denoted by the reference sign 105. The mold compound 108 may be a duroplastic resin, a thermosetting plastic material, a thermoplastic resin or a composite compound. The active surface 109 of the chip 103 lies flush with the upper surface 110 of the fan-out area 105 of the mold compound 108, and a first dielectric layer 111 a, a metal redistribution layer 112 and a second dielectric layer 111 b extend over the plane composed of the active surface 109 of the chip 103 and the upper surface 110 of the mold compound 108, compare FIG. 4. The first and second dielectric layers 111 a, 111 b and the metal redistribution layer 112 may be manufactured in a thin-film process onto the plane composed of the active surface 109 of the chip 103 and the upper surface 110 of the fan-out area 105 of the mold compound 108. The fabrication of the first and second dielectric layers 111 a, 111 b as well as the metal redistribution layer 112 and the generation of via 113 may be accomplished by applying thin-film technology processes as explained in conjunction with the manufacturing of the build-up layers 22, 23 depicted in FIG. 2. Thus, via 113 may be formed photo-lithographically, jetted or by laser drilling and the redistribution layer 112 may be structured by photo-lithographic processes. Higher number of layers might be applied when needed.
  • The second, upper dielectric layer 111 b may serve as a solder stop when solder balls 114 are optionally applied to exposed contact regions 115 of the metal redistribution layer 112. Instead of solder balls 114, it is also possible that solder bumps of less height showing a smoother curved, lenticular surface or flat metal contact posts (which might be applied by a non-galvanic plating process) are deposited on the exposed contact region 115 of the metal redistribution layer 112.
  • Fan-out type package 101 may be fabricated in an embedded device technology based on a molded reconfigured wafer. This embedded device wafer level packaging (eWLP) technology is developed from standard wafer level packaging (WLP) technology. Standard WLP technology is defined such that virtually all technology processes are performed on wafer level. More specifically, in standard WLP, dielectric and metal layers such as layers 111 a, 111 b and 112 are deposited and processed on the active surface of the wafer before the wafer is cut into single chips. Consequently, standard WLPs are always fan-in solutions. In contrast to WLP technology, in eWLP technology the front-end processed and probed wafer is first singulated to obtain single chips. The chips 103 are then placed onto a support in a spaced-apart relationship. In the next process, the spaced-apart chips 103 on the support are molded, e.g., by using a liquid mold compound that is dispensed over the chips 103 on the support. Thereby, the gaps between the placed chips are filled with liquid mold compound. After curing the mold compound, the support is removed to obtain the reconfigured wafer, in which the chips are distributed within the mold compound in a regular, array-like fashion. This reconfigured wafer is then processed according to standard WLP technology, i.e. the dielectric layers 111 a, 111 b and the metal redistribution layer 112 are applied typically by using thin-film processes. Moreover, appropriate connecting elements such as solder balls 114, solder bumps or metal elements may optionally be applied on wafer level. Only after finishing the fan-out package interconnect, the molded reconfigured wafer is singularized into single packages such as, for instance, illustrated in FIG. 3.
  • FIG. 5 illustrates a second fan-out type package 201. The fan-out type package 201 distinguishes from the fan-out type package 101 mainly in that the package 201 encapsulate a chip 203 and a further electronic component 215 (more than one further component could be applied, but by way of simplification only one is depicted). The further electronic component 215 may be a passive element, e.g., a capacitor, a resistor or an impedance, or may be another integrated circuit. The further component 215 is interconnected to the chip 203 via an interconnect structure including first and second (for many practical cases only one dielectric will be sufficient) dielectric layers 211 a, 211 b, vias 213 and a structured metal redistribution layer 212 similar to layers 111 a, 111 b, vias 113 and the structured metal redistribution layer 112 as explained above. The second package 201 represents an SiP (System in Package), as it includes more than one electronic components encapsulated by the package 201. For fabrication, eWLP technology may be applied in the same way as described in conjunction with FIGS. 3, 4.
  • FIG. 6 illustrates a third fan-out type package 301 similar to 201 which likewise represents an SiP. More specifically, fan-out type package 301 includes a chip 303, a further electronic component 315, first and second dielectric layers 311 a, 311 b, vias 313 and a metal redistribution layer 312 in accordance with the description of parts 203, 215, 211 a, 211 b, 213 and 212, respectively, as explained above in conjunction with FIG. 5. In contrast to the fan-out type package 201, fan-out type package 301 is equipped with a conductive layer 316 at the backside of chip 303 and/or electronic component 315 (which may likewise be an integrated circuit). The layer 316 may also be a dissipative layer having a higher specific electrical resistance than conductive layers typically used for signal distribution. The conductive layer 316 may be structured (not illustrated in FIG. 6). It could serve for different functions such as providing an interconnect to chip 303 and/or electronic component 315, providing a shielding against electromagnetic interference to the fan-out type package 301 and providing for an improved thermal transfer of heat out of the fan-out type package 301. The conductive layer 316 may be of a conductive polymer (especially if it is intended to provide for shielding) or may be made of metal. There might also be a dielectric layer and/or multilayers between the components 303, 315. Fabrication of the fan-out type package 301 may be again performed using eWLP technology as described above. It is to be noted that packages 101, 201 may likewise be equipped with such conductive layer at the backside and/or at the edge of the package 101, 102.
  • Further, in all fan-out type packages 101, 201, 301, the upper dielectric layer 111 b, 211 b, 311 b may be omitted. That is because if fan-out type packages 101, 201, 301 are embedded, e.g., in an SBU laminate substrate 20 as illustrated in FIG. 2, the first build-up layer 22 b covering the fan-out type package 101, 201, 301 may serve as a solder stop, i.e. may replace the upper dielectric layer 111 b, 211 b, 311 b.
  • Further, it is to be noted that the fan-out type packages 101, 201, 301 shall be as thin as possible in order to facilitate the accommodation in the substrate. Thus, in all embodiments described herein, the chips may be thinned e.g., by mechanical grinding or chemical etching the backside of the chip 103, 203, 303.
  • Nevertheless, fan-out type packages with stacked components are feasible. FIG. 7 illustrates a fan-out type package 401 which is designed and may be fabricated substantially in line with the descriptions of FIGS. 3 to 6. Briefly, parts denoted by reference signs 403, 415, 411 a, 411 b, 412 and 413 correspond to parts illustrated in FIG. 6 denoted by reference signs 303, 315, 311 a, 311 b, 312 and 313. In contrast to the example of the fan-out type package 301, the fan-out type package 401 includes a third electronic component 416 which is located above the chip 403 and the second electronic component 415. Similar to the second electronic component 415, the third electronic component 416 may be a passive element (resistor, inductor, capacitance) or an integrated circuit. The third electronic component 416 in the example illustrated is disposed on the first dielectric layer 411 a and embedded in an intermediate dielectric layer 417 extending in between the first and second dielectric layers 411 a, 411 b. Similar to the fan-out type packages 101, 201, 301, the backside of the package 401 may be made of continuous mold compound (cf. FIGS. 3, 4, 5), a conductive layer 316 (cf. FIG. 6) or—as depicted in FIG. 7—may include one or more areas of bare semiconductor material.
  • FIGS. 8 and 9 illustrate fan-out type packages 501, 601 which are basically different to the fan-out type packages exemplified in FIGS. 3 to 7. Packages 501, 601 use a laminate substrate 508, 608 as a carrier for chip 503, 603. The lateral dimensions of the laminate substrate chip carrier 508, 608 in relation to the (lateral) outline 504, 604 of the chip 503, 603 define the available fan-out area 505, 605 provided by the packages 501, 601. The laminate substrate chip carrier 508, 608 is known as “interposer” in the art. In the depicted example it includes a core dielectric material 509, 609 metallized on both sides by structured metal layers 510, 610. Thin dielectric layers 511, 611 are applied to the structured metal layers 510, 610, e.g., to serve as a solder stop. The laminate substrate chip carrier 508, 608 is equipped with metallized vias in order to interconnect the structured metal layers 510, 610 on both sides of the core 509, 609. The chip 503 in FIG. 8 is flip-chip bonded to the laminate substrate chip carrier 508 by flip-chip solder bumps 512, whereas chip 603 in FIG. 9 is wire-bonded to the laminate substrate chip carrier 608 by bond wires 612. In FIG. 8 an underfill material 513 may be introduced between the chip 503 and the laminate substrate chip carrier 508. In FIG. 9 the chip 603 is fixed to the chip carrier 608 with the die attach material 613. Solder balls 514, 614 are contacted to the structured metal layer 511, 611 opposite to the chip 503, 603. Further, a mold compound 520, 620 is provided over the laminate substrate chip carrier 508, 608 and encapsulates the chip 503, 603 along with the bonding elements 512, 612. Packages as illustrated in FIGS. 8 and 9 are known as BGAs (Ball Grid Arrays). Another package group in this area which could be used is the VQFN (Very Thin Quad Flat), which is not depicted here.
  • Fan-out type mold compound packages 101, 201, 301, 401 and fan-out type BGA packages 501, 601 are integrated in e.g., substrates 2, 20 as illustrated in FIGS. 1, 2 with reference to fan-out type package 1. In other words, any description relating to the integration of fan-out type package 1 in substrate 2 or 20 applies to eWLP technology packages 101, 201, 301, 401 as well as laminate substrate chip carrier or any interposer based fan-out type packages like 501, 601 or/and VQFNs.
  • Further, substrate 2 may itself be a mold compound structure. An example for a process of integrating a fan-out type package 1 into a mold compound substrate is illustrated in FIGS. 10 to 14.
  • In FIG. 10, a fan-out type package 1 which may be designed in accordance with any of the previously described fan-out type packages 1, 101, 201, 301, 401, 501, 601 is mounted on a mounting platform 1000. The mounting platform 1000 may be a plate made of a dielectric material, for instance an epoxy thermoset, thermoplastic material or a glass-fiber enforced epoxy. It may also be a PCB. In this case, a structured metal (e.g., copper) layer, which is not depicted in FIGS. 10 to 14, is provided on the upper surface of the dielectric mounting platform 1000.
  • The fan-out type package 1 is mounted on the mounting platform 1000. If the backside of the fan-out type package 1 is made of mold resin, the chip 3 is insulated from any metal layer optionally provided at the upper surface of the mounting platform 1000.
  • In a next process, the fan-out type package 1 is covered by a mold compound 1001. The mold compound 1001 is a dielectric material and may be identical to the material of the mold compound 108 used for encapsulating the chips 103, 203, 303, 403 in FIGS. 3 to 7. According to FIG. 12, the substrate mold compound 1001 completely covers and extends over the top surface of the fan-out type package 1.
  • According to FIG. 13, in order to contact the fan-out type package 1, through-holes 1002 are produced in the substrate mold compound 1001 in a region above the fan-out type package 1. The through-holes 1002 open to pads 6 of the fan-out type package 1. As already mentioned before, pads 6 of the fan-out type package 1 are interconnected to pads (not illustrated) on chip 3. As illustrated in FIG. 14, pads 6 of the fan-out type package 1 are connected to external applications by chemical or galvanic deposition of a metal layer 1003 on the mold compound 1001, which extends through the through-holes 1002 down to the package pads 6. The through-holes 1002 may be generated by laser drilling or other suitable processes. Structuring of the metal layer 1003 may be accomplished by using thin-film techniques such as lithographic processes. Further, e.g., using thin-film techniques, it is possible that a plurality of polymer layers and metal layers are deposited alternately over the substrate mold compound 1001 to provide a substrate wiring which may be the same as the top and/or bottom wiring 22, 23 of an SBU laminate substrate 20 illustrated in FIG. 2.
  • The substrate mold compound 1001 may be applied by various techniques, among them laminating processes, spin-coating or dispensing of a liquid dielectric material, e.g., based on liquid epoxy. FIGS. 15 to 18 illustrate a compression molding process which might be used for encapsulating fan-out type packages 1 into a substrate 2. Besides compression molding, transfer molding or other molding techniques may be used for practicing the resin encapsulation process of FIG. 12.
  • In compression molding, a fast melting or liquid mold compound 1001 is required, which is supplied substantially in the middle of the mounting platform 1000 carrying a number of fan-out type packages 1. The mounting platform 1000, the fan-out type packages 1 and dispensed mold compound 1001 is then transferred between two mold halves 2001, 2002 of a molding tool. In a compression phase depicted in FIG. 16, the molding halves 2001, 2002 are closed under the application of heat. By closing the molding halves 2001, 2002, the liquid mold compound 1001 is distributed within the cavity defined by the molding halves 2001, 2002. In a subsequent curing phase, the mold compound 1001 is cured. Then, a substrate composed of the mounting platform 1000 and mold compound 1001 encapsulating fan-out type packages 1 as depicted in FIG. 18 and represented in FIG. 12 for the case of a single embedded fan-out type package 1 is taken out of the mold tool. Analog to the FIGS. 4 to 7 there could be integrated several different device packages 1 and/or different chips/passives combined into “new” eWLP.
  • As previously mentioned, the molding of chip 3 in a package 1 as depicted in FIGS. 3 to 7 may be accomplished equally by the process of compression molding. Thus, mounting platform 1000, mold compound substrate 1001 and mold compound fan-out type package 1 could be termed a (fan-out type) mold compound package-in-mold compound substrate structure. Analog to the FIGS. 4 to 7 there could be integrated several different device packages 1 and/or different chips/passives combined into “new” eWLP.
  • Further, it is to be noted that fan-out type packages 1 may be embedded in conventional PCB single layer or multi-layer substrates (where each layer is made e.g., of glass-fiber-reinforced epoxy resin coated by a metal layer) or in ceramic substrates. In these cases, it might be necessary to form a cavity in the substrate and then to insert the fan-out type package 1 into the cavity. FIG. 19 illustrates a substrate 3000 in which a recess 3001 has been machined. The recess 3001 is partially filled by a dielectric material 3002, e.g., epoxy, and a fan-out type package 1 is inserted into the recess 3001. The fan-out type package 1 may be interconnected by thin-film techniques using build-up layers 3004, 3005 and vias 3006 as described above in connection with FIG. 2. It is to be noted that recessed substrate 3000 is not limited to a PCB or ceramic substrate but may be of alternate kind, including mold compound or an SBU laminate substrate. If the package 1 is thin enough, it is obvious that no recess is needed and such packages may be embedded into the layers 22 depicted in FIG. 2.
  • Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments illustrated and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims (38)

1. An electronic assembly, comprising:
at least one semiconductor chip defining a chip outline;
a package structure embedding the semiconductor chip, the package structure defining a package periphery; and
the package structure comprising at least one conducting line extending into an area of the package structure that is outside of the outline of the chip and inside the package periphery.
2. The electronic assembly of claim 1, further comprising a substrate wherein the substrate is a printed circuit board.
3. The electronic assembly of claim 1, wherein the package structure comprises a carrier on which the chip is mounted, wherein the carrier extends laterally beyond the outline of the chip.
4. The electronic assembly of claim 3, wherein the carrier is a laminate substrate.
5. The electronic assembly of claim 3, wherein the carrier is a leadframe.
6. The electronic assembly of claim 4, wherein the chip is flip-chip mounted on the carrier.
7. The electronic assembly of claim 5, wherein the chip is wire-bonded to the carrier.
8. The electronic assembly of claim 1, wherein a backside of the package structure is a multilayer.
9. The electronic assembly of claim 1, wherein the substrate comprises at least one core layer and at least one polymer build-up layer above the epoxy core layer.
10. The electronic assembly of claim 8, wherein the package structure is embedded in the at least one polymer build-up layer.
11. The electronic assembly of claim 8, wherein the package structure is embedded in the at least one core layer.
12. The electronic assembly of claim 9, wherein the core layer is made of one or more materials of the group comprising epoxy, fluoropolymer, polytetrafluoroethylene, aramid fibers, and carbon fibers.
13. The electronic assembly of claim 1, wherein the substrate comprises a copper-carbon fiber compound material.
14. The electronic assembly of claim 1, wherein the substrate is a mold compound.
15. The electronic assembly of claim 1, wherein the substrate is a printed circuit board.
16. The electronic assembly of claim 1, wherein the substrate is a ceramic substrate.
17. The electronic assembly of claim 16, wherein the package structure is mounted in a cavity of the ceramic substrate.
18. A method comprising:
providing a package structure embedding at least one semiconductor chip and comprising at least one conducting line extending into an area of the package structure inside a package periphery and outside of the outline of the chip.
19. The method of claim 18, further comprising:
including the package structure on a substrate and
providing a conductive wiring of the substrate.
20. The method of claim 19, further comprising:
generating vias in the substrate to connect the conductive wiring to the at least one conducting line of the package structure.
21. The method of claim 20, wherein embedding the package structure in the substrate comprises:
providing a core layer of the substrate;
placing the package structure above the core layer; and
embedding the package structure in at least one polymer build-up layer generated above the epoxy core layer.
22. The method of claim 21, further comprising:
generating vias extending through the at least one polymer build-up layer.
23. The method of claim 19, wherein including the package structure on the substrate comprises:
providing a support member;
placing the package structure onto the support member; and
embedding the package structure into a dielectric compound to generate a molded substrate.
24. The method of claim 23, comprising removing the support member from the molded substrate.
25. The method of claim 23, comprising using a liquid mold material for embedding.
26. The method of claim 25, further comprising:
curing the liquid mold material using a compression mold tool.
27. The method of claim 23, further comprising:
generating vias in the molded substrate to electrically connect to the at least one conducting line.
28. The method of claim 19, wherein including the package structure on the substrate comprises:
encapsulation of the package structure into one or more dielectric layers of a printed circuit board.
29. The method of claim 28, further comprising:
generating vias in at least one dielectric layer to electrically connect to the at least one conducting line.
30. The method of claim 19, wherein including the package structure on the substrate comprises:
forming a cavity in the substrate; and
disposing the package structure into the cavity.
31. An assembly comprising:
a fan-out type package structure comprising a chip, wherein the fan-out type package structure comprises a mold compound embedding the chip, a conductive redistribution layer extending laterally beyond the chip outline and being confined to the package outline and a dielectric layer arranged above the conductive redistribution layer and extending laterally beyond the chip outline and being laterally confined to the package outline.
32. The assembly of claim 31 further comprising a substrate configured to embed the fan-out type package structure, wherein the substrate comprises a conductive wiring electrically connected to the conductive redistribution layer of the fan-out package structure via openings in the dielectric layer, and wherein the substrate is a printed circuit board.
33. The assembly of claim 31, wherein the fan-out type package structure comprises a mold compound embedding the chip and a conductive redistribution layer extending laterally beyond the chip outline.
34. The assembly of claim 32, wherein the substrate comprises a conductive wiring electrically connected to the conductive redistribution layer of the fan-out type package structure.
35. The electronic assembly of claim 32, wherein the substrate is a printed circuit board.
36. The electronic assembly of claim 32, wherein the substrate comprises at least one core layer and at least one polymer build-up layer above the epoxy core layer.
37. A method comprising:
providing a fan-out type package structure comprising a chip; and
embedding the fan-out type package structure in a substrate.
38. The method of claim 37, further comprising:
electrically connecting pads on the fan-out type package structure to a conductive wiring of the substrate.
US13/557,774 2007-06-13 2012-07-25 Embedded chip package Abandoned US20120287583A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103871998A (en) * 2012-12-13 2014-06-18 珠海越亚封装基板技术股份有限公司 Single Layer Coreless Substrate
US9721922B2 (en) 2013-12-23 2017-08-01 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7342303B1 (en) * 2006-02-28 2008-03-11 Amkor Technology, Inc. Semiconductor device having RF shielding and method therefor
DE102006032251A1 (en) * 2006-07-12 2008-01-17 Infineon Technologies Ag A method for producing chip package and chip package produced in this way
US7816792B2 (en) * 2007-09-14 2010-10-19 Infineon Technologies Ag Semiconductor device with conductive interconnect
US7986023B2 (en) * 2007-09-17 2011-07-26 Infineon Technologies Ag Semiconductor device with inductor
US8217482B2 (en) * 2007-12-21 2012-07-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Infrared proximity sensor package with reduced crosstalk
KR20090117237A (en) * 2008-05-09 2009-11-12 삼성전기주식회사 Electronic components embedded pcb and the method for manufacturing thereof
WO2009147547A1 (en) * 2008-06-02 2009-12-10 Nxp B.V. Electronic device and method of manufacturing an electronic device
US8114708B2 (en) * 2008-09-30 2012-02-14 General Electric Company System and method for pre-patterned embedded chip build-up
KR101461630B1 (en) * 2008-11-06 2014-11-20 삼성전자주식회사 Wafer level chip on chip package, package on package improving solder joint reliability but reducing mounting height and manufacturing method thereof
JP5330065B2 (en) 2009-04-13 2013-10-30 新光電気工業株式会社 Electronic device and manufacturing method thereof
US8420999B2 (en) * 2009-05-08 2013-04-16 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Metal shield and housing for optical proximity sensor with increased resistance to mechanical deformation
US9525093B2 (en) 2009-06-30 2016-12-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Infrared attenuating or blocking layer in optical proximity sensor
US8779361B2 (en) * 2009-06-30 2014-07-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Optical proximity sensor package with molded infrared light rejection barrier and infrared pass components
US8957380B2 (en) * 2009-06-30 2015-02-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Infrared attenuating or blocking layer in optical proximity sensor
US8350216B2 (en) * 2009-09-10 2013-01-08 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Miniaturized optical proximity sensor
US8097852B2 (en) * 2009-09-10 2012-01-17 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Multiple transfer molded optical proximity sensor and corresponding method
US8143608B2 (en) * 2009-09-10 2012-03-27 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Package-on-package (POP) optical proximity sensor
US8716665B2 (en) 2009-09-10 2014-05-06 Avago Technologies General Ip (Singapore) Pte. Ltd. Compact optical proximity sensor with ball grid array and windowed substrate
US8334202B2 (en) 2009-11-03 2012-12-18 Infineon Technologies Ag Device fabricated using an electroplating process
US9733357B2 (en) * 2009-11-23 2017-08-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Infrared proximity sensor package with improved crosstalk isolation
US8987830B2 (en) 2010-01-12 2015-03-24 Marvell World Trade Ltd. Attaching passive components to a semiconductor package
TWI395312B (en) * 2010-01-20 2013-05-01 Siliconware Prec Ind Co Ltd Package structure having mems element and method of making the same
US8241952B2 (en) * 2010-02-25 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of forming IPD in fan-out level chip scale package
US8535989B2 (en) * 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
DE102010039156A1 (en) * 2010-08-10 2012-02-16 Robert Bosch Gmbh A method of manufacturing an electrical circuit and electrical circuit
US8624353B2 (en) 2010-12-22 2014-01-07 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device over semiconductor die with conductive bridge and fan-out redistribution layer
US8841597B2 (en) 2010-12-27 2014-09-23 Avago Technologies Ip (Singapore) Pte. Ltd. Housing for optical proximity sensor
US8536695B2 (en) 2011-03-08 2013-09-17 Georgia Tech Research Corporation Chip-last embedded interconnect structures
US9406580B2 (en) 2011-03-16 2016-08-02 Synaptics Incorporated Packaging for fingerprint sensors and methods of manufacture
US8937382B2 (en) * 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) * 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
US20130075928A1 (en) * 2011-09-23 2013-03-28 Texas Instruments Incorporated Integrated circuit and method of making
US9679836B2 (en) * 2011-11-16 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods for forming the same
WO2013102146A1 (en) 2011-12-30 2013-07-04 Deca Technologies, Inc. Die up fully molded fan-out wafer level packaging
US9831170B2 (en) 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
US9177926B2 (en) 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
US9576919B2 (en) 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US9613830B2 (en) 2011-12-30 2017-04-04 Deca Technologies Inc. Fully molded peripheral package on package device
JP6142800B2 (en) * 2012-02-09 2017-06-07 パナソニック株式会社 Semiconductor device and manufacturing method thereof
US9536798B2 (en) * 2012-02-22 2017-01-03 Cyntec Co., Ltd. Package structure and the method to fabricate thereof
WO2013172814A1 (en) * 2012-05-14 2013-11-21 Intel Corporation Microelectronic package utilizing multiple bumpless build-up structures and through-silicon vias
AT513047B1 (en) * 2012-07-02 2014-01-15 Austria Tech & System Tech A method for embedding at least one component in a printed circuit board
JP2014086651A (en) * 2012-10-26 2014-05-12 Ibiden Co Ltd Printed wiring board and manufacturing method for printed wiring board
KR20140055006A (en) * 2012-10-30 2014-05-09 엘지이노텍 주식회사 Printed circuit board for mounting chip and manufacturing method thereof
CN104584210B (en) 2012-12-21 2017-09-26 松下知识产权经营株式会社 An electronic component package manufacturing method thereof
JP5624700B1 (en) * 2012-12-21 2014-11-12 パナソニック株式会社 Electronic component package and a method for manufacturing the same
US9595651B2 (en) 2012-12-21 2017-03-14 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing same
WO2014097645A1 (en) 2012-12-21 2014-06-26 パナソニック株式会社 Electronic component package and method for producing same
US9356332B2 (en) 2013-04-29 2016-05-31 Infineon Technologies Ag Integrated-circuit module with waveguide transition element
US9856136B2 (en) 2013-06-05 2018-01-02 Intel Deutschland Gmbh Chip arrangement and method for manufacturing a chip arrangement
DE102013014587B4 (en) 2013-08-29 2017-10-19 Fachhochschule Schmalkalden Method for IT protect security-sensitive data and their processing
CN105934823A (en) 2013-11-27 2016-09-07 At&S奥地利科技与系统技术股份公司 Circuit board structure
AT515447A1 (en) 2014-02-27 2015-09-15 Austria Tech & System Tech A method for contacting a embedded in a printed circuit board device and the printed circuit board
DE102014103954A1 (en) * 2014-03-21 2015-09-24 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Reinforcing structures with thermal conductivity-increasing coating in the resin matrix and by coating separate electrical conductor structure
SG10201401622RA (en) 2014-04-17 2015-11-27 Delta Electronics Int’L Singapore Pte Ltd Package structure
US9646955B2 (en) 2014-09-05 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and methods of forming packages
US20160183391A1 (en) * 2014-12-17 2016-06-23 The Charles Stark Draper Laboratory, Inc. Methods and devices for miniaturization of high density wafer based electronic 3d multi-chip modules
US10115688B2 (en) * 2015-05-29 2018-10-30 Infineon Technologies Ag Solder metallization stack and methods of formation thereof
US10050004B2 (en) 2015-11-20 2018-08-14 Deca Technologies Inc. Fully molded peripheral package on package device
US9999121B2 (en) 2016-04-25 2018-06-12 Laird Technologies, Inc. Board level shields with virtual grounding capability
US9679878B1 (en) 2016-07-27 2017-06-13 Semiconductor Components Industries, Llc Embedded stacked die packages and related methods
US10218407B2 (en) 2016-08-08 2019-02-26 Infineon Technologies Ag Radio frequency system and method for wearable device
DE102017215354A1 (en) 2016-10-14 2018-04-19 Infineon Technologies Ag Semiconductor and process for the manufacture of semiconductor devices
DE102016224936A1 (en) 2016-12-14 2018-06-14 Robert Bosch Gmbh radar module
DE102017208435A1 (en) 2017-05-18 2018-11-22 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. A method of encapsulating a semiconductor chip in a housing

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5306670A (en) * 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
US6143981A (en) * 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6762488B2 (en) * 2002-03-19 2004-07-13 Nec Electronics Corporation Light thin stacked package semiconductor device and process for fabrication thereof
US20050124093A1 (en) * 2003-12-03 2005-06-09 Wen-Kun Yang Fan out type wafer level package structure and method of the same
US20060008944A1 (en) * 2003-09-26 2006-01-12 Yoshinori Shizuno Substrate having built-in semiconductor apparatus and manufacturing method thereof
US20060115931A1 (en) * 2004-11-26 2006-06-01 Phoenix Precision Technology Corporation Semiconductor package substrate with embedded chip and fabrication method thereof
US20070262436A1 (en) * 2006-05-12 2007-11-15 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6714336A (en) 1967-10-21 1969-04-23
JPS5759453U (en) 1980-09-24 1982-04-08
US5241456A (en) 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5847951A (en) 1996-12-16 1998-12-08 Dell Usa, L.P. Method and apparatus for voltage regulation within an integrated circuit package
US6107179A (en) * 1998-05-28 2000-08-22 Xerox Corporation Integrated flexible interconnection
US6114048A (en) * 1998-09-04 2000-09-05 Brush Wellman, Inc. Functionally graded metal substrates and process for making same
DE19954941C2 (en) 1999-11-16 2003-11-06 Fraunhofer Ges Forschung A method of integrating a chip within a printed circuit board
US6486005B1 (en) * 2000-04-03 2002-11-26 Hynix Semiconductor Inc. Semiconductor package and method for fabricating the same
JP2002040095A (en) 2000-07-26 2002-02-06 Nec Corp Semiconductor device and mounting method thereof
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
CN100539106C (en) * 2000-09-25 2009-09-09 揖斐电株式会社 Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US6707149B2 (en) * 2000-09-29 2004-03-16 Tessera, Inc. Low cost and compliant microelectronic packages for high i/o and fine pitch
US6423570B1 (en) * 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
DE10137184B4 (en) * 2001-07-31 2007-09-06 Infineon Technologies Ag A method for manufacturing an electronic component having an electronic component and Kuststoffgehäuse
US6727576B2 (en) * 2001-10-31 2004-04-27 Infineon Technologies Ag Transfer wafer level packaging
TW503496B (en) * 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
US6977436B2 (en) * 2002-02-14 2005-12-20 Macronix International Co. Ltd. Semiconductor packaging device
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US6750397B2 (en) * 2002-02-15 2004-06-15 Advanced Semiconductor Engineering, Inc. Thermally enhanced semiconductor build-up package
US7485489B2 (en) 2002-06-19 2009-02-03 Bjoersell Sten Electronics circuit manufacture
US6756662B2 (en) * 2002-09-25 2004-06-29 International Business Machines Corporation Semiconductor chip module and method of manufacture of same
DE10250621B4 (en) * 2002-10-30 2004-09-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. A method for generating encapsulated chips and for producing a stack of the encapsulated chips
US6905914B1 (en) * 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US7141874B2 (en) 2003-05-14 2006-11-28 Matsushita Electric Industrial Co., Ltd. Electronic component packaging structure and method for producing the same
CN100468719C (en) * 2003-06-03 2009-03-11 卡西欧计算机株式会社;Cmk株式会社 Overlappable semiconductor device and method of manufacturing the same
TWI255538B (en) * 2003-06-09 2006-05-21 Siliconware Prec Ind Co Ltd Semiconductor package having conductive bumps on chip and method for fabricating the same
TWI236113B (en) * 2003-08-28 2005-07-11 Advanced Semiconductor Eng Semiconductor chip package and method for making the same
TWI256095B (en) * 2004-03-11 2006-06-01 Siliconware Prec Ind Co Ltd Wafer level semiconductor package with build-up layer and process for fabricating the same
US7208344B2 (en) * 2004-03-31 2007-04-24 Aptos Corporation Wafer level mounting frame for ball grid array packaging, and method of making and using the same
TWI239611B (en) 2004-04-19 2005-09-11 Advanced Semiconductor Eng Multi chip module with embedded package configuration and method for manufacturing the same
US7326592B2 (en) * 2005-04-04 2008-02-05 Infineon Technologies Ag Stacked die package
FI122128B (en) 2005-06-16 2011-08-31 Imbera Electronics Oy Process for the manufacture of circuit-board structure
US7572681B1 (en) * 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US7550857B1 (en) * 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5306670A (en) * 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
US6143981A (en) * 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6762488B2 (en) * 2002-03-19 2004-07-13 Nec Electronics Corporation Light thin stacked package semiconductor device and process for fabrication thereof
US20060008944A1 (en) * 2003-09-26 2006-01-12 Yoshinori Shizuno Substrate having built-in semiconductor apparatus and manufacturing method thereof
US20050124093A1 (en) * 2003-12-03 2005-06-09 Wen-Kun Yang Fan out type wafer level package structure and method of the same
US20060115931A1 (en) * 2004-11-26 2006-06-01 Phoenix Precision Technology Corporation Semiconductor package substrate with embedded chip and fabrication method thereof
US20070262436A1 (en) * 2006-05-12 2007-11-15 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103871998A (en) * 2012-12-13 2014-06-18 珠海越亚封装基板技术股份有限公司 Single Layer Coreless Substrate
US8866286B2 (en) * 2012-12-13 2014-10-21 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Single layer coreless substrate
US9721922B2 (en) 2013-12-23 2017-08-01 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package

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