CN100487888C - 半导体器件、半导体晶片、半导体组件及半导体器件的制造方法 - Google Patents
半导体器件、半导体晶片、半导体组件及半导体器件的制造方法 Download PDFInfo
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- CN100487888C CN100487888C CNB991273842A CN99127384A CN100487888C CN 100487888 C CN100487888 C CN 100487888C CN B991273842 A CNB991273842 A CN B991273842A CN 99127384 A CN99127384 A CN 99127384A CN 100487888 C CN100487888 C CN 100487888C
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Abstract
Description
晶片的翘曲量(μm) | 封装的翘曲量(μm) | 1000次循环<sup>*1</sup>之后故障产生率(故障数/试验数) | |
E-1 | ≤5μm | ≤1μm | 0/100 |
E-2 | ≤5μm | ≤1μm | 0/100 |
E-3 | ≤5μm | ≤1μm | 0/100 |
E-4 | ≤5μm | ≤1μm | 0/100 |
E-5 | ≤5μm | ≤1μm | 0/100 |
E-6 | ≤5μm | ≤1μm | 0/100 |
E-7 | ≤5μm | ≤1μm | 0/100 |
E-8 | ≤5μm | ≤1μm | 0/100 |
E-9 | ≤5μm | ≤1μm | 0/100 |
E-10 | ≤5μm | ≤1μm | 0/100 |
E-11 | ≤5μm | ≤1μm | 0/100 |
C-1 | - | 5μm | 85/100 |
C-2 | - | ≤1μm | 20/100<sup>*3</sup> |
C-3 | 20μm | 5μm | 20/100 |
回流试验<sup>*2</sup>中的故障产生率(故障数量/试验数量) | 下降试验<sup>*4</sup>中的故障产生率(故障数量/试验数量) | 面积的比值(封装面积/芯片面积) | |
E-1 | 0/100 | 0/20 | 1 |
E-2 | 0/100 | 0/20 | 1 |
E-3 | 0/100 | 0/20 | 1 |
E-4 | 0/100 | 0/20 | 1 |
E-5 | 0/100 | 0/20 | 1 |
E-6 | 0/100 | 0/20 | 1 |
E-7 | 0/100 | 0/20 | 1 |
E-8 | 0/100 | 0/20 | 1 |
E-9 | 0/100 | 0/20 | 1 |
E-10 | 0/100 | 0/20 | 1 |
E-11 | 0/100 | 0/20 | 1 |
C-1 | 90/100 | 0/20 | 1.44 |
C-2 | 0/100*3 | 8/20 | 1.2 |
C-3 | 50/100 | 12/20 | 1 |
Claims (20)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP307554/1998 | 1998-10-28 | ||
JP30755498A JP3661444B2 (ja) | 1998-10-28 | 1998-10-28 | 半導体装置、半導体ウエハ、半導体モジュールおよび半導体装置の製造方法 |
JP307554/98 | 1998-10-28 |
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CN1260590A CN1260590A (zh) | 2000-07-19 |
CN100487888C true CN100487888C (zh) | 2009-05-13 |
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CNB991273842A Expired - Fee Related CN100487888C (zh) | 1998-10-28 | 1999-10-28 | 半导体器件、半导体晶片、半导体组件及半导体器件的制造方法 |
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US (2) | US6888230B1 (zh) |
JP (1) | JP3661444B2 (zh) |
KR (1) | KR100670751B1 (zh) |
CN (1) | CN100487888C (zh) |
MY (1) | MY125437A (zh) |
SG (1) | SG85141A1 (zh) |
TW (1) | TW445528B (zh) |
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-
1998
- 1998-10-28 JP JP30755498A patent/JP3661444B2/ja not_active Expired - Fee Related
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1999
- 1999-10-20 SG SG9905306A patent/SG85141A1/en unknown
- 1999-10-20 TW TW088118155A patent/TW445528B/zh not_active IP Right Cessation
- 1999-10-21 MY MYPI99004556A patent/MY125437A/en unknown
- 1999-10-22 KR KR1019990046103A patent/KR100670751B1/ko not_active IP Right Cessation
- 1999-10-28 CN CNB991273842A patent/CN100487888C/zh not_active Expired - Fee Related
- 1999-10-28 US US09/429,297 patent/US6888230B1/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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US20040217453A1 (en) | 2004-11-04 |
JP2000133683A (ja) | 2000-05-12 |
US6888230B1 (en) | 2005-05-03 |
US7217992B2 (en) | 2007-05-15 |
TW445528B (en) | 2001-07-11 |
SG85141A1 (en) | 2001-12-19 |
JP3661444B2 (ja) | 2005-06-15 |
KR100670751B1 (ko) | 2007-01-18 |
MY125437A (en) | 2006-08-30 |
CN1260590A (zh) | 2000-07-19 |
KR20000029261A (ko) | 2000-05-25 |
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