FR2806189B1 - Circuit integre renforce et procede de renforcement de circuits integres - Google Patents

Circuit integre renforce et procede de renforcement de circuits integres

Info

Publication number
FR2806189B1
FR2806189B1 FR0003089A FR0003089A FR2806189B1 FR 2806189 B1 FR2806189 B1 FR 2806189B1 FR 0003089 A FR0003089 A FR 0003089A FR 0003089 A FR0003089 A FR 0003089A FR 2806189 B1 FR2806189 B1 FR 2806189B1
Authority
FR
France
Prior art keywords
reinforcing
integrated circuit
reinforced
integrated circuits
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0003089A
Other languages
English (en)
Other versions
FR2806189A1 (fr
Inventor
Sophie Girard
Michel Gouiller
Stephane Provost
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Axalto SA
Original Assignee
Schlumberger Systemes SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Schlumberger Systemes SA filed Critical Schlumberger Systemes SA
Priority to FR0003089A priority Critical patent/FR2806189B1/fr
Priority to CNB018060072A priority patent/CN1165874C/zh
Priority to PCT/IB2001/000377 priority patent/WO2001067387A1/fr
Priority to EP01912057A priority patent/EP1261938A1/fr
Priority to JP2001565128A priority patent/JP2003526216A/ja
Priority to US10/221,245 priority patent/US20030038349A1/en
Publication of FR2806189A1 publication Critical patent/FR2806189A1/fr
Application granted granted Critical
Publication of FR2806189B1 publication Critical patent/FR2806189B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
FR0003089A 2000-03-10 2000-03-10 Circuit integre renforce et procede de renforcement de circuits integres Expired - Fee Related FR2806189B1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR0003089A FR2806189B1 (fr) 2000-03-10 2000-03-10 Circuit integre renforce et procede de renforcement de circuits integres
CNB018060072A CN1165874C (zh) 2000-03-10 2001-03-07 加强的集成电路
PCT/IB2001/000377 WO2001067387A1 (fr) 2000-03-10 2001-03-07 Circuit integre renforce
EP01912057A EP1261938A1 (fr) 2000-03-10 2001-03-07 Circuit integre renforce
JP2001565128A JP2003526216A (ja) 2000-03-10 2001-03-07 補強された集積回路
US10/221,245 US20030038349A1 (en) 2000-03-10 2001-03-07 Glycogen phosphorylase inhibitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0003089A FR2806189B1 (fr) 2000-03-10 2000-03-10 Circuit integre renforce et procede de renforcement de circuits integres

Publications (2)

Publication Number Publication Date
FR2806189A1 FR2806189A1 (fr) 2001-09-14
FR2806189B1 true FR2806189B1 (fr) 2002-05-31

Family

ID=8847951

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0003089A Expired - Fee Related FR2806189B1 (fr) 2000-03-10 2000-03-10 Circuit integre renforce et procede de renforcement de circuits integres

Country Status (6)

Country Link
US (1) US20030038349A1 (fr)
EP (1) EP1261938A1 (fr)
JP (1) JP2003526216A (fr)
CN (1) CN1165874C (fr)
FR (1) FR2806189B1 (fr)
WO (1) WO2001067387A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2817656B1 (fr) * 2000-12-05 2003-09-26 Gemplus Card Int Isolation electrique de microcircuits regroupes avant collage unitaire
EP1447844A3 (fr) * 2003-02-11 2004-10-06 Axalto S.A. Plaquette semiconductrice renforcée
JP2006245076A (ja) * 2005-03-01 2006-09-14 Matsushita Electric Ind Co Ltd 半導体装置

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59228743A (ja) * 1983-06-10 1984-12-22 Kyodo Printing Co Ltd Ｉｃカ−ド用ｉｃモジユ−ル
JPS61123990A (ja) * 1984-11-05 1986-06-11 Casio Comput Co Ltd Ｉｃカ−ド
US4841134A (en) * 1985-07-27 1989-06-20 Dai Nippon Insatsu Kabushika Kaisha IC card
US4701999A (en) * 1985-12-17 1987-10-27 Pnc, Inc. Method of making sealed housings containing delicate structures
FR2599165A1 (fr) * 1986-05-21 1987-11-27 Michot Gerard Objet associe a un element electronique et procede d'obtention
NL8601404A (nl) * 1986-05-30 1987-12-16 Papier Plastic Coating Groning Gegevensdragende kaart, werkwijze voor het vervaardigen van een dergelijke kaart en inrichting voor het uitvoeren van deze werkwijze.
US4700273A (en) * 1986-06-03 1987-10-13 Kaufman Lance R Circuit assembly with semiconductor expansion matched thermal path
EP0339763A3 (fr) * 1988-04-28 1990-04-25 Citizen Watch Co. Ltd. Carte à circuit intégré
FR2664721B1 (fr) * 1990-07-10 1992-09-25 Gemplus Card Int Carte a puce renforcee.
JPH04336448A (ja) * 1991-05-13 1992-11-24 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPH0567599A (ja) * 1991-09-06 1993-03-19 Mitsubishi Electric Corp 半導体装置の製造方法
US5581445A (en) * 1994-02-14 1996-12-03 Us3, Inc. Plastic integrated circuit card with reinforcement structure for protecting integrated circuit module
JPH0883861A (ja) * 1994-07-12 1996-03-26 Nitto Denko Corp 半導体パッケージ被覆用金属箔材料および半導体装置
JPH08316411A (ja) * 1995-05-18 1996-11-29 Hitachi Ltd 半導体装置
JPH08324166A (ja) * 1995-05-30 1996-12-10 Toppan Printing Co Ltd Ｉｃカード用モジュール及びｉｃカード
JP3496347B2 (ja) * 1995-07-13 2004-02-09 株式会社デンソー 半導体装置及びその製造方法
JPH09232475A (ja) * 1996-02-22 1997-09-05 Nitto Denko Corp 半導体装置及びその製造方法
US5956605A (en) * 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
JP3045107B2 (ja) * 1997-06-20 2000-05-29 日本電気株式会社 固体撮像素子の組立方法
EP0919950B1 (fr) * 1997-06-23 2007-04-04 Rohm Co., Ltd. Module pour carte a circuit integre, carte a circuit integre, et procede de fabrication d'un tel module
JP3914620B2 (ja) * 1997-10-16 2007-05-16 シチズン時計株式会社 Ｉｃカード
US6441487B2 (en) * 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
US5920769A (en) * 1997-12-12 1999-07-06 Micron Technology, Inc. Method and apparatus for processing a planar structure
FR2774197B1 (fr) * 1998-01-26 2001-11-23 Rue Cartes Et Systemes De Procede de fabrication d'une carte a microcircuit et carte obtenue par la mise en oeuvre de ce procede
JP3497722B2 (ja) * 1998-02-27 2004-02-16 富士通株式会社 半導体装置及びその製造方法及びその搬送トレイ
TW407364B (en) * 1998-03-26 2000-10-01 Toshiba Corp Memory apparatus, card type memory apparatus, and electronic apparatus
US6008070A (en) * 1998-05-21 1999-12-28 Micron Technology, Inc. Wafer level fabrication and assembly of chip scale packages
JP3982082B2 (ja) * 1998-09-28 2007-09-26 ソニー株式会社 半導体装置の製造方法
US6504241B1 (en) * 1998-10-15 2003-01-07 Sony Corporation Stackable semiconductor device and method for manufacturing the same
JP3661444B2 (ja) * 1998-10-28 2005-06-15 株式会社ルネサステクノロジ 半導体装置、半導体ウエハ、半導体モジュールおよび半導体装置の製造方法
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6498387B1 (en) * 2000-02-15 2002-12-24 Wen-Ken Yang Wafer level package and the process of the same

Also Published As

Publication number Publication date
CN1165874C (zh) 2004-09-08
FR2806189A1 (fr) 2001-09-14
WO2001067387A1 (fr) 2001-09-13
JP2003526216A (ja) 2003-09-02
US20030038349A1 (en) 2003-02-27
EP1261938A1 (fr) 2002-12-04
CN1411589A (zh) 2003-04-16

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Legal Events

Date Code Title Description
ST Notification of lapse