CN1411589A - 加强的集成电路 - Google Patents
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Abstract
本发明涉及一种集成电路,该集成电路具有其中带端子焊点(3)的工作表面(2)和与工作表面相反的非工作表面(4)。相应的加强片(5、6)覆盖集成电路的各表面。本发明也提供了一种加强集成电路的方法。
Description
技术领域
本发明涉及一种加强的集成电路以及加强集成电路的方法。本发明尤其可用于诸如象银行信用卡或电话卡、赊购卡之类的接触或非接触卡的便携物品领域,或是集成电路标签领域内的物品中。
背景技术
集成电路一般由硅片制成,硅片具有包括端子焊点的工作表面和与工作表面相反的非工作表面。硅是相对脆的材料,并且在承受冲击和弯曲应力方面较弱。
在植入卡中的集成电路方面,该集成电路一般首先粘结到一个支撑物上,并连接到固定于该支撑物上的导体区域上,由此形成一个模块。然后,该集成电路封装在与加强相关的一块树脂中,由此改善了该模块的强度并保护集成电路和导电区域之间的连接。尽管如此,这种模块制造起来相对昂贵。另外,此模块结构不太适于特定类型的卡(尤其是薄卡),且不太适于标签,并且不太适合于制造他们的特定方法。
集成电路承受弯曲的能力的问题由于在实用中存在于卡中的集成电路其面积趋于增大而其厚度趋于减小这个事实而愈发恶化。
发明内容
本发明的目的是提供一种用于增大集成电路机械强度的装置。
本发明是通过提供一种如下的集成电路来实现这个目的的,即,该集成电路包括具有端子焊点的工作表面和与工作表面相反的非工作表面、覆盖集成电路每个表面的加强片。
加强片给集成电路赋予了抵抗弯曲的良好的强度,并且他们保护集成电路的他们所覆盖的表面不受冲击。以这种方式加强的集成电路易于植入薄卡中和植入标签中。另外,该集成电路然后可以放置在卡体厚度中靠近卡的中性纤维(neutral fiber)的位置处。这就约束了集成电路易于遭遇的弯曲应力。
优选地是,加强片借助于一层粘结剂固定到集成电路相应的表面上。粘结剂层优选地为足以适应加强片和集成电路之间膨胀变化的厚度。这使得正确利用具有不同于构成集成电路的材料的膨胀系数的加强片成为可能。
本发明也提供了一种加强集成电路的方法,其中集成电路分别具有包括端子焊点的工作表面和与工作表面相反的非工作表面,该方法包括以下步骤:
将加强片淀积到集成电路的每个表面上,同时集成电路彼此以晶片形式关联;
通过切割晶片而分别处理集成电路。
从而,以单独一次操作,可以将数以百计的集成电路覆盖在加强片中。另外,由于分别处理集成电路时加强片与晶片同时切割,因此每个加强片精确地定位在相应地集成电路上。最后,加强片在其切割之前提高了晶片地强度,并且防止可能在晶片切割时产生地裂缝扩散。
附图说明
本发明地其他特征和优点将在阅读以下对本发明地特定非限定实施例地描述时得以清楚。
参照附图,图中:
图1是通过构成本发明第一实施例的集成电路的横截面图;
图2是包括第一实施例的集成电路的晶片的平面图;
图3是包括构成本发明第二实施例的集成电路的晶片的横截面图。
具体实施方式
参照附图,如传统方式,集成电路1包括硅片,该硅片呈现出其中带有端子焊点3的工作表面2和与工作表面2相反的非工作表面4。
更详细的参照图1和图2,并根据本发明,加强片5和6借助于相应的粘结剂层7、8分别固定到集成电路的工作表面2和非工作表面4上。
在这种情况下,加强片5和6由诸如镍和铜的金属制成,并且他们大约100微米(μm)厚。
粘结剂层7和8厚度足以补偿存在于加强片5和6的金属与硅之间的膨胀的变化,并足以包容由这种膨胀变化产生的应力。从而,硅具有10-7数量级的膨胀系数,而铜加强片具有大约10-6数量级的膨胀系数。在这种条件下,有可能借助于膨胀系数为10-3和10-4数量级的粘结剂并将其扩展到几十微米左右的厚度来形成粘结剂层6、8。
覆盖工作表面2的加强片5和粘结剂层7在与端子焊点3对齐处呈现出开口9、10。
集成电路1得以加强,同时集成电路1仍然与其他以总地用附图标记11标示并且承载几百个集成电路的晶片的形式的集成电路相关联。
加强片5和6被切割成晶片的尺寸,而开口9通过光刻加强片5而形成。
集成电路1的工作表面2覆盖在感光粘结剂树脂中而形成粘结剂层7,集成电路1的非工作面4覆盖在粘结剂树脂中而形成粘结剂层8。对于每个粘结剂层7、8,树脂可以利用旋涂方法沉积到相应的晶片11的表面2、4上,该旋涂方法包括将晶片11设定为转动,并将树脂倾倒到相应的表面上,从而树脂在离心力的作用下在晶片11的表面上扩散。
然后,通过将加强片5和6施加到相应的粘结剂层7和8上而在初始真空(primary vacuum)下将加强片粘结到位。在初始真空下工作使得可以确保粘结剂层中不形成气泡。为了相同的目的,也有可能使微小的穿孔例如借助于激光穿过加强片5和6形成,从而使得封闭在加强片和粘结剂层之间的空气得以溢出。在加强片5粘结到位的同时,加强片5中的开口9放置成与晶片11上的端子焊点3对齐。
如果所用的树脂是加热时可再次活化的,那么粘结剂层在加强片5和6施加的同时加热。
然后除去与端子焊点3对齐的形成粘结剂层7的树脂,从而形成开口10。树脂可以例如以传统方式通过将粘结剂层7经由加强片5曝光于紫外光,然后借助于仅作用于粘结剂层7上已经被曝光的那些区域,即,与开口9对齐的那些区域,的溶剂蚀刻来予以去除,其中加强片5由此形成一个掩膜。
在第一种变型中,树脂层7也可以利用丝网通过丝网印刷沉积在集成电路1的晶片11上,从而端子焊点3不会覆盖在形成粘结剂层7的树脂中。
在第二种变型中,粘结剂层7可以由包含导电颗粒的树脂形成,该导电颗粒使粘结剂层7电各向异性,从而粘结剂层7的与端子焊点3对齐定位的区域可以通过在加热同时沿一个方向挤压树脂而使之局部导电,其中该方向垂直于端子焊点3。
在第三种变型中,粘结剂层7、8可以由通过热压施加到晶片11的工作表面2和非工作表面4上或否则施加到加强片5和6上的粘结剂薄膜形成。加强片5和6然后分别热压到晶片11的工作表面2和非工作表面4上。
一旦加强片5和6已经固定到晶片11的表面2和4上,晶片以传统方式切割,以分别处理集成电路。为了利于这个操作,可以采取如下的措施,即,将加强片5和6形成为具有沿着切割工具和锯将要跟随的路径延伸的厚度减小的区域。
在变型中,该方法可以包括在固定加强片6之前自集成电路的非工作表面减小其厚度的步骤。作为示例,这个步骤可以通过抛光非工作表面来执行。这使得加强后的集成电路具有与未加强的集成电路相类似的厚度成为可能。
在下面对本发明第二实施例的描述中,与上述相同或相类似的元件被赋予以相同的附图标记。
参照图3,接线柱12在集成电路1仍然以晶片11形式彼此相关联的同时形成在集成电路1的端子焊点3上。接线柱12可以通过丝网印刷制成。那么用于形成接线柱12的材料为银填充的聚合物或焊膏。接线柱12也可以通过电化学生长方法形成。
用于形成粘结剂层7的树脂为电绝缘的,并且其利用旋涂工艺沉积在晶片11的集成电路1的工作表面2上。粘结剂层7的深度小于接线柱12的高度。
加强片5具有事先形成在其中的开口9,以接收接线柱12,然后加强片通过热压在粘结剂层7上而施加。在这种情况下,加强片5由绝缘材料,如热塑材料制成。接线柱12稍微从加强片5中突出。
加强片6放置到位,并且晶片11以与前面相同的方式切割,而分别处理集成电路1。
当然,本发明不局限于所述的实施例,在不超出如权利要求所限定的本发明范围前提下可以对其作出变动。
尤其是,图1中的集成电路的加强片5和6可以由不同金属制成,更广义地说,可以由不同材料制成。用于形成加强片5和6的材料优选地是具有相等机械特性(例如,膨胀系数相似)的材料,从而有可能确保集成电路和晶片在温度升高作用下不会象双金属片一样翘曲。加强片5和6也可以为不同的厚度。从而,两个加强片的厚度和可以大于或等于未加强的集成电路。
Claims (12)
1.一种用于获得智能卡型便携物品的集成电路,该集成电路具有其中带端子焊点(3)的工作表面(2)和与工作表面相对的非工作表面(4),其特征在于,加强片(5、6)覆盖集成电路的每个表面。
2.如权利要求1所述的集成电路,其特征在于,每个加强片(5、6)借助于一层粘结剂(7、8)固定到集成电路(1)的相应表面(2、4)上。
3.如权利要求2所述的集成电路,其特征在于,每层粘结剂(7、8)的厚度足以补偿相应的加强片(5、6)和集成电路(1)之间的膨胀变化。
4.如权利要求1到3中任一项所述的集成电路,其特征在于,工作表面(2)的端子焊点(3)设置有从加强片(5)突出的接线柱(12)。
5.如权利要求1到4中任一项所述的集成电路,其特征在于,至少一个加强片(5、6)由金属制成。
6.如上述权利要求中任一项所述的集成电路,其特征在于,加强片(5、6)具有类似的机械特性,如类似的膨胀系数。
7.如上述权利要求中任一项所述的集成电路,其特征在于,加强片(5、6)基本上厚度相同。
8.一种加强集成电路(1)的方法,该集成电路分别具有其中带端子焊点(3)的工作表面(2)和与工作表面相反的非工作表面(4),其特征在于,该方法包括以下步骤:
在集成电路以晶片(11)形式彼此相关联时将加强片(5、6)沉积到集成电路的每个表面上;以及
通过切割晶片来分别处理集成电路。
9.如权利要求8所述的方法,其特征在于,至少一个加强片(5、6)通过在初始真空下粘结而固定。
10.如权利要求8和9所述的方法,在将加强片(5)固定到集成电路工作表面(2)上的方面,所述加强片具有用于与端子焊点(3)对齐放置的开口(9),其特征在于,加强片通过借助于一层感光粘结剂(7)粘结于工作表面上而固定到后者上,并且在加强片已经粘结到位后,粘结剂层曝光于穿过其的辐射,而粘结剂层被曝光的区域借助于溶剂蚀刻。
11.如权利要求8和9所述的方法,在将加强片(5)固定到集成电路工作表面(2)上的方面,所述加强片具有用于与端子焊点(3)对齐放置的开口(9),其特征在于,加强片通过借助于粘结剂层(7)粘结到工作表面上而固定到后者上,粘结剂层(7)在端子焊点(3)上已经形成接线柱(12)之后扩散在工作表面上,粘结剂层的厚度小于接线柱的高度。
12.如权利要求8到11中任一项所述的方法,其特征在于,该方法包括在将加强片(6)沉积到非工作表面(4)上之前从集成电路的非工作表面(4)减小集成电路的厚度的步骤。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0003089A FR2806189B1 (fr) | 2000-03-10 | 2000-03-10 | Circuit integre renforce et procede de renforcement de circuits integres |
FR00/03089 | 2000-03-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1411589A true CN1411589A (zh) | 2003-04-16 |
CN1165874C CN1165874C (zh) | 2004-09-08 |
Family
ID=8847951
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB018060072A Expired - Fee Related CN1165874C (zh) | 2000-03-10 | 2001-03-07 | 加强的集成电路 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20030038349A1 (zh) |
EP (1) | EP1261938A1 (zh) |
JP (1) | JP2003526216A (zh) |
CN (1) | CN1165874C (zh) |
FR (1) | FR2806189B1 (zh) |
WO (1) | WO2001067387A1 (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2817656B1 (fr) * | 2000-12-05 | 2003-09-26 | Gemplus Card Int | Isolation electrique de microcircuits regroupes avant collage unitaire |
EP1447844A3 (en) * | 2003-02-11 | 2004-10-06 | Axalto S.A. | Reinforced semiconductor wafer |
JP2006245076A (ja) * | 2005-03-01 | 2006-09-14 | Matsushita Electric Ind Co Ltd | 半導体装置 |
Family Cites Families (32)
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JPS59228743A (ja) * | 1983-06-10 | 1984-12-22 | Kyodo Printing Co Ltd | Icカ−ド用icモジユ−ル |
JPS61123990A (ja) * | 1984-11-05 | 1986-06-11 | Casio Comput Co Ltd | Icカ−ド |
US4841134A (en) * | 1985-07-27 | 1989-06-20 | Dai Nippon Insatsu Kabushika Kaisha | IC card |
US4701999A (en) * | 1985-12-17 | 1987-10-27 | Pnc, Inc. | Method of making sealed housings containing delicate structures |
FR2599165A1 (fr) * | 1986-05-21 | 1987-11-27 | Michot Gerard | Objet associe a un element electronique et procede d'obtention |
NL8601404A (nl) * | 1986-05-30 | 1987-12-16 | Papier Plastic Coating Groning | Gegevensdragende kaart, werkwijze voor het vervaardigen van een dergelijke kaart en inrichting voor het uitvoeren van deze werkwijze. |
US4700273A (en) * | 1986-06-03 | 1987-10-13 | Kaufman Lance R | Circuit assembly with semiconductor expansion matched thermal path |
EP0339763A3 (en) * | 1988-04-28 | 1990-04-25 | Citizen Watch Co. Ltd. | Ic card |
FR2664721B1 (fr) * | 1990-07-10 | 1992-09-25 | Gemplus Card Int | Carte a puce renforcee. |
JPH04336448A (ja) * | 1991-05-13 | 1992-11-24 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH0567599A (ja) * | 1991-09-06 | 1993-03-19 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US5581445A (en) * | 1994-02-14 | 1996-12-03 | Us3, Inc. | Plastic integrated circuit card with reinforcement structure for protecting integrated circuit module |
JPH0883861A (ja) * | 1994-07-12 | 1996-03-26 | Nitto Denko Corp | 半導体パッケージ被覆用金属箔材料および半導体装置 |
JPH08316411A (ja) * | 1995-05-18 | 1996-11-29 | Hitachi Ltd | 半導体装置 |
JPH08324166A (ja) * | 1995-05-30 | 1996-12-10 | Toppan Printing Co Ltd | Icカード用モジュール及びicカード |
JP3496347B2 (ja) * | 1995-07-13 | 2004-02-09 | 株式会社デンソー | 半導体装置及びその製造方法 |
JPH09232475A (ja) * | 1996-02-22 | 1997-09-05 | Nitto Denko Corp | 半導体装置及びその製造方法 |
US5956605A (en) * | 1996-09-20 | 1999-09-21 | Micron Technology, Inc. | Use of nitrides for flip-chip encapsulation |
JP3045107B2 (ja) * | 1997-06-20 | 2000-05-29 | 日本電気株式会社 | 固体撮像素子の組立方法 |
US6607135B1 (en) * | 1997-06-23 | 2003-08-19 | Rohm Co., Ltd. | Module for IC card, IC card, and method for manufacturing module for IC card |
JP3914620B2 (ja) * | 1997-10-16 | 2007-05-16 | シチズン時計株式会社 | Icカード |
US6441487B2 (en) * | 1997-10-20 | 2002-08-27 | Flip Chip Technologies, L.L.C. | Chip scale package using large ductile solder balls |
US5920769A (en) * | 1997-12-12 | 1999-07-06 | Micron Technology, Inc. | Method and apparatus for processing a planar structure |
FR2774197B1 (fr) * | 1998-01-26 | 2001-11-23 | Rue Cartes Et Systemes De | Procede de fabrication d'une carte a microcircuit et carte obtenue par la mise en oeuvre de ce procede |
JP3497722B2 (ja) * | 1998-02-27 | 2004-02-16 | 富士通株式会社 | 半導体装置及びその製造方法及びその搬送トレイ |
TW407364B (en) * | 1998-03-26 | 2000-10-01 | Toshiba Corp | Memory apparatus, card type memory apparatus, and electronic apparatus |
US6008070A (en) * | 1998-05-21 | 1999-12-28 | Micron Technology, Inc. | Wafer level fabrication and assembly of chip scale packages |
JP3982082B2 (ja) * | 1998-09-28 | 2007-09-26 | ソニー株式会社 | 半導体装置の製造方法 |
KR20000029054A (ko) * | 1998-10-15 | 2000-05-25 | 이데이 노부유끼 | 반도체 장치 및 그 제조 방법 |
JP3661444B2 (ja) * | 1998-10-28 | 2005-06-15 | 株式会社ルネサステクノロジ | 半導体装置、半導体ウエハ、半導体モジュールおよび半導体装置の製造方法 |
US6181569B1 (en) * | 1999-06-07 | 2001-01-30 | Kishore K. Chakravorty | Low cost chip size package and method of fabricating the same |
US6498387B1 (en) * | 2000-02-15 | 2002-12-24 | Wen-Ken Yang | Wafer level package and the process of the same |
-
2000
- 2000-03-10 FR FR0003089A patent/FR2806189B1/fr not_active Expired - Fee Related
-
2001
- 2001-03-07 US US10/221,245 patent/US20030038349A1/en not_active Abandoned
- 2001-03-07 WO PCT/IB2001/000377 patent/WO2001067387A1/en active Application Filing
- 2001-03-07 EP EP01912057A patent/EP1261938A1/en not_active Withdrawn
- 2001-03-07 CN CNB018060072A patent/CN1165874C/zh not_active Expired - Fee Related
- 2001-03-07 JP JP2001565128A patent/JP2003526216A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JP2003526216A (ja) | 2003-09-02 |
FR2806189B1 (fr) | 2002-05-31 |
CN1165874C (zh) | 2004-09-08 |
US20030038349A1 (en) | 2003-02-27 |
WO2001067387A1 (en) | 2001-09-13 |
FR2806189A1 (fr) | 2001-09-14 |
EP1261938A1 (en) | 2002-12-04 |
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